[RISCV] Optimize immediate materialisation with SLLI.UW

[benshi001]

Summary

Simplify "LUI+SLLI+ADDI+SLLI" and "LUI+ADDIW+SLLI+ADDI+SLLI" to

"LUI+ADDIW+SLLIUW" to reduce total instruction amount.

[craig.topper]

Your description is not accurate. You’re not replacing LUI+ADDI+SLLI. You’re replacing LUI+SLLI+ADDI+SLLI.

[benshi001]

In D111933#3068373, @craig.topper wrote:

Your description is not accurate. You’re not replacing LUI+ADDI+SLLI. You’re replacing LUI+SLLI+ADDI+SLLI.

I should add more tests, sometimes my patch can reduce two instructions, for example

long ass() {
        return 0xbbbbb111777;
}

The original instructions are

lui a0, 188
addiw a0, a0, -1093
slli  a0, a0, 12
addi  a0, a0, 273
slli  a0, a0, 12
addi  a0, a0, 1911
ret

which can be optimized by my patch to

lui a0, 768955
addiw a0, a0, 273
slli.uw a0, a0, 12
addi  a0, a0, 1911
ret

[benshi001]

In D111933#3068373, @craig.topper wrote:

Your description is not accurate. You’re not replacing LUI+ADDI+SLLI. You’re replacing LUI+SLLI+ADDI+SLLI.

So how about change the description to "Use LUI+ADDI+SLLI.UW to reduce multiple SLLI+ADDI pairs" ?

[benshi001]

ping ... This would be the last patch of immediate materialisation optimization with the B extension. Can it be merged?

[craig.topper]

LGTM

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

 static int getInstSeqCost(RISCVMatInt::InstSeq &Res, bool HasRVC) {
   if (!HasRVC)
     return Res.size();
 
   int Cost = 0;
   for (auto Instr : Res) {
     bool Compressed;
     switch (Instr.Opc) {
-    default: llvm_unreachable("Unexpected opcode");
+    default:
+      llvm_unreachable("Unexpected opcode");
     case RISCV::SLLI:
     case RISCV::SRLI:
       Compressed = true;
       break;
     case RISCV::ADDI:
     case RISCV::ADDIW:
     case RISCV::LUI:
       Compressed = isInt<6>(Instr.Imm);
if (isInt<32>((uint64_t)Hi52 << 12)) {
       // Reduce the shift amount and add zeros to the LSBs so it will match
       // LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
       ShiftAmount -= 12;
       Hi52 = ((uint64_t)Hi52 << 12) | (0xffffffffull << 32);
       Unsigned = true;
     }
   }
 
+  // Try to use SLLIUW for Hi52 when it is uint32 but not int32.
+  if (isUInt<32>((uint64_t)Hi52) && !isInt<32>((uint64_t)Hi52) &&
+      ActiveFeatures[RISCV::FeatureStdExtZba]) {
+    // Use LUI+ADDI or LUI to compose, then clear the upper 32 bits with SLLIUW.
+    Hi52 = ((uint64_t)Hi52) | (0xffffffffull << 32);
+    Unsigned = true;
+  }
+
   generateInstSeqImpl(Hi52, ActiveFeatures, Res);
 
   if (Unsigned)
     Res.push_back(RISCVMatInt::Inst(RISCV::SLLIUW, ShiftAmount));
   else
     Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount));
   if (Lo12)
     Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12));
if (Div > 0) {
         Res = TmpSeq;
     }
   }
 
   return Res;
 }
 
 int getIntMatCost(const APInt &Val, unsigned Size,
-                  const FeatureBitset &ActiveFeatures,
-                  bool CompressionCost) {
+                  const FeatureBitset &ActiveFeatures, bool CompressionCost) {
   bool IsRV64 = ActiveFeatures[RISCV::Feature64Bit];
   bool HasRVC = CompressionCost && ActiveFeatures[RISCV::FeatureStdExtC];
   int PlatRegSize = IsRV64 ? 64 : 32;
 
   // Split the constant into platform register sized chunks, and calculate cost
   // of each chunk.
   int Cost = 0;
   for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {
     APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
     InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), ActiveFeatures);
     Cost += getInstSeqCost(MatSeq, HasRVC);
   }
   return std::max(1, Cost);
 }
 } // namespace RISCVMatInt
 } // namespace llvm

llvm/test/CodeGen/RISCV/imm.ll

 ; RV64I-NEXT:    slli a0, a0, 2
 ; RV64I-NEXT:    addi a0, a0, -1093
 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    addi a0, a0, 1911
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_12900936431479:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 192239
-; RV64IZBA-NEXT:    slli a0, a0, 2
-; RV64IZBA-NEXT:    addi a0, a0, -1093
-; RV64IZBA-NEXT:    slli a0, a0, 12
+; RV64IZBA-NEXT:    lui a0, 768956
+; RV64IZBA-NEXT:    addiw a0, a0, -1093
+; RV64IZBA-NEXT:    slli.uw a0, a0, 12
 ; RV64IZBA-NEXT:    addi a0, a0, 1911
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_12900936431479:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 192239
 ; RV64IZBS-NEXT:    slli a0, a0, 2
 ; RV64IZBS-NEXT:    addi a0, a0, -1093

 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    addi a0, a0, -1365
 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    addi a0, a0, -1366
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_12900918536874:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 188
-; RV64IZBA-NEXT:    addiw a0, a0, -1093
-; RV64IZBA-NEXT:    slli a0, a0, 12
-; RV64IZBA-NEXT:    addi a0, a0, -1365
-; RV64IZBA-NEXT:    slli a0, a0, 12
+; RV64IZBA-NEXT:    lui a0, 768955
+; RV64IZBA-NEXT:    addiw a0, a0, -1365
+; RV64IZBA-NEXT:    slli.uw a0, a0, 12
 ; RV64IZBA-NEXT:    addi a0, a0, -1366
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_12900918536874:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 188
 ; RV64IZBS-NEXT:    addiw a0, a0, -1093
 ; RV64IZBS-NEXT:    slli a0, a0, 12

 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    addi a0, a0, 273
 ; RV64I-NEXT:    slli a0, a0, 12
 ; RV64I-NEXT:    addi a0, a0, 273
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_12900925247761:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 188
-; RV64IZBA-NEXT:    addiw a0, a0, -1093
-; RV64IZBA-NEXT:    slli a0, a0, 12
-; RV64IZBA-NEXT:    addi a0, a0, 273
-; RV64IZBA-NEXT:    slli a0, a0, 12
+; RV64IZBA-NEXT:    lui a0, 768955
+; RV64IZBA-NEXT:    addiw a0, a0, 273
+; RV64IZBA-NEXT:    slli.uw a0, a0, 12
 ; RV64IZBA-NEXT:    addi a0, a0, 273
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_12900925247761:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 188
 ; RV64IZBS-NEXT:    addiw a0, a0, -1093
 ; RV64IZBS-NEXT:    slli a0, a0, 12
 ; RV64IZBS-NEXT:    addi a0, a0, 273
 ; RV64IZBS-NEXT:    slli a0, a0, 12
 ; RV64IZBS-NEXT:    addi a0, a0, 273
 ; RV64IZBS-NEXT:    ret
   ret i64 12900925247761
 }

llvm/test/MC/RISCV/rv64zba-aliases-valid.s

 # CHECK-S-OBJ-NOALIAS: lui t1, 611378
 # CHECK-S-OBJ-NOALIAS-NEXT: addiw t1, t1, 265
 # CHECK-S-OBJ-NOALIAS-NEXT: sh3add t1, t1, t1
 # CHECK-S-OBJ: lui t1, 611378
 # CHECK-S-OBJ-NEXT: addiw t1, t1, 265
 # CHECK-S-OBJ-NEXT: sh3add t1, t1, t1
 li x6, -16116864687
 
-# CHECK-S-OBJ-NOALIASZBS: lui t2, 192239
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t2, t2, 2
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addi t2, t2, -1093
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t2, t2, 12
+# CHECK-S-OBJ-NOALIASZBS: lui t2, 768956
+# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t2, t2, -1093
+# CHECK-S-OBJ-NOALIASZBS-NEXT: slli.uw t2, t2, 12
 # CHECK-S-OBJ-NOALIASZBS-NEXT: addi t2, t2, 1911
-# CHECK-S-OBJ: lui t2, 192239
-# CHECK-S-OBJ-NEXT: slli t2, t2, 2
-# CHECK-S-OBJ-NEXT: addi t2, t2, -1093
-# CHECK-S-OBJ-NEXT: slli t2, t2, 12
+# CHECK-S-OBJ: lui t2, 768956
+# CHECK-S-OBJ-NEXT: addiw t2, t2, -1093
+# CHECK-S-OBJ-NEXT: slli.uw t2, t2, 12
 # CHECK-S-OBJ-NEXT: addi t2, t2, 1911
 li x7, 12900936431479
 
-# CHECK-S-OBJ-NOALIASZBS: lui t1, 188
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t1, t1, -1093
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t1, t1, 12
+# CHECK-S-OBJ-NOALIASZBS: lui t1, 768955
+# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t1, t1, 273
+# CHECK-S-OBJ-NOALIASZBS-NEXT: slli.uw t1, t1, 12
 # CHECK-S-OBJ-NOALIASZBS-NEXT: addi t1, t1, 273
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t1, t1, 12
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addi t1, t1, 273
-# CHECK-S-OBJ: lui t1, 188
-# CHECK-S-OBJ-NEXT: addiw t1, t1, -1093
-# CHECK-S-OBJ-NEXT: slli t1, t1, 12
-# CHECK-S-OBJ-NEXT: addi t1, t1, 273
-# CHECK-S-OBJ-NEXT: slli t1, t1, 12
+# CHECK-S-OBJ: lui t1, 768955
+# CHECK-S-OBJ-NEXT: addiw t1, t1, 273
+# CHECK-S-OBJ-NEXT: slli.uw t1, t1, 12
 # CHECK-S-OBJ-NEXT: addi t1, t1, 273
 li x6, 12900925247761
 
-# CHECK-S-OBJ-NOALIASZBS: lui t1, 188
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t1, t1, -1093
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t1, t1, 12
-# CHECK-S-OBJ-NOALIASZBS-NEXT: addi t1, t1, -1365
-# CHECK-S-OBJ-NOALIASZBS-NEXT: slli t1, t1, 12
+# CHECK-S-OBJ-NOALIASZBS: lui t1, 768955
+# CHECK-S-OBJ-NOALIASZBS-NEXT: addiw t1, t1, -1365
+# CHECK-S-OBJ-NOALIASZBS-NEXT: slli.uw t1, t1, 12
 # CHECK-S-OBJ-NOALIASZBS-NEXT: addi t1, t1, -1366
-# CHECK-S-OBJ: lui t1, 188
-# CHECK-S-OBJ-NEXT: addiw t1, t1, -1093
-# CHECK-S-OBJ-NEXT: slli t1, t1, 12
-# CHECK-S-OBJ-NEXT: addi t1, t1, -1365
-# CHECK-S-OBJ-NEXT: slli t1, t1, 12
+# CHECK-S-OBJ: lui t1, 768955
+# CHECK-S-OBJ-NEXT: addiw t1, t1, -1365
+# CHECK-S-OBJ-NEXT: slli.uw t1, t1, 12
 # CHECK-S-OBJ-NEXT: addi t1, t1, -1366
 li x6, 12900918536874