[WIP][X86] Update CPU_SPECIFIC list.

[FreddyYe]

Summary

[Notice] This is a work in progress patch.

This patch is to support cpu_specific() function multiversioning for the latest X86 cpu.
Meanwhile update attr-target-mv.c with missing cpu test.

[FreddyYe]

As mentioned before:

In D108422#2957528, @RKSimon wrote:

There's nothing later than CannonLake here - does Intel need to at least reference up to Tiger/Rocketlake?

I met some issues to discuss with you.

1. The feature list now I added is got from the output of -march=XXX. This version should work right with many cpus added above. But some of them don't(Functional issue). I dig a little and found it's caused beyond this table. And the issue already exists in the old CPU added before. For example, "core_i7_sse4_2" and "goldmont" only has one feature differs: which is "movbe", but "movebe" is not included in the table of __cpu_features in libgcc (The table is the same as the one in compiler-rt, which is enum ProcessorFeatures), so these two CPU_SPECIFIC won't be classified on run time.
2. Naming convention issue. -march=goldmont-plus v.s cpu_specific(goldmont_plus). From my test, CPU_SPECIFIC probably needs other changes to support "goldmont-plus".
3. We probably need to document somewhere for all the supported CPU names on this function multiversioning.
4. CPU_SPECIFIC_ALIAS() issue. For now, CPUs defined by CPU_SPECIFIC_ALIAS is not allowed to used together with original CPU(e.g. __attribute__((cpu_specific(sandybridge))) and __attribute__((cpu_specific(core_2nd_gen_avx)))), which introduces compile error. Not sure if it is expected.

[erichkeane]

Supporting these types requires changes to the library so that we can check these, right? Do you have the library changes for these as well? The constants used to check for these features/etc needs to be present in the glibc library.

[FreddyYe]

In D111778#3063891, @erichkeane wrote:

Supporting these types requires changes to the library so that we can check these, right? Do you have the library changes for these as well? The constants used to check for these features/etc needs to be present in the glibc library.

Yes. It's highly related to the ProcessorFeatures I mentioned above. Does the library changes refer to the compiler-rt/cpu_model.c? I think that change depends on libgcc. For now libgcc has no strong will to update that table.

[craig.topper]

In D111778#3064287, @FreddyYe wrote:

In D111778#3063891, @erichkeane wrote:

Supporting these types requires changes to the library so that we can check these, right? Do you have the library changes for these as well? The constants used to check for these features/etc needs to be present in the glibc library.

Yes. It's highly related to the ProcessorFeatures I mentioned above. Does the library changes refer to the compiler-rt/cpu_model.c? I think that change depends on libgcc. For now libgcc has no strong will to update that table.

Every feature gcc knows about should be in libgcc. The unfortunate problem now is that cpu_features2 in libgcc is an array thats size may be different with every version of gcc. Clang can’t know how big that array is without reading the libgcc.a symbol table at compile time. Without knowing the size we can’t access any bits past the first 32 bits of cpu_features2.

[erichkeane]

In D111778#3064439, @craig.topper wrote:

In D111778#3064287, @FreddyYe wrote:

In D111778#3063891, @erichkeane wrote:

Supporting these types requires changes to the library so that we can check these, right? Do you have the library changes for these as well? The constants used to check for these features/etc needs to be present in the glibc library.

Yes. It's highly related to the ProcessorFeatures I mentioned above. Does the library changes refer to the compiler-rt/cpu_model.c? I think that change depends on libgcc. For now libgcc has no strong will to update that table.

Every feature gcc knows about should be in libgcc. The unfortunate problem now is that cpu_features2 in libgcc is an array thats size may be different with every version of gcc. Clang can’t know how big that array is without reading the libgcc.a symbol table at compile time. Without knowing the size we can’t access any bits past the first 32 bits of cpu_features2.

libgcc entries are the ones I was concerned about. We need to make sure this list matches that one (and we don't generate checks that it does not have). @craig.topper can better clarify what needs to happen with the library lookup, but I THINK we keep a version of this in compiler-rt instead of using libgcc?

[craig.topper]

In D111778#3064555, @erichkeane wrote:

In D111778#3064439, @craig.topper wrote:

In D111778#3064287, @FreddyYe wrote:

In D111778#3063891, @erichkeane wrote:

Supporting these types requires changes to the library so that we can check these, right? Do you have the library changes for these as well? The constants used to check for these features/etc needs to be present in the glibc library.

Yes. It's highly related to the ProcessorFeatures I mentioned above. Does the library changes refer to the compiler-rt/cpu_model.c? I think that change depends on libgcc. For now libgcc has no strong will to update that table.

Every feature gcc knows about should be in libgcc. The unfortunate problem now is that cpu_features2 in libgcc is an array thats size may be different with every version of gcc. Clang can’t know how big that array is without reading the libgcc.a symbol table at compile time. Without knowing the size we can’t access any bits past the first 32 bits of cpu_features2.

libgcc entries are the ones I was concerned about. We need to make sure this list matches that one (and we don't generate checks that it does not have). @craig.topper can better clarify what needs to happen with the library lookup, but I THINK we keep a version of this in compiler-rt instead of using libgcc?

I don't know what needs to be done for the library lookup. I'm not sure if the compiler knows whether we are linking with compiler-rt or libgcc. That information is on the linker command line not necessarily the compiler command line.

[LuoYuanke]

It seems @craig.topper supported __cpu_features2 in compiler-rt revision 94ccb2acbf2c5. Anything else that we need to address before landing the patch?

clang/test/CodeGen/attr-target-mv.c

 // RUN: %clang_cc1 -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=LINUX
 // RUN: %clang_cc1 -triple x86_64-windows-pc -emit-llvm %s -o - | FileCheck %s --check-prefix=WINDOWS
 
 int __attribute__((target("sse4.2"))) foo(void) { return 0; }
 int __attribute__((target("arch=sandybridge"))) foo(void);
 int __attribute__((target("arch=ivybridge"))) foo(void) {return 1;}
 int __attribute__((target("arch=goldmont"))) foo(void) {return 3;}
 int __attribute__((target("arch=goldmont-plus"))) foo(void) {return 4;}
 int __attribute__((target("arch=tremont"))) foo(void) {return 5;}
 int __attribute__((target("arch=icelake-client"))) foo(void) {return 6;}
 int __attribute__((target("arch=icelake-server"))) foo(void) {return 7;}
 int __attribute__((target("arch=cooperlake"))) foo(void) {return 8;}
 int __attribute__((target("arch=tigerlake"))) foo(void) {return 9;}
 int __attribute__((target("arch=sapphirerapids"))) foo(void) {return 10;}
 int __attribute__((target("arch=alderlake"))) foo(void) {return 11;}
 int __attribute__((target("arch=rocketlake"))) foo(void) {return 12;}
+int __attribute__((target("arch=cascadelake"))) foo(void) {return 13;}
 int __attribute__((target("default"))) foo(void) { return 2; }
 
 int bar() {
   return foo();
 }
 
 inline int __attribute__((target("sse4.2"))) foo_inline(void) { return 0; }
 inline int __attribute__((target("arch=sandybridge"))) foo_inline(void);

 // LINUX: define{{.*}} i32 @foo.arch_tigerlake()
 // LINUX: ret i32 9
 // LINUX: define{{.*}} i32 @foo.arch_sapphirerapids()
 // LINUX: ret i32 10
 // LINUX: define{{.*}} i32 @foo.arch_alderlake()
 // LINUX: ret i32 11
 // LINUX: define{{.*}} i32 @foo.arch_rocketlake()
 // LINUX: ret i32 12
+// LINUX: define{{.*}} i32 @foo.arch_cascadelake()
+// LINUX: ret i32 13
 // LINUX: define{{.*}} i32 @foo()
 // LINUX: ret i32 2
 // LINUX: define{{.*}} i32 @bar()
 // LINUX: call i32 @foo.ifunc()
 
 // WINDOWS: define dso_local i32 @foo.sse4.2()
 // WINDOWS: ret i32 0
 // WINDOWS: define dso_local i32 @foo.arch_ivybridge()

 // WINDOWS: define dso_local i32 @foo.arch_tigerlake()
 // WINDOWS: ret i32 9
 // WINDOWS: define dso_local i32 @foo.arch_sapphirerapids()
 // WINDOWS: ret i32 10
 // WINDOWS: define dso_local i32 @foo.arch_alderlake()
 // WINDOWS: ret i32 11
 // WINDOWS: define dso_local i32 @foo.arch_rocketlake()
 // WINDOWS: ret i32 12
+// WINDOWS: define dso_local i32 @foo.arch_cascadelake()
+// WINDOWS: ret i32 13
 // WINDOWS: define dso_local i32 @foo()
 // WINDOWS: ret i32 2
 // WINDOWS: define dso_local i32 @bar()
 // WINDOWS: call i32 @foo.resolver()
 
 // LINUX: define weak_odr i32 ()* @foo.resolver() comdat
 // LINUX: call void @__cpu_indicator_init()
 // LINUX: ret i32 ()* @foo.arch_sandybridge

llvm/include/llvm/Support/X86TargetParser.def

 CPU_SPECIFIC("core_2_duo_ssse3", 'M', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3")
 CPU_SPECIFIC("core_2_duo_sse4_1", 'N', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1")
 CPU_SPECIFIC("atom", 'O', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+movbe")
 CPU_SPECIFIC("atom_sse4_2", 'c', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt")
 CPU_SPECIFIC("core_i7_sse4_2", 'P', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt")
 CPU_SPECIFIC("core_aes_pclmulqdq", 'Q', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt")
 CPU_SPECIFIC("atom_sse4_2_movbe", 'd', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt")
 CPU_SPECIFIC("goldmont", 'i', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt")
+CPU_SPECIFIC("goldmont_plus", 'f', "+aes,+clflushopt,+crc32,+cx16,+cx8,+fsgsbase,+fxsr,+mmx,+movbe,+pclmul,+popcnt,+prfchw,+ptwrite,+rdpid,+rdrnd,+rdseed,+sahf,+sgx,+sha,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves")
+CPU_SPECIFIC("tremont", 'g', "+aes,+clflushopt,+clwb,+crc32,+cx16,+cx8,+fsgsbase,+fxsr,+gfni,+mmx,+movbe,+pclmul,+popcnt,+prfchw,+ptwrite,+rdpid,+rdrnd,+rdseed,+sahf,+sgx,+sha,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves")
 CPU_SPECIFIC("sandybridge", 'R', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+avx")
 CPU_SPECIFIC_ALIAS("core_2nd_gen_avx", "sandybridge")
 CPU_SPECIFIC("ivybridge", 'S', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+popcnt,+f16c,+avx")
 CPU_SPECIFIC_ALIAS("core_3rd_gen_avx", "ivybridge")
 CPU_SPECIFIC("haswell", 'V', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2")
 CPU_SPECIFIC_ALIAS("core_4th_gen_avx", "haswell")
 CPU_SPECIFIC("core_4th_gen_avx_tsx", 'W', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2")
 CPU_SPECIFIC("broadwell", 'X', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
 CPU_SPECIFIC_ALIAS("core_5th_gen_avx", "broadwell")
 CPU_SPECIFIC("core_5th_gen_avx_tsx", 'Y', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx")
 CPU_SPECIFIC("knl", 'Z', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd")
 CPU_SPECIFIC_ALIAS("mic_avx512", "knl")
 CPU_SPECIFIC("skylake", 'b', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+adx,+mpx")
 CPU_SPECIFIC( "skylake_avx512", 'a', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512dq,+avx512f,+adx,+avx512cd,+avx512bw,+avx512vl,+clwb")
 CPU_SPECIFIC("cannonlake", 'e', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512dq,+avx512f,+adx,+avx512ifma,+avx512cd,+avx512bw,+avx512vl,+avx512vbmi")
+CPU_SPECIFIC("cascadelake", 'o', "+adx,+aes,+avx,+avx2,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+avx512vnni,+bmi,+bmi2,+clflushopt,+clwb,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves")
+CPU_SPECIFIC("cooperlake", 'h', "+adx,+aes,+avx,+avx2,+avx512bf16,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512vl,+avx512vnni,+bmi,+bmi2,+clflushopt,+clwb,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdrnd,+rdseed,+sahf,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+x87,+xsave,+xsavec,+xsaveopt,+xsaves")
+CPU_SPECIFIC("icelake_client", 'k', "+adx,+aes,+avx,+avx2,+avx512bitalg,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512ifma,+avx512vbmi,+avx512vbmi2,+avx512vl,+avx512vnni,+avx512vpopcntdq,+bmi,+bmi2,+clflushopt,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+gfni,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pku,+popcnt,+prfchw,+rdpid,+rdrnd,+rdseed,+sahf,+sgx,+sha,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+vaes,+vpclmulqdq,+x87,+xsave,+xsavec,+xsaveopt,+xsaves")
+CPU_SPECIFIC("tigerlake", 'l', "+adx,+aes,+avx,+avx2,+avx512bitalg,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512ifma,+avx512vbmi,+avx512vbmi2,+avx512vl,+avx512vnni,+avx512vp2intersect,+avx512vpopcntdq,+bmi,+bmi2,+clflushopt,+clwb,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+gfni,+invpcid,+kl,+lzcnt,+mmx,+movbe,+movdir64b,+movdiri,+pclmul,+pku,+popcnt,+prfchw,+rdpid,+rdrnd,+rdseed,+sahf,+sgx,+sha,+shstk,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+vaes,+vpclmulqdq,+widekl,+x87,+xsave,+xsavec,+xsaveopt,+xsaves")
+CPU_SPECIFIC("icelake_server", 'm', "+adx,+aes,+avx,+avx2,+avx512bitalg,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512ifma,+avx512vbmi,+avx512vbmi2,+avx512vl,+avx512vnni,+avx512vpopcntdq,+bmi,+bmi2,+clflushopt,+clwb,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+gfni,+invpcid,+lzcnt,+mmx,+movbe,+pclmul,+pconfig,+pku,+popcnt,+prfchw,+rdpid,+rdrnd,+rdseed,+sahf,+sgx,+sha,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+vaes,+vpclmulqdq,+wbnoinvd,+x87,+xsave,+xsavec,+xsaveopt,+xsaves")
+CPU_SPECIFIC("sapphirerapids", 'n', "+adx,+aes,+amx-bf16,+amx-int8,+amx-tile,+avx,+avx2,+avx512bf16,+avx512bitalg,+avx512bw,+avx512cd,+avx512dq,+avx512f,+avx512fp16,+avx512ifma,+avx512vbmi,+avx512vbmi2,+avx512vl,+avx512vnni,+avx512vp2intersect,+avx512vpopcntdq,+avxvnni,+bmi,+bmi2,+cldemote,+clflushopt,+clwb,+crc32,+cx16,+cx8,+enqcmd,+f16c,+fma,+fsgsbase,+fxsr,+gfni,+invpcid,+lzcnt,+mmx,+movbe,+movdir64b,+movdiri,+pclmul,+pconfig,+pku,+popcnt,+prfchw,+ptwrite,+rdpid,+rdrnd,+rdseed,+sahf,+serialize,+sgx,+sha,+shstk,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+tsxldtrk,+uintr,+vaes,+vpclmulqdq,+waitpkg,+wbnoinvd,+x87,+xsave,+xsavec,+xsaveopt,+xsaves")
+CPU_SPECIFIC_ALIAS("rocketlake", "icelake_client")
+CPU_SPECIFIC("alderlake", 'p', "+adx,+aes,+avx,+avx2,+avxvnni,+bmi,+bmi2,+cldemote,+clflushopt,+clwb,+crc32,+cx16,+cx8,+f16c,+fma,+fsgsbase,+fxsr,+gfni,+hreset,+invpcid,+kl,+lzcnt,+mmx,+movbe,+movdir64b,+movdiri,+pclmul,+pconfig,+pku,+popcnt,+prfchw,+ptwrite,+rdpid,+rdrnd,+rdseed,+sahf,+serialize,+sgx,+sha,+shstk,+sse,+sse2,+sse3,+sse4.1,+sse4.2,+ssse3,+vaes,+vpclmulqdq,+waitpkg,+widekl,+x87,+xsave,+xsavec,+xsaveopt,+xsaves")
 CPU_SPECIFIC("knm", 'j', "+cmov,+mmx,+sse,+sse2,+sse3,+ssse3,+sse4.1,+sse4.2,+movbe,+popcnt,+f16c,+avx,+fma,+bmi,+lzcnt,+avx2,+avx512f,+adx,+avx512er,+avx512pf,+avx512cd,+avx5124fmaps,+avx5124vnniw,+avx512vpopcntdq")
 
 #undef CPU_SPECIFIC_ALIAS
 #undef CPU_SPECIFIC