[RISCV] Optimize immediate materialisation with SLLI.UW

[benshi001]

Summary

Use LUI+SLLI.UW to compose the upper bits instead of LUI+SLLI.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

static void generateInstSeqImpl(int64_t Val,
 
   int64_t Lo12 = SignExtend64<12>(Val);
   int64_t Hi52 = ((uint64_t)Val + 0x800ull) >> 12;
   int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
   Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
 
   // If the remaining bits don't fit in 12 bits, we might be able to reduce the
   // shift amount in order to use LUI which will zero the lower 12 bits.
-  if (ShiftAmount > 12 && !isInt<12>(Hi52) && isInt<32>((uint64_t)Hi52 << 12)) {
+  bool Unsigned = false;
+  if (ShiftAmount > 12 && !isInt<12>(Hi52)) {
+    if (isInt<32>((uint64_t)Hi52 << 12)) {
       // Reduce the shift amount and add zeros to the LSBs so it will match LUI.
       ShiftAmount -= 12;
       Hi52 = (uint64_t)Hi52 << 12;
+    } else if (isUInt<32>((uint64_t)Hi52 << 12) &&
+               ActiveFeatures[RISCV::FeatureStdExtZba]) {
+      // Reduce the shift amount and add zeros to the LSBs so it will match
+      // LUI, then shift left with SLLI.UW to clear the upper 32 set bits.
+      ShiftAmount -= 12;
+      Hi52 = ((uint64_t)Hi52 << 12) | (0xffffffffull << 32);
+      Unsigned = true;
+    }
   }
 
   generateInstSeqImpl(Hi52, ActiveFeatures, Res);
 
+  if (Unsigned)
+    Res.push_back(RISCVMatInt::Inst(RISCV::SLLIUW, ShiftAmount));
+  else
     Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount));
   if (Lo12)
     Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12));
 }
 
 namespace llvm {
 namespace RISCVMatInt {
 InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
   RISCVMatInt::InstSeq Res;

llvm/test/CodeGen/RISCV/imm.ll

 ; RV64I-NEXT:    lui a0, 160
 ; RV64I-NEXT:    addiw a0, a0, 437
 ; RV64I-NEXT:    slli a0, a0, 13
 ; RV64I-NEXT:    addi a0, a0, -795
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_5372288229:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 160
-; RV64IZBA-NEXT:    addiw a0, a0, 437
-; RV64IZBA-NEXT:    slli a0, a0, 13
+; RV64IZBA-NEXT:    lui a0, 655797
+; RV64IZBA-NEXT:    slli.uw a0, a0, 1
 ; RV64IZBA-NEXT:    addi a0, a0, -795
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_5372288229:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 160
 ; RV64IZBS-NEXT:    addiw a0, a0, 437
 ; RV64IZBS-NEXT:    slli a0, a0, 13

 ; RV64I-NEXT:    lui a0, 188
 ; RV64I-NEXT:    addiw a0, a0, -1093
 ; RV64I-NEXT:    slli a0, a0, 24
 ; RV64I-NEXT:    addi a0, a0, 1979
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_12900924131259:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 188
-; RV64IZBA-NEXT:    addiw a0, a0, -1093
-; RV64IZBA-NEXT:    slli a0, a0, 24
+; RV64IZBA-NEXT:    lui a0, 768955
+; RV64IZBA-NEXT:    slli.uw a0, a0, 12
 ; RV64IZBA-NEXT:    addi a0, a0, 1979
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_12900924131259:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 188
 ; RV64IZBS-NEXT:    addiw a0, a0, -1093
 ; RV64IZBS-NEXT:    slli a0, a0, 24

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a0, 188
 ; RV64I-NEXT:    addiw a0, a0, -1093
 ; RV64I-NEXT:    slli a0, a0, 16
 ; RV64I-NEXT:    ret
 ;
 ; RV64IZBA-LABEL: imm_50394234880:
 ; RV64IZBA:       # %bb.0:
-; RV64IZBA-NEXT:    lui a0, 188
-; RV64IZBA-NEXT:    addiw a0, a0, -1093
-; RV64IZBA-NEXT:    slli a0, a0, 16
+; RV64IZBA-NEXT:    lui a0, 768955
+; RV64IZBA-NEXT:    slli.uw a0, a0, 4
 ; RV64IZBA-NEXT:    ret
 ;
 ; RV64IZBS-LABEL: imm_50394234880:
 ; RV64IZBS:       # %bb.0:
 ; RV64IZBS-NEXT:    lui a0, 188
 ; RV64IZBS-NEXT:    addiw a0, a0, -1093
 ; RV64IZBS-NEXT:    slli a0, a0, 16
 ; RV64IZBS-NEXT:    ret
   ret i64 50394234880
 }

llvm/test/MC/RISCV/rv64zba-aliases-valid.s

 # CHECK-S-OBJ-NOALIAS: lui t2, 699051
 # CHECK-S-OBJ-NOALIAS-NEXT: addiw t2, t2, -1366
 # CHECK-S-OBJ-NOALIAS-NEXT: add.uw t2, t2, zero
 # CHECK-S-OBJ: lui t2, 699051
 # CHECK-S-OBJ-NEXT: addiw t2, t2, -1366
 # CHECK-S-OBJ-NEXT: zext.w t2, t2
 li x7, 0xaaaaaaaa
 
-# CHECK-S-OBJ-NOALIAS: lui t0, 188
-# CHECK-S-OBJ-NOALIAS-NEXT: addiw t0, t0, -1093
-# CHECK-S-OBJ-NOALIAS-NEXT: slli t0, t0, 24
+# CHECK-S-OBJ-NOALIAS: lui t0, 768955
+# CHECK-S-OBJ-NOALIAS-NEXT: slli.uw t0, t0, 12
 # CHECK-S-OBJ-NOALIAS-NEXT: addi t0, t0, 1979
-# CHECK-S-OBJ: lui t0, 188
-# CHECK-S-OBJ-NEXT: addiw t0, t0, -1093
-# CHECK-S-OBJ-NEXT: slli t0, t0, 24
+# CHECK-S-OBJ: lui t0, 768955
+# CHECK-S-OBJ-NEXT: slli.uw t0, t0, 12
 # CHECK-S-OBJ-NEXT: addi t0, t0, 1979
 li x5, 0xbbbbb0007bb
 
-# CHECK-S-OBJ-NOALIAS: lui t0, 188
-# CHECK-S-OBJ-NOALIAS-NEXT: addiw t0, t0, -1093
-# CHECK-S-OBJ-NOALIAS-NEXT: slli t0, t0, 16
-# CHECK-S-OBJ: lui t0, 188
-# CHECK-S-OBJ-NEXT: addiw t0, t0, -1093
-# CHECK-S-OBJ-NEXT: slli t0, t0, 16
+# CHECK-S-OBJ-NOALIAS: lui t0, 768955
+# CHECK-S-OBJ-NOALIAS-NEXT: slli.uw t0, t0, 4
+# CHECK-S-OBJ: lui t0, 768955
+# CHECK-S-OBJ-NEXT: slli.uw t0, t0, 4
 li x5, 0xbbbbb0000