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Differential D111304

[RISCV] Reorder the vector register allocation order.
ClosedPublic

Authored by HsiangKai on Oct 7 2021, 4:57 AM.

Details

Reviewers
rogfer01
frasercrmck
craig.topper
Commits
rGfacff468b6c4: [RISCV] Reorder the vector register allocation order.
Summary

GPR uses argument registers as the first group of registers to allocate.
This patch uses vector argument registers, v8 to v23, as the first group
to allocate.

Diff Detail

Event Timeline

HsiangKai created this revision.Oct 7 2021, 4:57 AM
Herald added subscribers: achieveartificialintelligence, StephenFan, vkmr and 27 others. · View Herald TranscriptOct 7 2021, 4:57 AM
HsiangKai requested review of this revision.Oct 7 2021, 4:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 7 2021, 4:57 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
HsiangKai mentioned this in D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers..Oct 7 2021, 5:01 AM
Harbormaster completed remote builds in B127491: Diff 377808.Oct 7 2021, 5:36 AM
kito-cheng added a comment.Oct 7 2021, 5:48 AM

It's changed code gen so this should not be NFC?

HsiangKai retitled this revision from [NFC][RISCV] Reorder the vector register allocation order. to [RISCV] Reorder the vector register allocation order..Oct 7 2021, 4:33 PM
kito-cheng added inline comments.Oct 7 2021, 8:18 PM
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
506

https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Target/Target.td#L329

Seems like sequence have optional 4th argument for stride, so this could be simplified to

(add (sequence "V%uM2", 8, 31, 2),
     (sequence "V%uM2", 0, 7, 2)), 2>;
HsiangKai updated this revision to Diff 378499.Oct 10 2021, 6:03 AM

Address Kito's comments.

Harbormaster completed remote builds in B127979: Diff 378499.Oct 10 2021, 6:50 AM
rogfer01 added a comment.Oct 12 2021, 2:23 AM

No objection with this, I guess it is for consistency with GPRs, right?

HsiangKai added a comment.Oct 12 2021, 5:52 PM
In D111304#3057612, @rogfer01 wrote:

No objection with this, I guess it is for consistency with GPRs, right?

Yes. Starting with v25 is also strange. It should be an 8x number for LMUL may be 8. To be consistent with GPR to start with argument registers may be a way to go.

HsiangKai added a comment.Oct 17 2021, 8:22 PM

Ping.

frasercrmck accepted this revision.Oct 18 2021, 1:46 AM

LGTM, makes sense

This revision is now accepted and ready to land.Oct 18 2021, 1:46 AM
This revision was landed with ongoing or failed builds.Oct 18 2021, 6:30 PM
Closed by commit rGfacff468b6c4: [RISCV] Reorder the vector register allocation order. (authored by HsiangKai). · Explain Why
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rGfacff468b6c4: [RISCV] Reorder the vector register allocation order..

Large Diff

This large diff affects 399 files. Files without inline comments have been collapsed. Expand All Files

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Diff 380565

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

Show First 20 Lines • Show All 481 Lines • ▼ Show 20 Lines
def VR : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, def VR : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
vfloat16m1_t, vfloat32m1_t, vfloat64m1_t, vfloat16m1_t, vfloat32m1_t, vfloat64m1_t,
vint8mf2_t, vint8mf4_t, vint8mf8_t, vint8mf2_t, vint8mf4_t, vint8mf8_t,
vint16mf2_t, vint16mf4_t, vint32mf2_t, vint16mf2_t, vint16mf4_t, vint32mf2_t,
vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t, vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t,
vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t, vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t,
vbool2_t, vbool1_t], vbool2_t, vbool1_t],
(add (sequence "V%u", 25, 31), (add (sequence "V%u", 8, 31),
(sequence "V%u", 8, 24),
(sequence "V%u", 0, 7)), 1>; (sequence "V%u", 0, 7)), 1>;
def VRNoV0 : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t, def VRNoV0 : VReg<[vint8m1_t, vint16m1_t, vint32m1_t, vint64m1_t,
vfloat16m1_t, vfloat32m1_t, vfloat64m1_t, vfloat16m1_t, vfloat32m1_t, vfloat64m1_t,
vint8mf2_t, vint8mf4_t, vint8mf8_t, vint8mf2_t, vint8mf4_t, vint8mf8_t,
vint16mf2_t, vint16mf4_t, vint32mf2_t, vint16mf2_t, vint16mf4_t, vint32mf2_t,
vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t, vfloat16mf4_t, vfloat16mf2_t, vfloat32mf2_t,
vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t, vbool64_t, vbool32_t, vbool16_t, vbool8_t, vbool4_t,
vbool2_t, vbool1_t], vbool2_t, vbool1_t],
(add (sequence "V%u", 25, 31), (add (sequence "V%u", 8, 31),
(sequence "V%u", 8, 24),
(sequence "V%u", 1, 7)), 1>; (sequence "V%u", 1, 7)), 1>;
def VRM2 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, def VRM2 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
vfloat16m2_t, vfloat32m2_t, vfloat64m2_t], vfloat16m2_t, vfloat32m2_t, vfloat64m2_t],
(add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2, (add (sequence "V%uM2", 8, 31, 2),
V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2), 2>; (sequence "V%uM2", 0, 7, 2)), 2>;
kito-chengUnsubmitted
Not Done
ReplyInline Actions

https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Target/Target.td#L329

Seems like sequence have optional 4th argument for stride, so this could be simplified to

(add (sequence "V%uM2", 8, 31, 2),
     (sequence "V%uM2", 0, 7, 2)), 2>;
kito-cheng: https://github.com/llvm/llvm-project/blob/main/llvm/include/llvm/Target/Target.td#L329 Seems…
def VRM2NoV0 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t, def VRM2NoV0 : VReg<[vint8m2_t, vint16m2_t, vint32m2_t, vint64m2_t,
vfloat16m2_t, vfloat32m2_t, vfloat64m2_t], vfloat16m2_t, vfloat32m2_t, vfloat64m2_t],
(add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2, (add (sequence "V%uM2", 8, 31, 2),
V18M2, V20M2, V22M2, V24M2, V2M2, V4M2, V6M2), 2>; (sequence "V%uM2", 2, 7, 2)), 2>;
def VRM4 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, def VRM4 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
vfloat16m4_t, vfloat32m4_t, vfloat64m4_t], vfloat16m4_t, vfloat32m4_t, vfloat64m4_t],
(add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4), 4>; (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V0M4, V4M4), 4>;
def VRM4NoV0 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t, def VRM4NoV0 : VReg<[vint8m4_t, vint16m4_t, vint32m4_t, vint64m4_t,
vfloat16m4_t, vfloat32m4_t, vfloat64m4_t], vfloat16m4_t, vfloat32m4_t, vfloat64m4_t],
(add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V4M4), 4>; (add V8M4, V12M4, V16M4, V20M4, V24M4, V28M4, V4M4), 4>;
def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, def VRM8 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
vfloat16m8_t, vfloat32m8_t, vfloat64m8_t], vfloat16m8_t, vfloat32m8_t, vfloat64m8_t],
(add V8M8, V16M8, V24M8, V0M8), 8>; (add V8M8, V16M8, V24M8, V0M8), 8>;
def VRM8NoV0 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t, def VRM8NoV0 : VReg<[vint8m8_t, vint16m8_t, vint32m8_t, vint64m8_t,
vfloat16m8_t, vfloat32m8_t, vfloat64m8_t], vfloat16m8_t, vfloat32m8_t, vfloat64m8_t],
(add V8M8, V16M8, V24M8), 8>; (add V8M8, V16M8, V24M8), 8>;
defvar VMaskVTs = [vbool64_t, vbool32_t, vbool16_t, vbool8_t, defvar VMaskVTs = [vbool64_t, vbool32_t, vbool16_t, vbool8_t,
vbool4_t, vbool2_t, vbool1_t]; vbool4_t, vbool2_t, vbool1_t];
def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> { def VMV0 : RegisterClass<"RISCV", VMaskVTs, 64, (add V0)> {
let Size = 64; let Size = 64;
} }
// The register class is added for inline assembly for vector mask types. // The register class is added for inline assembly for vector mask types.
def VM : VReg<[vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t, def VM : VReg<[vbool1_t, vbool2_t, vbool4_t, vbool8_t, vbool16_t,
vbool32_t, vbool64_t], vbool32_t, vbool64_t],
(add (sequence "V%u", 25, 31), (add (sequence "V%u", 8, 31),
(sequence "V%u", 8, 24),
(sequence "V%u", 0, 7)), 1>; (sequence "V%u", 0, 7)), 1>;
foreach m = LMULList.m in { foreach m = LMULList.m in {
foreach nf = NFList<m>.L in { foreach nf = NFList<m>.L in {
def "VRN" # nf # "M" # m: VReg<[untyped], def "VRN" # nf # "M" # m: VReg<[untyped],
(add !cast<RegisterTuples>("VN" # nf # "M" # m # "V0"), !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")), (add !cast<RegisterTuples>("VN" # nf # "M" # m # "V0"), !cast<RegisterTuples>("VN" # nf # "M" # m # "NoV0")),
!mul(nf, m)>; !mul(nf, m)>;
def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped], def "VRN" # nf # "M" # m # "NoV0": VReg<[untyped],
Show All 21 Lines

llvm/test/CodeGen/RISCV/GlobalISel/calllowering-ret.ll

llvm/test/CodeGen/RISCV/byval.ll

llvm/test/CodeGen/RISCV/calls.ll

llvm/test/CodeGen/RISCV/copy-frameindex.mir

llvm/test/CodeGen/RISCV/double-calling-conv.ll

llvm/test/CodeGen/RISCV/double-previous-failure.ll

llvm/test/CodeGen/RISCV/fastcc-int.ll

llvm/test/CodeGen/RISCV/rvv/abs-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll

llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir

llvm/test/CodeGen/RISCV/rvv/combine-splats.ll

llvm/test/CodeGen/RISCV/rvv/combine-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/common-shuffle-patterns.ll

llvm/test/CodeGen/RISCV/rvv/constant-folding.ll

llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vector-strided-load-store.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-abs.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-elen.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-conv.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-setcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-vrgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-load-store.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-logic.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-mask-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmul-vp.ll

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vreductions-mask.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vshl-vp.ll

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsrl-vp.ll

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmacc.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmaccu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmul.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwmulu.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll

llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/interleave-crash.ll

llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll

llvm/test/CodeGen/RISCV/rvv/load-add-store-16.ll

llvm/test/CodeGen/RISCV/rvv/load-add-store-32.ll

llvm/test/CodeGen/RISCV/rvv/load-add-store-64.ll

llvm/test/CodeGen/RISCV/rvv/load-add-store-8.ll

llvm/test/CodeGen/RISCV/rvv/load-mask.ll

llvm/test/CodeGen/RISCV/rvv/localvar.ll

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv32.ll

llvm/test/CodeGen/RISCV/rvv/mask-exts-truncs-rv64.ll

llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir

llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll

llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll

llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll

llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll

llvm/test/CodeGen/RISCV/rvv/saddo-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/select-fp.ll

llvm/test/CodeGen/RISCV/rvv/select-int.ll

llvm/test/CodeGen/RISCV/rvv/select-sra.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll

llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll

llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

llvm/test/CodeGen/RISCV/rvv/stepvector.ll

llvm/test/CodeGen/RISCV/rvv/urem-seteq-vec.ll

llvm/test/CodeGen/RISCV/rvv/vaadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vaaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vand-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vand-vp.ll

llvm/test/CodeGen/RISCV/rvv/vasub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vasubu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vcompress-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vcompress-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfadd-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfcopysign-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rod-f-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-rtz-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfpext-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfptrunc-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vfrdiv-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfslide1up-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-x-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-xu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-rtz-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwmul-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vleff-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vleff-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vloxei-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vluxei-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmax-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfeq-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfge-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfge-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfgt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfle-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmin-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vminu-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsbf-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmseq-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsge-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsgt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsif-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsif-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsle-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsleu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsltu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsne-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmsof-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmsof-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmul-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll

llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnclip-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnclip-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vnclipu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnclipu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vnsra-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnsra-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vnsrl-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vnsrl-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vor-vp.ll

llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-mask-vp.ll

llvm/test/CodeGen/RISCV/rvv/vreductions-mask.ll

llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrem-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll

llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vremu-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll

llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrgatherei16-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vselect-fp-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vselect-mask.ll

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll

llvm/test/CodeGen/RISCV/rvv/vsext-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsext-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vshl-vp.ll

llvm/test/CodeGen/RISCV/rvv/vslide1down-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vslide1up-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vslide1up-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsm-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsm-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll

llvm/test/CodeGen/RISCV/rvv/vsra-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsrl-vp.ll

llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll

llvm/test/CodeGen/RISCV/rvv/vsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsub-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwadd-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwadd-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwaddu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwaddu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmul-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmul-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmulsu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwmulu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwmulu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwsub-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwsub-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwsubu-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwsubu-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll

llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vxor-sdnode-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll

llvm/test/CodeGen/RISCV/rvv/vzext-rv32.ll

llvm/test/CodeGen/RISCV/rvv/vzext-rv64.ll

llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

llvm/test/CodeGen/RISCV/select-optimize-multiple.mir

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll