[mlir][Linalg] Add support for min/max reduction vectorization in linalg.generic

[dcaballe]

Summary

This patch extends Linalg core vectorization with support for min/max reductions
in linalg.generic ops. It enables the reduction detection for min/max combiner ops.
It also renames MIN/MAX combining kinds to MINS/MAXS to make the sign explicit for
floating point and signed integer types. MINU/MAXU should be introduce din the future
for unsigned integer types.

[ThomasRaoux]

mlir/include/mlir/Dialect/Vector/VectorOps.td

41

nit: The naming seems a bit confusing. Is there any reason why we don't want to add spearate minf/maxf? It doesn't look like it would add code/complexity?

mlir/lib/Dialect/Vector/VectorTransforms.cpp

871–873

This lowering doesn't propagate Nan while the new minf op is supposed to propagate Nan. I assume we want to match the semantic of minf. (same for maxf of course)

[ThomasRaoux]

mlir/lib/Dialect/Vector/VectorTransforms.cpp

871–873

The most natural would be to lower to minf/maxf ops in my opinion.

[pifon2a]

mlir/include/mlir/Dialect/Vector/VectorOps.td

41

yes, i think with the current maxf, maxsi, maxui ops added we can actually have 1 to 1 map.

mlir/lib/Dialect/Vector/VectorTransforms.cpp

823–825

create<MinSIOp>?

826–827

create<MaxSIOp>?

871–873

+1 @ThomasRaoux , create<MinFOp>?

[dcaballe]

mlir/include/mlir/Dialect/Vector/VectorOps.td

41

What I inferred from the current implementation, and maybe I'm totally wrong, is that the actual type is taken from the reduction/contraction op itself. I understand that's why we only have ADD, MUL, etc., and not ADDI/ADDF, MULI/MULF etc. The only thing that is missing is the signedness for those operations where it makes a difference (min/max, in this case). I though adding MINS/MAXS for signed integer and floating point (and eventually MINU/MAXU for unsigned integers) would avoid duplicating all the I/SI/UI/F variants.

If we wanted to go with all the I/SI/UI/F variants, shouldn't we do it for all the ops to be consistent? We would also need verification rules to make sure the type of the combiner matches the type of the op. Again, this sounds a bit redundant to me since the type itself is in the operation. We just need the sign information.

WDYT?

mlir/lib/Dialect/Vector/VectorTransforms.cpp

871–873

Yes, that makes sense, thanks! I thought @pifon2a's patch was taking care of that already. I see now that it's only expanding the min/max ops to the compare/select implementation.

[ThomasRaoux]

mlir/include/mlir/Dialect/Vector/VectorOps.td

41

I agree, that's how it is right now, however having MAXS maps to float max seems confusing to me. Overall even for Add/Mul the float and integer version are separate opcodes everywhere so we don't really save a lot having a single enum.
It doesn't make sense to have ADD and MUL for I/SI/UI as they are equivalent so I don't think it is makes sense to have different version for those (and we don't have different opcodes for them).

Updating verifier is just a matter of updating is SupportedCombiningKind so shouldn't be to bad. What do you think?

[dcaballe]

mlir/include/mlir/Dialect/Vector/VectorOps.td

41

It doesn't make sense to have ADD and MUL for I/SI/UI as they are equivalent so I don't think it is makes sense to have different version for those (and we don't have different opcodes for them).

Sorry, I wasn't clear here. Not all the variants make sense for all the ops, obviously. I and SI/UI are mutually exclusive.

No strong opinion, though. I can start addressing the min/max ones.

[ThomasRaoux]

mlir/include/mlir/Dialect/Vector/VectorOps.td

41

I don't have a strong opinion but my preference is to have mins/maxs/minf/maxf in this case

[nicolasvasilache]

General comment (not for this CL), I find mins maxs etc quite worse than smin, smax etc.
Any reason we want to deviate from the LLVM names (e.g. https://llvm.org/docs/LangRef.html#llvm-smin-intrinsic) ?

I see that the attr names are consistent with the MLIR names but I don't know why we deviated in the first place.

mlir/include/mlir/Dialect/Vector/VectorOps.td

41

The LLVM Langref has smin/smax/umin/umax/fmin/fmax; any reason we want to deviate from that ?
@pifon2a I realized I hadn't checked that in your original PR, but would be nice to be consistent with LLVM unless there is a strong reason not to.

I'd agree that using smin/smax for float would be a further step away form LLVM so I'd prefer we'd avoid that.

[pifon2a]

mlir/include/mlir/Dialect/Vector/VectorOps.td

41

Because in MLIR we already have "postfix" style. We have addf and not fadd. Also the PR that adds Arith dialect (https://reviews.llvm.org/D110200) has DivSIOp and so on. I wanted to be consistent with the style.

[dcaballe]

mlir/include/mlir/Dialect/Vector/VectorOps.td

41

Yes, I think it's important to keep things consistent within MLIR. If we want to align with LLVM, it's probably better to address it separately, at a broader level. I'll go with the S/U/F approach for min/max, then.

41

> The LLVM Langref has smin/smax/umin/umax/fmin/fmax; any reason we want to deviate from that ?

Note that we have more inconsistencies than just the prefix/postfix name. LLVM has the following intrinsics for fp min/max:

Scalar/vector max/min intrinsics:

• 'llvm.maxnum': https://llvm.org/docs/LangRef.html#llvm-maxnum-intrinsic - Nothing equivalent in MLIR.
• 'llvm.minnum': https://llvm.org/docs/LangRef.html#llvm-minnum-intrinsic - Nothing equivalent in MLIR.
• 'lllvm.maximum': https://llvm.org/docs/LangRef.html#llvm-maximum-intrinsic - Same as MLIR's maxf.
• 'lllvm.minimum': https://llvm.org/docs/LangRef.html#llvm-minimum-intrinsic - Same as MLIR's minf.

Horizontal vector reductions:

• llvm.vector.reduce.fmax - https://llvm.org/docs/LangRef.html#llvm-vector-reduce-fmax-intrinsic - It uses 'maxnum' semantics. We can't lower MLIR vector.reduce #maxf to this one!
• llvm.vector.reduce.fmin - https://llvm.org/docs/LangRef.html#llvm-vector-reduce-fmin-intrinsic - It uses 'minnum' semantics. We can't lower MLIR vector.reduce #minf to this one!

So, to be aligned with LLVM, our minf/maxf ops should be renamed to minimum/maximum. Note as well that, AFAICT, there are no horizontal reductions with minimum/maximum semantics in LLVM so we can't use those!

If we want to be aligned with LLVM, I think we should consider renaming minf/maxf -> minimum/maximum.

[dcaballe]

Addressed feedback.
Sorry for the delay but I went into a rabbit hole. For some reason,
the existing implementation lowered min/max ops on signless integers
assuming signed integers. It took me a while to realize what was going
on...

[dcaballe]

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp

494

This is exactly the problem that I described above. This lowering is incorrect and it won't produce the right output if the input has NaNs. We need to add a new 'vector_reduce' intrinsic to LLVM or implement our own lowering to more basic vector instructions in MLIR. I'll follow up on this when we hit this limitation.

[ThomasRaoux]

mlir/lib/Dialect/Vector/VectorOps.cpp

99

should MAXF case only return true if the elementType is float?

308–309

can we call isSupportedCombiningKind here?

[dcaballe]

Addressed feedback.
Thanks!

mlir/lib/Dialect/Vector/VectorOps.cpp

99

Good catch, thanks!

308–309

much better, thanks!

[pifon2a]

Great, thank you, Diego!

[ThomasRaoux]

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp

494

As discuss it is a bit scary to have a potential silent miscompile. Can we fail this pattern here?

mlir/include/mlir/Dialect/Vector/VectorOps.td

class Vector_Op<string mnemonic, list<OpTrait> traits = []> :
   //                                         OperationState &result)
   // functions.
   let printer = [{ return ::print(p, *this); }];
   let verifier = [{ return ::verify(*this); }];
   let parser = [{ return ::parse$cppClass(parser, result); }];
 }
 
 // The "kind" of combining function for contractions and reductions.
-def COMBINING_KIND_ADD : BitEnumAttrCase<"ADD", 0x1,  "add">;
-def COMBINING_KIND_MUL : BitEnumAttrCase<"MUL", 0x2,  "mul">;
-def COMBINING_KIND_MIN : BitEnumAttrCase<"MIN", 0x4,  "min">;
-def COMBINING_KIND_MAX : BitEnumAttrCase<"MAX", 0x8,  "max">;
-def COMBINING_KIND_AND : BitEnumAttrCase<"AND", 0x10, "and">;
-def COMBINING_KIND_OR  : BitEnumAttrCase<"OR",  0x20, "or">;
-def COMBINING_KIND_XOR : BitEnumAttrCase<"XOR", 0x40, "xor">;
+def COMBINING_KIND_ADD : BitEnumAttrCase<"ADD", 0x1, "add">;
+def COMBINING_KIND_MUL : BitEnumAttrCase<"MUL", 0x2, "mul">;
+def COMBINING_KIND_MINUI : BitEnumAttrCase<"MINUI", 0x4, "minui">;
+def COMBINING_KIND_MINSI : BitEnumAttrCase<"MINSI", 0x8, "minsi">;
+def COMBINING_KIND_MINF : BitEnumAttrCase<"MINF", 0x10, "minf">;
+def COMBINING_KIND_MAXUI : BitEnumAttrCase<"MAXUI", 0x20, "maxui">;
+def COMBINING_KIND_MAXSI : BitEnumAttrCase<"MAXSI", 0x40, "maxsi">;
+def COMBINING_KIND_MAXF : BitEnumAttrCase<"MAXF", 0x80, "maxf">;
+def COMBINING_KIND_AND : BitEnumAttrCase<"AND", 0x100, "and">;
+def COMBINING_KIND_OR  : BitEnumAttrCase<"OR", 0x200, "or">;
+def COMBINING_KIND_XOR : BitEnumAttrCase<"XOR", 0x400, "xor">;
 
 def CombiningKind : BitEnumAttr<
     "CombiningKind",
     "Kind of combining function for contractions and reductions",
-    [COMBINING_KIND_ADD, COMBINING_KIND_MUL, COMBINING_KIND_MIN,
-     COMBINING_KIND_MAX, COMBINING_KIND_AND, COMBINING_KIND_OR,
-     COMBINING_KIND_XOR]> {
+    [COMBINING_KIND_ADD, COMBINING_KIND_MUL, COMBINING_KIND_MINUI,
+     COMBINING_KIND_MINSI, COMBINING_KIND_MINF, COMBINING_KIND_MAXUI,
+     COMBINING_KIND_MAXSI, COMBINING_KIND_MAXF, COMBINING_KIND_AND,
+     COMBINING_KIND_OR, COMBINING_KIND_XOR]> {
   let cppNamespace = "::mlir::vector";
   let genSpecializedAttr = 0;
 }
 
 def Vector_CombiningKindAttr : DialectAttr<
     Vector_Dialect,
     CPred<"$_self.isa<::mlir::vector::CombiningKindAttr>()">,
     "Kind of combining function for contractions and reductions"> {
static SmallVector<bool> getReductionMask(
       SmallVector<bool> res(sourceRank, false);
       for (auto idx : reductionDims)
         res[idx] = true;
       return res;
     }
 
     static SmallVector<int64_t> inferDestShape(
       ArrayRef<int64_t> shape, ArrayRef<bool> reducedDimsMask) {
-      assert(shape.size() == reducedDimsMask.size() && 
+      assert(shape.size() == reducedDimsMask.size() &&
              "shape and maks of different sizes");
       SmallVector<int64_t> res;
       for (auto it : llvm::zip(reducedDimsMask, shape))
         if (!std::get<0>(it))
           res.push_back(std::get<1>(it));
       return res;
     }
   }];

mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp

matchAndRewrite(vector::ReductionOp reductionOp, OpAdaptor adaptor,
     if (eltType.isIntOrIndex()) {
       // Integer reductions: add/mul/min/max/and/or/xor.
       if (kind == "add")
         rewriter.replaceOpWithNewOp<LLVM::vector_reduce_add>(reductionOp,
                                                              llvmType, operand);
       else if (kind == "mul")
         rewriter.replaceOpWithNewOp<LLVM::vector_reduce_mul>(reductionOp,
                                                              llvmType, operand);
-      else if (kind == "min" &&
-               (eltType.isIndex() || eltType.isUnsignedInteger()))
+      else if (kind == "minui")
         rewriter.replaceOpWithNewOp<LLVM::vector_reduce_umin>(
             reductionOp, llvmType, operand);
-      else if (kind == "min")
+      else if (kind == "minsi")
         rewriter.replaceOpWithNewOp<LLVM::vector_reduce_smin>(
             reductionOp, llvmType, operand);
-      else if (kind == "max" &&
-               (eltType.isIndex() || eltType.isUnsignedInteger()))
+      else if (kind == "maxui")
         rewriter.replaceOpWithNewOp<LLVM::vector_reduce_umax>(
             reductionOp, llvmType, operand);
-      else if (kind == "max")
+      else if (kind == "maxsi")
         rewriter.replaceOpWithNewOp<LLVM::vector_reduce_smax>(
             reductionOp, llvmType, operand);
       else if (kind == "and")
         rewriter.replaceOpWithNewOp<LLVM::vector_reduce_and>(reductionOp,
                                                              llvmType, operand);
       else if (kind == "or")
         rewriter.replaceOpWithNewOp<LLVM::vector_reduce_or>(reductionOp,
                                                             llvmType, operand);
if (kind == "add") {
       Value acc = adaptor.getOperands().size() > 1
                       ? adaptor.getOperands()[1]
                       : rewriter.create<LLVM::ConstantOp>(
                             reductionOp->getLoc(), llvmType,
                             rewriter.getFloatAttr(eltType, 1.0));
       rewriter.replaceOpWithNewOp<LLVM::vector_reduce_fmul>(
           reductionOp, llvmType, acc, operand,
           rewriter.getBoolAttr(reassociateFPReductions));
-    } else if (kind == "min")
+    } else if (kind == "minf")
+      // FIXME: MLIR's 'minf' and LLVM's 'vector_reduce_fmin' do not handle
+      // NaNs/-0.0/+0.0 in the same way.
       rewriter.replaceOpWithNewOp<LLVM::vector_reduce_fmin>(reductionOp,
                                                             llvmType, operand);
-    else if (kind == "max")
+    else if (kind == "maxf")
+      // FIXME: MLIR's 'maxf' and LLVM's 'vector_reduce_fmax' do not handle
+      // NaNs/-0.0/+0.0 in the same way.
       rewriter.replaceOpWithNewOp<LLVM::vector_reduce_fmax>(reductionOp,
                                                             llvmType, operand);
     else
       return failure();
     return success();
   }
 
 private:

mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp

 /// ShapedType of `v`.
 static VectorType extractVectorTypeFromShapedValue(Value v) {
   auto st = v.getType().cast<ShapedType>();
   if (st.isa<MemRefType>() && st.getShape().empty())
     return VectorType();
   return VectorType::get(st.getShape(), st.getElementType());
 }
 
+static llvm::Optional<vector::CombiningKind>
+getKindForOp(Operation *reductionOp) {
+  if (!reductionOp)
+    return llvm::None;
+  return llvm::TypeSwitch<Operation *, llvm::Optional<vector::CombiningKind>>(
+             reductionOp)
+      .Case<AddIOp, AddFOp>([&](auto op) { return vector::CombiningKind::ADD; })
+      .Case<MaxSIOp>([&](auto op) { return vector::CombiningKind::MAXSI; })
+      .Case<MaxFOp>([&](auto op) { return vector::CombiningKind::MAXF; })
+      .Case<MinSIOp>([&](auto op) { return vector::CombiningKind::MINSI; })
+      .Case<MinFOp>([&](auto op) { return vector::CombiningKind::MINF; })
+      .Default([&](auto op) { return llvm::None; });
+}
+
 /// Check whether `outputOperand` is a reduction with a single combiner
-/// operation. Return the combiner operation of the reduction, which is assumed
-/// to be a binary operation. Multiple reduction operations would impose an
-/// ordering between reduction dimensions and is currently unsupported in
-/// Linalg. This limitation is motivated by the fact that e.g. min(max(X)) !=
+/// operation. Return the combiner operation kind of the reduction, if
+/// supported. Return llvm::None, otherwise. Multiple reduction operations would
+/// impose an ordering between reduction dimensions and is currently unsupported
+/// in Linalg. This limitation is motivated by the fact that e.g. min(max(X)) !=
 /// max(min(X))
 // TODO: use in LinalgOp verification, there is a circular dependency atm.
-static Operation *getSingleBinaryOpAssumedReduction(OpOperand *outputOperand) {
+static llvm::Optional<vector::CombiningKind>
+matchLinalgReduction(OpOperand *outputOperand) {
   auto linalgOp = cast<LinalgOp>(outputOperand->getOwner());
   unsigned outputPos =
       outputOperand->getOperandNumber() - linalgOp.getNumInputs();
+  // Only single combiner operatios are supported for now.
   SmallVector<Operation *, 4> combinerOps;
   if (!matchReduction(linalgOp.getRegionOutputArgs(), outputPos, combinerOps) ||
       combinerOps.size() != 1)
-    return nullptr;
+    return llvm::None;
 
-  // TODO: also assert no other subsequent ops break the reduction.
-  return combinerOps[0];
+  // Return the combiner operation kind, if supported.
+  return getKindForOp(combinerOps[0]);
 }
 
 /// If `value` of assumed VectorType has a shape different than `shape`, try to
 /// build and return a new vector.broadcast to `shape`.
 /// Otherwise, just return `value`.
 // TODO: this is best effort atm and there is currently no guarantee of
 // correctness for the broadcast semantics.
 static Value broadcastIfNeeded(OpBuilder &b, Value value,
                                ArrayRef<int64_t> shape) {
   unsigned numDimsGtOne = std::count_if(shape.begin(), shape.end(),
                                         [](int64_t val) { return val > 1; });
   auto vecType = value.getType().dyn_cast<VectorType>();
   if (shape.empty() ||
       (vecType != nullptr &&
        (vecType.getShape() == shape || vecType.getRank() > numDimsGtOne)))
     return value;
   auto newVecType = VectorType::get(shape, vecType ? vecType.getElementType()
                                                    : value.getType());
   return b.create<vector::BroadcastOp>(b.getInsertionPoint()->getLoc(),
                                        newVecType, value);
 }
 
-static llvm::Optional<vector::CombiningKind>
-getKindForOp(Operation *reductionOp) {
-  if (!reductionOp)
-    return llvm::None;
-  return llvm::TypeSwitch<Operation *, llvm::Optional<vector::CombiningKind>>(
-             reductionOp)
-      .Case<AddIOp, AddFOp>([&](auto op) {
-        return llvm::Optional<vector::CombiningKind>{
-            vector::CombiningKind::ADD};
-      })
-      .Default([&](auto op) { return llvm::None; });
-}
-
 /// If value of assumed VectorType has a shape different than `shape`, build and
 /// return a new vector.broadcast to `shape`.
 /// Otherwise, just return value.
 static Value reduceIfNeeded(OpBuilder &b, VectorType targetVectorType,
                             Value value, OpOperand *outputOperand) {
   auto linalgOp = cast<LinalgOp>(outputOperand->getOwner());
   auto vecType = value.getType().dyn_cast<VectorType>();
   if (!vecType || vecType.getShape() == targetVectorType.getShape())
     return value;
-  // At this point, we know we need to reduce. Detect the reduction operator.
-  // TODO: Use the generic reduction detection util.
-  Operation *reductionOp = getSingleBinaryOpAssumedReduction(outputOperand);
+
   unsigned pos = 0;
   MLIRContext *ctx = b.getContext();
   SmallVector<AffineExpr> exprs;
   for (auto s : linalgOp.iterator_types())
     if (isParallelIterator(s))
       exprs.push_back(getAffineDimExpr(pos++, ctx));
   auto loc = value.getLoc();
-  // TODO: reuse common CombiningKing logic and support more than add.
-  auto maybeKind = getKindForOp(reductionOp);
+
+  // At this point, we know we need to reduce. Detect the reduction operator.
+  auto maybeKind = matchLinalgReduction(outputOperand);
   assert(maybeKind && "Failed precondition: could not get reduction kind");
   unsigned idx = 0;
   SmallVector<bool> reductionMask(linalgOp.iterator_types().size(), false);
   for (auto attr : linalgOp.iterator_types()) {
     if (isReductionIterator(attr))
       reductionMask[idx] = true;
     ++idx;
   }

 }
 
 // TODO: probably need some extra checks for reduction followed by consumer
 // ops that may not commute (e.g. linear reduction + non-linear instructions).
 static LogicalResult reductionPreconditions(LinalgOp op) {
   if (llvm::none_of(op.iterator_types(), isReductionIterator))
     return failure();
   for (OpOperand *opOperand : op.getOutputOperands()) {
-    Operation *reductionOp = getSingleBinaryOpAssumedReduction(opOperand);
-    if (!getKindForOp(reductionOp))
+    if (!matchLinalgReduction(opOperand))
       return failure();
   }
   return success();
 }
 
 LogicalResult mlir::linalg::vectorizeLinalgOpPrecondition(Operation *op) {
   auto linalgOp = cast<linalg::LinalgOp>(op);
   // All types must be static shape to go to vector.

mlir/lib/Dialect/Vector/VectorOps.cpp

 }
 
 // Helper for verifying combining kinds in contractions and reductions.
 static bool isSupportedCombiningKind(CombiningKind combiningKind,
                                      Type elementType) {
   switch (combiningKind) {
   case CombiningKind::ADD:
   case CombiningKind::MUL:
-  case CombiningKind::MIN:
-  case CombiningKind::MAX:
     return elementType.isIntOrIndexOrFloat();
+  case CombiningKind::MINUI:
+  case CombiningKind::MINSI:
+  case CombiningKind::MAXUI:
+  case CombiningKind::MAXSI:
   case CombiningKind::AND:
   case CombiningKind::OR:
   case CombiningKind::XOR:
     return elementType.isIntOrIndex();
+  case CombiningKind::MINF:
+  case CombiningKind::MAXF:
+    return elementType.isa<FloatType>();
   }
   return false;
 }
 
 /// Return true if the last dimension of the MemRefType has unit stride. Also
 /// return true for memrefs with no strides.
 bool mlir::vector::isLastMemrefDimUnitStride(MemRefType type) {
   int64_t offset;

 CombiningKind CombiningKindAttr::getKind() const {
   return static_cast<CombiningKind>(getImpl()->value);
 }
 
 static constexpr const CombiningKind combiningKindsList[] = {
     // clang-format off
     CombiningKind::ADD,
     CombiningKind::MUL,
-    CombiningKind::MIN,
-    CombiningKind::MAX,
+    CombiningKind::MINUI,
+    CombiningKind::MINSI,
+    CombiningKind::MINF,
+    CombiningKind::MAXUI,
+    CombiningKind::MAXSI,
+    CombiningKind::MAXF,
     CombiningKind::AND,
     CombiningKind::OR,
     CombiningKind::XOR,
     // clang-format on
 };
 
 void CombiningKindAttr::print(DialectAsmPrinter &printer) const {
   printer << "kind<";

 
 static LogicalResult verify(ReductionOp op) {
   // Verify for 1-D vector.
   int64_t rank = op.getVectorType().getRank();
   if (rank != 1)
     return op.emitOpError("unsupported reduction rank: ") << rank;
 
   // Verify supported reduction kind.
-  auto kind = op.kind();
+  StringRef strKind = op.kind();
+  auto maybeKind = symbolizeCombiningKind(strKind);
+  if (!maybeKind)
+    return op.emitOpError("unknown reduction kind: ") << strKind;
+
   Type eltType = op.dest().getType();
-  if (kind == "add" || kind == "mul" || kind == "min" || kind == "max") {
-    if (!eltType.isIntOrIndexOrFloat())
-      return op.emitOpError("unsupported reduction type");
-  } else if (kind == "and" || kind == "or" || kind == "xor") {
-    if (!eltType.isIntOrIndex())
-      return op.emitOpError("unsupported reduction type");
-  } else {
-    return op.emitOpError("unknown reduction kind: ") << kind;
-  }
+  if (!isSupportedCombiningKind(*maybeKind, eltType))
+    return op.emitOpError("unsupported reduction type '")
+           << eltType << "' for kind '" << op.kind() << "'";
 
   // Verify optional accumulator.
   if (!op.acc().empty()) {
-    if (kind != "add" && kind != "mul")
-      return op.emitOpError("no accumulator for reduction kind: ") << kind;
+    if (strKind != "add" && strKind != "mul")
+      return op.emitOpError("no accumulator for reduction kind: ") << strKind;
     if (!eltType.isa<FloatType>())
       return op.emitOpError("no accumulator for type: ") << eltType;
   }
 
   return success();
 }
 
 static ParseResult parseReductionOp(OpAsmParser &parser,

mlir/lib/Dialect/Vector/VectorTransforms.cpp

static Optional<Value> genMultI(Location loc, Value x, Value y, Value acc,
 
     Value combinedResult;
     switch (kind) {
     case CombiningKind::ADD:
       combinedResult = rewriter.create<AddIOp>(loc, mul, acc);
       break;
     case CombiningKind::MUL:
       combinedResult = rewriter.create<MulIOp>(loc, mul, acc);
       break;
-    case CombiningKind::MIN:
-      combinedResult = rewriter.create<SelectOp>(
-          loc, rewriter.create<CmpIOp>(loc, CmpIPredicate::slt, mul, acc), mul,
-          acc);
-      break;
-    case CombiningKind::MAX:
-      combinedResult = rewriter.create<SelectOp>(
-          loc, rewriter.create<CmpIOp>(loc, CmpIPredicate::sge, mul, acc), mul,
-          acc);
+    case CombiningKind::MINUI:
+      combinedResult = rewriter.create<MinUIOp>(loc, mul, acc);
+      break;
+    case CombiningKind::MINSI:
+      combinedResult = rewriter.create<MinSIOp>(loc, mul, acc);
+      break;
+    case CombiningKind::MAXUI:
+      combinedResult = rewriter.create<MaxUIOp>(loc, mul, acc);
+      break;
+    case CombiningKind::MAXSI:
+      combinedResult = rewriter.create<MaxSIOp>(loc, mul, acc);
       break;
     case CombiningKind::AND:
       combinedResult = rewriter.create<AndOp>(loc, mul, acc);
       break;
     case CombiningKind::OR:
       combinedResult = rewriter.create<OrOp>(loc, mul, acc);
       break;
     case CombiningKind::XOR:
       combinedResult = rewriter.create<XOrOp>(loc, mul, acc);
       break;
+    case CombiningKind::MINF: // Only valid for floating point types.
+    case CombiningKind::MAXF: // Only valid for floating point types.
+      return Optional<Value>();
     }
     return Optional<Value>(combinedResult);
   }
 
   static Optional<Value> genMultF(Location loc, Value x, Value y, Value acc,
                                   vector::CombiningKind kind,
                                   PatternRewriter &rewriter) {
     using vector::CombiningKind;
 
     // Special case for fused multiply-add.
     if (acc && kind == CombiningKind::ADD) {
       return Optional<Value>(rewriter.create<vector::FMAOp>(loc, x, y, acc));
     }
 
     MulFOp mul = rewriter.create<MulFOp>(loc, x, y);
 
     if (!acc)
       return Optional<Value>(mul);
 
     Value combinedResult;
     switch (kind) {
     case CombiningKind::MUL:
       combinedResult = rewriter.create<MulFOp>(loc, mul, acc);
       break;
-    case CombiningKind::MIN:
-      combinedResult = rewriter.create<SelectOp>(
-          loc, rewriter.create<CmpFOp>(loc, CmpFPredicate::OLE, mul, acc), mul,
-          acc);
-      break;
-    case CombiningKind::MAX:
-      combinedResult = rewriter.create<SelectOp>(
-          loc, rewriter.create<CmpFOp>(loc, CmpFPredicate::OGT, mul, acc), mul,
-          acc);
+    case CombiningKind::MINF:
+      combinedResult = rewriter.create<MinFOp>(loc, mul, acc);
+      break;
+    case CombiningKind::MAXF:
+      combinedResult = rewriter.create<MaxFOp>(loc, mul, acc);
       break;
     case CombiningKind::ADD: // Already handled this special case above.
     case CombiningKind::AND: // Only valid for integer types.
+    case CombiningKind::MINUI: // Only valid for integer types.
+    case CombiningKind::MINSI: // Only valid for integer types.
+    case CombiningKind::MAXUI: // Only valid for integer types.
+    case CombiningKind::MAXSI: // Only valid for integer types.
     case CombiningKind::OR:  // Only valid for integer types.
     case CombiningKind::XOR: // Only valid for integer types.
       return Optional<Value>();
     }
     return Optional<Value>(combinedResult);
   }
 };
 
for (int64_t i = 1; i < srcShape[0]; i++) {
           result = rewriter.create<AddFOp>(loc, operand, result);
         break;
       case vector::CombiningKind::MUL:
         if (elementType.isIntOrIndex())
           result = rewriter.create<MulIOp>(loc, operand, result);
         else
           result = rewriter.create<MulFOp>(loc, operand, result);
         break;
-      case vector::CombiningKind::MIN:
-        if (elementType.isIntOrIndex())
-          condition =
-              rewriter.create<CmpIOp>(loc, CmpIPredicate::slt, operand, result);
-        else
-          condition =
-              rewriter.create<CmpFOp>(loc, CmpFPredicate::OLT, operand, result);
-        result = rewriter.create<SelectOp>(loc, condition, operand, result);
+      case vector::CombiningKind::MINUI:
+        result = rewriter.create<MinUIOp>(loc, operand, result);
         break;
-      case vector::CombiningKind::MAX:
-        if (elementType.isIntOrIndex())
-          condition =
-              rewriter.create<CmpIOp>(loc, CmpIPredicate::sge, operand, result);
-        else
-          condition =
-              rewriter.create<CmpFOp>(loc, CmpFPredicate::OGE, operand, result);
-        result = rewriter.create<SelectOp>(loc, condition, operand, result);
+      case vector::CombiningKind::MINSI:
+        result = rewriter.create<MinSIOp>(loc, operand, result);
+        break;
+      case vector::CombiningKind::MINF:
+        result = rewriter.create<MinFOp>(loc, operand, result);
+        break;
+      case vector::CombiningKind::MAXUI:
+        result = rewriter.create<MaxUIOp>(loc, operand, result);
+        break;
+      case vector::CombiningKind::MAXSI:
+        result = rewriter.create<MaxSIOp>(loc, operand, result);
+        break;
+      case vector::CombiningKind::MAXF:
+        result = rewriter.create<MaxFOp>(loc, operand, result);
         break;
       case vector::CombiningKind::AND:
         result = rewriter.create<AndOp>(loc, operand, result);
         break;
       case vector::CombiningKind::OR:
         result = rewriter.create<OrOp>(loc, operand, result);
         break;
       case vector::CombiningKind::XOR:
LogicalResult matchAndRewrite(vector::MultiDimReductionOp multiReductionOp,
     // TODO: Add vector::CombiningKind attribute instead of string to
     // vector.reduction.
     auto getKindStr = [](vector::CombiningKind kind) {
       switch (kind) {
       case vector::CombiningKind::ADD:
         return "add";
       case vector::CombiningKind::MUL:
         return "mul";
-      case vector::CombiningKind::MIN:
-        return "min";
-      case vector::CombiningKind::MAX:
-        return "max";
+      case vector::CombiningKind::MINUI:
+        return "minui";
+      case vector::CombiningKind::MINSI:
+        return "minsi";
+      case vector::CombiningKind::MINF:
+        return "minf";
+      case vector::CombiningKind::MAXUI:
+        return "maxui";
+      case vector::CombiningKind::MAXSI:
+        return "maxsi";
+      case vector::CombiningKind::MAXF:
+        return "maxf";
       case vector::CombiningKind::AND:
         return "and";
       case vector::CombiningKind::OR:
         return "or";
       case vector::CombiningKind::XOR:
         return "xor";
       }
       llvm_unreachable("unknown combining kind");

mlir/test/Dialect/Linalg/vectorization.mlir

^bb0(%arg0: f32, %arg1: f32, %arg2: f32):  // no predecessors
       %1 = math.exp %arg0 : f32
       %2 = math.exp %arg1 : f32
       %3 = addf %1, %2 : f32
       %4 = addf %3, %arg2 : f32
       linalg.yield %4 : f32
     } -> tensor<5x2xf32>
   return %0 : tensor<5x2xf32>
 }
+
+// -----
+
+// CHECK-LABEL:   func @red_max_2d(
+func @red_max_2d(%arg0: tensor<4x4xf32>) -> tensor<4xf32> {
+  // CHECK: linalg.init_tensor [4] : tensor<4xf32>
+  // CHECK: vector.transfer_write {{.*}} : vector<4xf32>, tensor<4xf32>
+  // CHECK: vector.transfer_read {{.*}} : tensor<4x4xf32>, vector<4x4xf32>
+  // CHECK: vector.transfer_read {{.*}} : tensor<4xf32>, vector<4x4xf32>
+  // CHECK: maxf {{.*}} : vector<4x4xf32>
+  // CHECK: vector.multi_reduction #vector.kind<maxf>, {{.*}} [1] : vector<4x4xf32> to vector<4xf32>
+  // CHECK: vector.transfer_write {{.*}} : vector<4xf32>, tensor<4xf32>
+  %minf32 = constant -3.40282e+38 : f32
+  %init = linalg.init_tensor [4] : tensor<4xf32>
+  %fill = linalg.fill(%minf32, %init) : f32, tensor<4xf32> -> tensor<4xf32>
+  %red = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
+                                          affine_map<(d0, d1) -> (d0)>],
+                         iterator_types = ["parallel", "reduction"]}
+                         ins(%arg0 : tensor<4x4xf32>) outs(%fill : tensor<4xf32>) {
+  ^bb0(%in0: f32, %out0: f32):  // no predecessors
+    %max = maxf %in0, %out0 : f32
+    linalg.yield %max : f32
+  } -> tensor<4xf32>
+  return %red : tensor<4xf32>
+}
+
+// -----
+
+// CHECK-LABEL:   func @red_min_2d(
+func @red_min_2d(%arg0: tensor<4x4xf32>) -> tensor<4xf32> {
+  // CHECK: linalg.init_tensor [4] : tensor<4xf32>
+  // CHECK: vector.transfer_write {{.*}} : vector<4xf32>, tensor<4xf32>
+  // CHECK: vector.transfer_read {{.*}} : tensor<4x4xf32>, vector<4x4xf32>
+  // CHECK: vector.transfer_read {{.*}} : tensor<4xf32>, vector<4x4xf32>
+  // CHECK: minf {{.*}} : vector<4x4xf32>
+  // CHECK: vector.multi_reduction #vector.kind<minf>, {{.*}} [1] : vector<4x4xf32> to vector<4xf32>
+  // CHECK: vector.transfer_write {{.*}} : vector<4xf32>, tensor<4xf32>
+  %maxf32 = constant 3.40282e+38 : f32
+  %init = linalg.init_tensor [4] : tensor<4xf32>
+  %fill = linalg.fill(%maxf32, %init) : f32, tensor<4xf32> -> tensor<4xf32>
+  %red = linalg.generic {indexing_maps = [affine_map<(d0, d1) -> (d0, d1)>,
+                                          affine_map<(d0, d1) -> (d0)>],
+                         iterator_types = ["parallel", "reduction"]}
+                         ins(%arg0 : tensor<4x4xf32>) outs(%fill : tensor<4xf32>) {
+  ^bb0(%in0: f32, %out0: f32):  // no predecessors
+    %min = minf %in0, %out0 : f32
+    linalg.yield %min : f32
+  } -> tensor<4xf32>
+  return %red : tensor<4xf32>
+}
+

mlir/test/Dialect/Vector/invalid.mlir

func @reduce_unsupported_third_argument(%arg0: vector<16xf32>, %arg1: f32) -> f32 {
   // expected-error@+1 {{'vector.reduction' unsupported number of operands}}
   %0 = vector.reduction "add", %arg0, %arg1, %arg1 : vector<16xf32> into f32
 }
 
 // -----
 
 func @reduce_unsupported_accumulator_kind(%arg0: vector<16xf32>, %arg1: f32) -> f32 {
   // expected-error@+1 {{'vector.reduction' op no accumulator for reduction kind: min}}
-  %0 = vector.reduction "min", %arg0, %arg1 : vector<16xf32> into f32
+  %0 = vector.reduction "minf", %arg0, %arg1 : vector<16xf32> into f32
 }
 
 // -----
 
 func @reduce_unsupported_accumulator_type(%arg0: vector<16xi32>, %arg1: i32) -> i32 {
   // expected-error@+1 {{'vector.reduction' op no accumulator for type: 'i32'}}
   %0 = vector.reduction "add", %arg0, %arg1 : vector<16xi32> into i32
 }

mlir/test/Dialect/Vector/ops.mlir

 #contraction_to_scalar_max_accesses = [
   affine_map<(i) -> (i)>,
   affine_map<(i) -> (i)>,
   affine_map<(i) -> ()>
 ]
 #contraction_to_scalar_max_trait = {
   indexing_maps = #contraction_to_scalar_max_accesses,
   iterator_types = ["reduction"],
-  kind = #vector.kind<max>
+  kind = #vector.kind<maxf>
 }
 // CHECK-LABEL: @contraction_to_scalar_with_max
 func @contraction_to_scalar_with_max(%arg0: vector<10xf32>, %arg1: vector<10xf32>) -> f32 {
   // CHECK:      %[[C0:.*]] = constant 0.000000e+00 : f32
   %f0 = constant 0.0: f32
-  // CHECK:      %[[X:.*]] = vector.contract {indexing_maps = [#{{.*}}, #{{.*}}, #{{.*}}], iterator_types = ["reduction"], kind = #vector.kind<max>} %{{.*}}, %{{.*}}, %[[C0]] : vector<10xf32>, vector<10xf32> into f32
+  // CHECK:      %[[X:.*]] = vector.contract {indexing_maps = [#{{.*}}, #{{.*}}, #{{.*}}], iterator_types = ["reduction"], kind = #vector.kind<maxf>} %{{.*}}, %{{.*}}, %[[C0]] : vector<10xf32>, vector<10xf32> into f32
   %0 = vector.contract #contraction_to_scalar_max_trait %arg0, %arg1, %f0
     : vector<10xf32>, vector<10xf32> into f32
   // CHECK:      return %[[X]] : f32
   return %0 : f32
 }
 
 #contraction_accesses0 = [
   affine_map<(b0, f0, f1, c0, c1) -> (c0, b0, c1, f0)>,
#iterator_types1 = ["parallel", "parallel", "parallel", "parallel", "reduction",
                     "reduction"]
 #contraction_trait1 = {
   indexing_maps = #contraction_accesses1,
   iterator_types = #iterator_types1
 }
 #contraction_trait2 = {
   indexing_maps = #contraction_accesses1,
   iterator_types = #iterator_types1,
-  kind = #vector.kind<max>
+  kind = #vector.kind<maxf>
 }
 // CHECK-LABEL: @contraction
 func @contraction(%arg0 : vector<7x8x16x15xf32>, %arg1 : vector<8x16x7x5xf32>,
                   %arg2 : vector<8x15x5xf32>, %arg3 : vector<8x8x15x5xf32>,
                   %arg4 : vector<7x8x16x15xf16>, %arg5 : vector<8x16x7x5xf16>) {
   // Test contraction with batch and contracting dims.
   // CHECK: vector.contract {indexing_maps = [#{{.*}}, #{{.*}}, #{{.*}}], iterator_types = ["parallel", "parallel", "parallel", "reduction", "reduction"], kind = #vector.kind<add>} {{.*}}, {{.*}}, {{.*}} : vector<7x8x16x15xf32>, vector<8x16x7x5xf32> into vector<8x15x5xf32>
   %0 = vector.contract #contraction_trait0 %arg0, %arg1, %arg2
func @contraction(%arg0 : vector<7x8x16x15xf32>, %arg1 : vector<8x16x7x5xf32>,
   %2 = vector.contract #contraction_trait1 %arg0, %arg1, %arg3, %lhs_mask,
                                            %rhs_mask
       : vector<7x8x16x15xf32>, vector<8x16x7x5xf32> into vector<8x8x15x5xf32>
   // Test contraction with mixed type.
   // CHECK: vector.contract {indexing_maps = [#{{.*}}, #{{.*}}, #{{.*}}], iterator_types = ["parallel", "parallel", "parallel", "parallel", "reduction", "reduction"], kind = #vector.kind<add>} {{.*}}, {{.*}}, {{.*}} : vector<7x8x16x15xf16>, vector<8x16x7x5xf16> into vector<8x8x15x5xf32>
   %3 = vector.contract #contraction_trait1 %arg4, %arg5, %arg3
       : vector<7x8x16x15xf16>, vector<8x16x7x5xf16> into vector<8x8x15x5xf32>
   // Test contraction with "max" instead of "add".
-  // CHECK: vector.contract {indexing_maps = [#{{.*}}, #{{.*}}, #{{.*}}], iterator_types = ["parallel", "parallel", "parallel", "parallel", "reduction", "reduction"], kind = #vector.kind<max>} {{.*}}, {{.*}}, {{.*}} : vector<7x8x16x15xf32>, vector<8x16x7x5xf32> into vector<8x8x15x5xf32>
+  // CHECK: vector.contract {indexing_maps = [#{{.*}}, #{{.*}}, #{{.*}}], iterator_types = ["parallel", "parallel", "parallel", "parallel", "reduction", "reduction"], kind = #vector.kind<maxf>} {{.*}}, {{.*}}, {{.*}} : vector<7x8x16x15xf32>, vector<8x16x7x5xf32> into vector<8x8x15x5xf32>
   %4 = vector.contract #contraction_trait2 %arg0, %arg1, %arg3
       : vector<7x8x16x15xf32>, vector<8x16x7x5xf32> into vector<8x8x15x5xf32>
   return
 }
 
 // CHECK-LABEL: @create_vector_mask
 func @create_vector_mask() {
   // CHECK:      %[[C2:.*]] = constant 2 : index
func @reduce_fp(%arg0: vector<16xf32>, %arg1: f32) -> f32 {
   // CHECK:    vector.reduction "add", %{{.*}} : vector<16xf32> into f32
   vector.reduction "add", %arg0 : vector<16xf32> into f32
   // CHECK:    vector.reduction "add", %{{.*}}, %{{.*}} : vector<16xf32> into f32
   vector.reduction "add", %arg0, %arg1 : vector<16xf32> into f32
   // CHECK:    vector.reduction "mul", %{{.*}} : vector<16xf32> into f32
   vector.reduction "mul", %arg0 : vector<16xf32> into f32
   // CHECK:    vector.reduction "mul", %{{.*}}, %{{.*}} : vector<16xf32> into f32
   vector.reduction "mul", %arg0, %arg1 : vector<16xf32> into f32
-  // CHECK:    vector.reduction "min", %{{.*}} : vector<16xf32> into f32
-  vector.reduction "min", %arg0 : vector<16xf32> into f32
-  // CHECK:    %[[X:.*]] = vector.reduction "max", %{{.*}} : vector<16xf32> into f32
-  %0 = vector.reduction "max", %arg0 : vector<16xf32> into f32
+  // CHECK:    vector.reduction "minf", %{{.*}} : vector<16xf32> into f32
+  vector.reduction "minf", %arg0 : vector<16xf32> into f32
+  // CHECK:    %[[X:.*]] = vector.reduction "maxf", %{{.*}} : vector<16xf32> into f32
+  %0 = vector.reduction "maxf", %arg0 : vector<16xf32> into f32
   // CHECK:    return %[[X]] : f32
   return %0 : f32
 }
 
 // CHECK-LABEL: @reduce_int
 func @reduce_int(%arg0: vector<16xi32>) -> i32 {
   // CHECK:    vector.reduction "add", %{{.*}} : vector<16xi32> into i32
   vector.reduction "add", %arg0 : vector<16xi32> into i32
   // CHECK:    vector.reduction "mul", %{{.*}} : vector<16xi32> into i32
   vector.reduction "mul", %arg0 : vector<16xi32> into i32
-  // CHECK:    vector.reduction "min", %{{.*}} : vector<16xi32> into i32
-  vector.reduction "min", %arg0 : vector<16xi32> into i32
-  // CHECK:    vector.reduction "max", %{{.*}} : vector<16xi32> into i32
-  vector.reduction "max", %arg0 : vector<16xi32> into i32
+  // CHECK:    vector.reduction "minui", %{{.*}} : vector<16xi32> into i32
+  vector.reduction "minui", %arg0 : vector<16xi32> into i32
+  // CHECK:    vector.reduction "minsi", %{{.*}} : vector<16xi32> into i32
+  vector.reduction "minsi", %arg0 : vector<16xi32> into i32
+  // CHECK:    vector.reduction "maxui", %{{.*}} : vector<16xi32> into i32
+  vector.reduction "maxui", %arg0 : vector<16xi32> into i32
+  // CHECK:    vector.reduction "maxsi", %{{.*}} : vector<16xi32> into i32
+  vector.reduction "maxsi", %arg0 : vector<16xi32> into i32
   // CHECK:    vector.reduction "and", %{{.*}} : vector<16xi32> into i32
   vector.reduction "and", %arg0 : vector<16xi32> into i32
   // CHECK:    vector.reduction "or", %{{.*}} : vector<16xi32> into i32
   vector.reduction "or", %arg0 : vector<16xi32> into i32
   // CHECK:    %[[X:.*]] = vector.reduction "xor", %{{.*}} : vector<16xi32> into i32
   %0 = vector.reduction "xor", %arg0 : vector<16xi32> into i32
   // CHECK:    return %[[X]] : i32
   return %0 : i32

mlir/test/Dialect/Vector/vector-contract-matvec-transforms.mlir

 // RUN: mlir-opt %s -test-vector-contraction-conversion=vector-outerproduct=1 | FileCheck %s
 
 #matvec_accesses = [
   affine_map<(i, j) -> (i, j)>,
   affine_map<(i, j) -> (j)>,
   affine_map<(i, j) -> (i)>
 ]
 #matvec_trait = {
   indexing_maps = #matvec_accesses,
   iterator_types = ["parallel", "reduction"]
 }
 #matvecmax_trait = {
   indexing_maps = #matvec_accesses,
   iterator_types = ["parallel", "reduction"],
-  kind = #vector.kind<max>
+  kind = #vector.kind<maxf>
 }
 
 #mattransvec_accesses = [
   affine_map<(i, j) -> (j, i)>,
   affine_map<(i, j) -> (j)>,
   affine_map<(i, j) -> (i)>
 ]
 #mattransvec_trait = {

 // CHECK-SAME: %[[B:.*1]]: memref<vector<2xf32>>
 // CHECK-SAME: %[[C:.*2]]: memref<vector<2xf32>>
 // CHECK: %[[T0:.*]] = memref.load %[[A]][] : memref<vector<2x2xf32>>
 // CHECK: %[[T1:.*]] = memref.load %[[B]][] : memref<vector<2xf32>>
 // CHECK: %[[T2:.*]] = memref.load %[[C]][] : memref<vector<2xf32>>
 // CHECK: %[[T3:.*]] = vector.transpose %[[T0]], [1, 0] : vector<2x2xf32> to vector<2x2xf32>
 // CHECK: %[[T4:.*]] = vector.extract %[[T3]][0] : vector<2x2xf32>
 // CHECK: %[[T5:.*]] = vector.extract %[[T1]][0] : vector<2xf32>
-// CHECK: %[[T6:.*]] = vector.outerproduct %[[T4]], %[[T5]], %[[T2]] {kind = #vector.kind<max>} : vector<2xf32>, f32
+// CHECK: %[[T6:.*]] = vector.outerproduct %[[T4]], %[[T5]], %[[T2]] {kind = #vector.kind<maxf>} : vector<2xf32>, f32
 // CHECK: %[[T7:.*]] = vector.extract %[[T3]][1] : vector<2x2xf32>
 // CHECK: %[[T8:.*]] = vector.extract %[[T1]][1] : vector<2xf32>
-// CHECK: %[[T9:.*]] = vector.outerproduct %[[T7]], %[[T8]], %[[T6]] {kind = #vector.kind<max>} : vector<2xf32>, f32
+// CHECK: %[[T9:.*]] = vector.outerproduct %[[T7]], %[[T8]], %[[T6]] {kind = #vector.kind<maxf>} : vector<2xf32>, f32
 // CHECK: memref.store %[[T9]], %[[C]][] : memref<vector<2xf32>>
 // CHECK: return
 func @matvecmax2x2(%arg0: memref<vector<2x2xf32>>, %arg1: memref<vector<2xf32>>,
                                                    %arg2: memref<vector<2xf32>>) {
   %A = memref.load %arg0[] : memref<vector<2x2xf32>>
   %x = memref.load %arg1[] : memref<vector<2xf32>>
   %b = memref.load %arg2[] : memref<vector<2xf32>>
   %0 = vector.contract #matvecmax_trait %A, %x, %b : vector<2x2xf32>, vector<2xf32> into vector<2xf32>

mlir/test/Dialect/Vector/vector-multi-reduction-outer-lowering.mlir

 //       CHECK:   %[[RV01:.+]] = mulf %[[V1]], %[[V0]] : vector<2xf32>
 //       CHECK:   %[[V2:.+]] = vector.extract %[[TRANSPOSED]][2] : vector<4x2xf32>
 //       CHECK:   %[[RV012:.+]] = mulf %[[V2]], %[[RV01]] : vector<2xf32>
 //       CHECK:   %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xf32>
 //       CHECK:   %[[RESULT_VEC:.+]] = mulf %[[V3]], %[[RV012]] : vector<2xf32>
 //       CHECK:   return %[[RESULT_VEC]] : vector<2xf32>
 
 func @vector_multi_reduction_min(%arg0: vector<2x4xf32>) -> vector<2xf32> {
-    %0 = vector.multi_reduction #vector.kind<min>, %arg0 [1] : vector<2x4xf32> to vector<2xf32>
+    %0 = vector.multi_reduction #vector.kind<minf>, %arg0 [1] : vector<2x4xf32> to vector<2xf32>
     return %0 : vector<2xf32>
 }
 
 // CHECK-LABEL: func @vector_multi_reduction_min
 //  CHECK-SAME:   %[[INPUT:.+]]: vector<2x4xf32>
 //       CHECK:   %[[TRANSPOSED:.+]] = vector.transpose %[[INPUT]], [1, 0] : vector<2x4xf32> to vector<4x2xf32>
 //       CHECK:   %[[V0:.+]] = vector.extract %[[TRANSPOSED]][0] : vector<4x2xf32>
 //       CHECK:   %[[V1:.+]] = vector.extract %[[TRANSPOSED]][1] : vector<4x2xf32>
-//       CHECK:   %[[C0:.+]] = cmpf olt, %[[V1]], %[[V0]] : vector<2xf32>
-//       CHECK:   %[[RV01:.+]] = select %[[C0]], %[[V1]], %[[V0]] : vector<2xi1>, vector<2xf32>
+//       CHECK:   %[[RV01:.+]] = minf %[[V1]], %[[V0]] : vector<2xf32>
 //       CHECK:   %[[V2:.+]] = vector.extract %[[TRANSPOSED]][2] : vector<4x2xf32>
-//       CHECK:   %[[C1:.+]] = cmpf olt, %[[V2]], %[[RV01]] : vector<2xf32>
-//       CHECK:   %[[RV012:.+]] = select %[[C1]], %[[V2]], %[[RV01]] : vector<2xi1>, vector<2xf32>
+//       CHECK:   %[[RV012:.+]] = minf %[[V2]], %[[RV01]] : vector<2xf32>
 //       CHECK:   %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xf32>
-//       CHECK:   %[[C2:.+]] = cmpf olt, %[[V3]], %[[RV012]] : vector<2xf32>
-//       CHECK:   %[[RESULT_VEC:.+]] = select %[[C2]], %[[V3]], %[[RV012]] : vector<2xi1>, vector<2xf32>
+//       CHECK:   %[[RESULT_VEC:.+]] = minf %[[V3]], %[[RV012]] : vector<2xf32>
 //       CHECK:   return %[[RESULT_VEC]] : vector<2xf32>
 
 func @vector_multi_reduction_max(%arg0: vector<2x4xf32>) -> vector<2xf32> {
-    %0 = vector.multi_reduction #vector.kind<max>, %arg0 [1] : vector<2x4xf32> to vector<2xf32>
+    %0 = vector.multi_reduction #vector.kind<maxf>, %arg0 [1] : vector<2x4xf32> to vector<2xf32>
     return %0 : vector<2xf32>
 }
 
 // CHECK-LABEL: func @vector_multi_reduction_max
 //  CHECK-SAME:   %[[INPUT:.+]]: vector<2x4xf32>
 //       CHECK:   %[[TRANSPOSED:.+]] = vector.transpose %[[INPUT]], [1, 0] : vector<2x4xf32> to vector<4x2xf32>
 //       CHECK:   %[[V0:.+]] = vector.extract %[[TRANSPOSED]][0] : vector<4x2xf32>
 //       CHECK:   %[[V1:.+]] = vector.extract %[[TRANSPOSED]][1] : vector<4x2xf32>
-//       CHECK:   %[[C0:.+]] = cmpf oge, %[[V1]], %[[V0]] : vector<2xf32>
-//       CHECK:   %[[RV01:.+]] = select %[[C0]], %[[V1]], %[[V0]] : vector<2xi1>, vector<2xf32>
+//       CHECK:   %[[RV01:.+]] = maxf %[[V1]], %[[V0]] : vector<2xf32>
 //       CHECK:   %[[V2:.+]] = vector.extract %[[TRANSPOSED]][2] : vector<4x2xf32>
-//       CHECK:   %[[C1:.+]] = cmpf oge, %[[V2]], %[[RV01]] : vector<2xf32>
-//       CHECK:   %[[RV012:.+]] = select %[[C1]], %[[V2]], %[[RV01]] : vector<2xi1>, vector<2xf32>
+//       CHECK:   %[[RV012:.+]] = maxf %[[V2]], %[[RV01]] : vector<2xf32>
 //       CHECK:   %[[V3:.+]] = vector.extract %[[TRANSPOSED]][3] : vector<4x2xf32>
-//       CHECK:   %[[C2:.+]] = cmpf oge, %[[V3]], %[[RV012]] : vector<2xf32>
-//       CHECK:   %[[RESULT_VEC:.+]] = select %[[C2]], %[[V3]], %[[RV012]] : vector<2xi1>, vector<2xf32>
+//       CHECK:   %[[RESULT_VEC:.+]] = maxf %[[V3]], %[[RV012]] : vector<2xf32>
 //       CHECK:   return %[[RESULT_VEC]] : vector<2xf32>
 
 func @vector_multi_reduction_and(%arg0: vector<2x4xi32>) -> vector<2xi32> {
     %0 = vector.multi_reduction #vector.kind<and>, %arg0 [1] : vector<2x4xi32> to vector<2xi32>
     return %0 : vector<2xi32>
 }
 
 // CHECK-LABEL: func @vector_multi_reduction_and

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f32-reassoc.mlir

func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction "add", %v2 : vector<64xf32> into f32
   vector.print %0 : f32
   // CHECK: 67
   %1 = vector.reduction "mul", %v2 : vector<64xf32> into f32
   vector.print %1 : f32
   // CHECK: 6
-  %2 = vector.reduction "min", %v2 : vector<64xf32> into f32
+  %2 = vector.reduction "minf", %v2 : vector<64xf32> into f32
   vector.print %2 : f32
   // CHECK: 1
-  %3 = vector.reduction "max", %v2 : vector<64xf32> into f32
+  %3 = vector.reduction "maxf", %v2 : vector<64xf32> into f32
   vector.print %3 : f32
   // CHECK: 3
 
   return
 }

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f32.mlir

func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction "add", %v9 : vector<10xf32> into f32
   vector.print %0 : f32
   // CHECK: -7.75
   %1 = vector.reduction "mul", %v9 : vector<10xf32> into f32
   vector.print %1 : f32
   // CHECK: -5760
-  %2 = vector.reduction "min", %v9 : vector<10xf32> into f32
+  %2 = vector.reduction "minf", %v9 : vector<10xf32> into f32
   vector.print %2 : f32
   // CHECK: -16
-  %3 = vector.reduction "max", %v9 : vector<10xf32> into f32
+  %3 = vector.reduction "maxf", %v9 : vector<10xf32> into f32
   vector.print %3 : f32
   // CHECK: 5
 
   return
 }

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f64-reassoc.mlir

func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction "add", %v2 : vector<64xf64> into f64
   vector.print %0 : f64
   // CHECK: 67
   %1 = vector.reduction "mul", %v2 : vector<64xf64> into f64
   vector.print %1 : f64
   // CHECK: 6
-  %2 = vector.reduction "min", %v2 : vector<64xf64> into f64
+  %2 = vector.reduction "minf", %v2 : vector<64xf64> into f64
   vector.print %2 : f64
   // CHECK: 1
-  %3 = vector.reduction "max", %v2 : vector<64xf64> into f64
+  %3 = vector.reduction "maxf", %v2 : vector<64xf64> into f64
   vector.print %3 : f64
   // CHECK: 3
 
   return
 }

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-f64.mlir

func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction "add", %v9 : vector<10xf64> into f64
   vector.print %0 : f64
   // CHECK: -7.75
   %1 = vector.reduction "mul", %v9 : vector<10xf64> into f64
   vector.print %1 : f64
   // CHECK: -5760
-  %2 = vector.reduction "min", %v9 : vector<10xf64> into f64
+  %2 = vector.reduction "minf", %v9 : vector<10xf64> into f64
   vector.print %2 : f64
   // CHECK: -16
-  %3 = vector.reduction "max", %v9 : vector<10xf64> into f64
+  %3 = vector.reduction "maxf", %v9 : vector<10xf64> into f64
   vector.print %3 : f64
   // CHECK: 5
 
   return
 }

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i32.mlir

func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction "add", %v9 : vector<10xi32> into i32
   vector.print %0 : i32
   // CHECK: -88
   %1 = vector.reduction "mul", %v9 : vector<10xi32> into i32
   vector.print %1 : i32
   // CHECK: -1228800
-  %2 = vector.reduction "min", %v9 : vector<10xi32> into i32
+  %2 = vector.reduction "minsi", %v9 : vector<10xi32> into i32
   vector.print %2 : i32
   // CHECK: -80
-  %3 = vector.reduction "max", %v9 : vector<10xi32> into i32
+  %3 = vector.reduction "maxsi", %v9 : vector<10xi32> into i32
   vector.print %3 : i32
   // CHECK: 5
   %4 = vector.reduction "and", %v9 : vector<10xi32> into i32
   vector.print %4 : i32
   // CHECK: 0
   %5 = vector.reduction "or", %v9 : vector<10xi32> into i32
   vector.print %5 : i32
   // CHECK: -1
   %6 = vector.reduction "xor", %v9 : vector<10xi32> into i32
   vector.print %6 : i32
   // CHECK: -68
 
   return
 }

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i4.mlir

func @entry() {
   %0 = vector.reduction "add", %v : vector<24xi4> into i4
   vector.print %0 : i4
   // CHECK: 4
 
   %1 = vector.reduction "mul", %v : vector<24xi4> into i4
   vector.print %1 : i4
   // CHECK: 0
 
-  %2 = vector.reduction "min", %v : vector<24xi4> into i4
+  %2 = vector.reduction "minsi", %v : vector<24xi4> into i4
   vector.print %2 : i4
   // CHECK: -8
 
-  %3 = vector.reduction "max", %v : vector<24xi4> into i4
+  %3 = vector.reduction "maxsi", %v : vector<24xi4> into i4
   vector.print %3 : i4
   // CHECK: 7
 
   %4 = vector.reduction "and", %v : vector<24xi4> into i4
   vector.print %4 : i4
   // CHECK: 0
 
   %5 = vector.reduction "or", %v : vector<24xi4> into i4

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-i64.mlir

func @entry() {
   // Various vector reductions. Not full functional unit tests, but
   // a simple integration test to see if the code runs end-to-end.
   %0 = vector.reduction "add", %v9 : vector<10xi64> into i64
   vector.print %0 : i64
   // CHECK: -88
   %1 = vector.reduction "mul", %v9 : vector<10xi64> into i64
   vector.print %1 : i64
   // CHECK: -1228800
-  %2 = vector.reduction "min", %v9 : vector<10xi64> into i64
+  %2 = vector.reduction "minsi", %v9 : vector<10xi64> into i64
   vector.print %2 : i64
   // CHECK: -80
-  %3 = vector.reduction "max", %v9 : vector<10xi64> into i64
+  %3 = vector.reduction "maxsi", %v9 : vector<10xi64> into i64
   vector.print %3 : i64
   // CHECK: 5
   %4 = vector.reduction "and", %v9 : vector<10xi64> into i64
   vector.print %4 : i64
   // CHECK: 0
   %5 = vector.reduction "or", %v9 : vector<10xi64> into i64
   vector.print %5 : i64
   // CHECK: -1
   %6 = vector.reduction "xor", %v9 : vector<10xi64> into i64
   vector.print %6 : i64
   // CHECK: -68
 
   return
 }

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-si4.mlir

func @entry() {
   %0 = vector.reduction "add", %v : vector<16xsi4> into si4
   vector.print %0 : si4
   // CHECK: -8
 
   %1 = vector.reduction "mul", %v : vector<16xsi4> into si4
   vector.print %1 : si4
   // CHECK: 0
 
-  %2 = vector.reduction "min", %v : vector<16xsi4> into si4
+  %2 = vector.reduction "minsi", %v : vector<16xsi4> into si4
   vector.print %2 : si4
   // CHECK: -8
 
-  %3 = vector.reduction "max", %v : vector<16xsi4> into si4
+  %3 = vector.reduction "maxsi", %v : vector<16xsi4> into si4
   vector.print %3 : si4
   // CHECK: 7
 
   %4 = vector.reduction "and", %v : vector<16xsi4> into si4
   vector.print %4 : si4
   // CHECK: 0
 
   %5 = vector.reduction "or", %v : vector<16xsi4> into si4

mlir/test/Integration/Dialect/Vector/CPU/test-reductions-ui4.mlir

func @entry() {
   %0 = vector.reduction "add", %v : vector<16xui4> into ui4
   vector.print %0 : ui4
   // CHECK: 8
 
   %1 = vector.reduction "mul", %v : vector<16xui4> into ui4
   vector.print %1 : ui4
   // CHECK: 0
 
-  %2 = vector.reduction "min", %v : vector<16xui4> into ui4
+  %2 = vector.reduction "minui", %v : vector<16xui4> into ui4
   vector.print %2 : ui4
   // CHECK: 0
 
-  %3 = vector.reduction "max", %v : vector<16xui4> into ui4
+  %3 = vector.reduction "maxui", %v : vector<16xui4> into ui4
   vector.print %3 : ui4
   // CHECK: 15
 
   %4 = vector.reduction "and", %v : vector<16xui4> into ui4
   vector.print %4 : ui4
   // CHECK: 0
 
   %5 = vector.reduction "or", %v : vector<16xui4> into ui4