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Differential D109536

[AMDGPU] Switch PostRA sched to MachineSched
ClosedPublic

Authored by Joe_Nash on Sep 9 2021, 12:16 PM.

Details

Reviewers
arsenm
rampitec
kerbowa
dstuttard
foad
critson
rdomingu
Commits
rG3ce1b9631a50: [AMDGPU] Switch PostRA sched to MachineSched
Summary

Use GCNHazardRecognizer in postra sched.
Updated tests for the new schedules.

Diff Detail

Event Timeline

Joe_Nash created this revision.Sep 9 2021, 12:16 PM
Herald added subscribers: wenlei, asbirlea, arphaman and 9 others. · View Herald TranscriptSep 9 2021, 12:16 PM
Joe_Nash requested review of this revision.Sep 9 2021, 12:16 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 9 2021, 12:16 PM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B123289: Diff 371689.Sep 9 2021, 12:16 PM
arsenm accepted this revision.Sep 9 2021, 12:32 PM
This revision is now accepted and ready to land.Sep 9 2021, 12:32 PM
Joe_Nash updated this revision to Diff 371699.Sep 9 2021, 12:59 PM

rebase on 7f48a8aedea7551318f021db5301b481e66712fb

Harbormaster completed remote builds in B123296: Diff 371699.Sep 9 2021, 2:13 PM
foad added a comment.Sep 9 2021, 10:46 PM

Can you give some rationale for the change in the commit message?

Joe_Nash updated this revision to Diff 371906.Sep 10 2021, 6:18 AM

update llc-pipeline.ll and commit message

Harbormaster completed remote builds in B123433: Diff 371906.Sep 10 2021, 6:59 AM
Closed by commit rG3ce1b9631a50: [AMDGPU] Switch PostRA sched to MachineSched (authored by Joe_Nash). · Explain WhySep 14 2021, 12:28 PM
This revision was automatically updated to reflect the committed changes.
Joe_Nash added a commit: rG3ce1b9631a50: [AMDGPU] Switch PostRA sched to MachineSched.
foad added a comment.Sep 15 2021, 1:01 AM
In D109536#2993511, @foad wrote:

Can you give some rationale for the change in the commit message?

Or failing that, leave a comment here with the rationale, just for the historical record?

Joe_Nash added a comment.Sep 15 2021, 6:28 AM
In D109536#3001188, @foad wrote:
In D109536#2993511, @foad wrote:

Can you give some rationale for the change in the commit message?

Or failing that, leave a comment here with the rationale, just for the historical record?

This was my updated commit message. I didn't expect it to update the description on phab, but apparently it also didn't make it into the landed patch either. Arcanist did something I didn't expect.

[AMDGPU] Switch PostRA sched to MachineSched

The PostRA Machine scheduler is more flexible and extensible than
the old PostRA top-down list scheduler. In particular it will
make better use of cluster edges. Testing shows no regressions
on graphics workloads relative to the old scheduler.

GCNHazardRecognizer is still used as the PostRA sched hazard rec.
Updated tests for the new schedules.

Large Diff

This large diff affects 204 files. Files without inline comments have been collapsed. Expand All Files

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Diff 371689

llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp

llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

llvm/lib/Target/AMDGPU/GCNSubtarget.h

llvm/lib/Target/AMDGPU/SIInstrInfo.h

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/floor.f64.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.dec.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.o.dim.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.d16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll

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llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

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llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll

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llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll

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llvm/test/CodeGen/AMDGPU/add3.ll

llvm/test/CodeGen/AMDGPU/agpr-remat.ll

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llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll

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llvm/test/CodeGen/AMDGPU/call-preserved-registers.ll

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llvm/test/CodeGen/AMDGPU/fp-min-max-atomics.ll

llvm/test/CodeGen/AMDGPU/fp64-atomics-gfx90a.ll

llvm/test/CodeGen/AMDGPU/fp_to_sint.ll

llvm/test/CodeGen/AMDGPU/fpext.f16.ll

llvm/test/CodeGen/AMDGPU/fpow.ll

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llvm/test/CodeGen/AMDGPU/frame-setup-without-sgpr-to-vgpr-spills.ll

llvm/test/CodeGen/AMDGPU/frem.ll

llvm/test/CodeGen/AMDGPU/fshl.ll

llvm/test/CodeGen/AMDGPU/fshr.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll

llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll

llvm/test/CodeGen/AMDGPU/half.ll

llvm/test/CodeGen/AMDGPU/idiv-licm.ll

llvm/test/CodeGen/AMDGPU/idot2.ll

llvm/test/CodeGen/AMDGPU/idot4s.ll

llvm/test/CodeGen/AMDGPU/idot4u.ll

llvm/test/CodeGen/AMDGPU/idot8s.ll

llvm/test/CodeGen/AMDGPU/idot8u.ll

llvm/test/CodeGen/AMDGPU/insert_vector_elt.ll

llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

llvm/test/CodeGen/AMDGPU/kernel-args.ll

llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll

llvm/test/CodeGen/AMDGPU/llvm.fma.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.fmuladd.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.mulo.ll

llvm/test/CodeGen/AMDGPU/llvm.round.f64.ll

llvm/test/CodeGen/AMDGPU/load-constant-i16.ll

llvm/test/CodeGen/AMDGPU/load-global-i16.ll

llvm/test/CodeGen/AMDGPU/load-local.128.ll

llvm/test/CodeGen/AMDGPU/load-local.96.ll

llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll

llvm/test/CodeGen/AMDGPU/lshl64-to-32.ll

llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll

llvm/test/CodeGen/AMDGPU/max.i16.ll

llvm/test/CodeGen/AMDGPU/memory-legalizer-local-nontemporal.ll

llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll

llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll

llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll

llvm/test/CodeGen/AMDGPU/memory_clause.ll

llvm/test/CodeGen/AMDGPU/min.ll

llvm/test/CodeGen/AMDGPU/move-addr64-rsrc-dead-subreg-writes.ll

llvm/test/CodeGen/AMDGPU/mul.i16.ll

llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll

llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll

llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll

llvm/test/CodeGen/AMDGPU/saddo.ll

llvm/test/CodeGen/AMDGPU/saddsat.ll

llvm/test/CodeGen/AMDGPU/sdiv.ll

llvm/test/CodeGen/AMDGPU/sdiv64.ll

llvm/test/CodeGen/AMDGPU/select.f16.ll

llvm/test/CodeGen/AMDGPU/select64.ll

llvm/test/CodeGen/AMDGPU/shift-i128.ll

llvm/test/CodeGen/AMDGPU/shl.ll

llvm/test/CodeGen/AMDGPU/shl.v2i16.ll

llvm/test/CodeGen/AMDGPU/shl_add_ptr.ll

llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll

llvm/test/CodeGen/AMDGPU/sign_extend.ll

llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll

llvm/test/CodeGen/AMDGPU/skip-if-dead.ll

llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll

llvm/test/CodeGen/AMDGPU/sra.ll

llvm/test/CodeGen/AMDGPU/srem64.ll

llvm/test/CodeGen/AMDGPU/srl.ll

llvm/test/CodeGen/AMDGPU/ssubsat.ll

llvm/test/CodeGen/AMDGPU/stack-realign.ll

llvm/test/CodeGen/AMDGPU/store-local.128.ll

llvm/test/CodeGen/AMDGPU/store-local.96.ll

llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll

llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll

llvm/test/CodeGen/AMDGPU/trunc.ll

llvm/test/CodeGen/AMDGPU/uaddsat.ll

llvm/test/CodeGen/AMDGPU/udiv64.ll

llvm/test/CodeGen/AMDGPU/udivrem.ll

llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll

llvm/test/CodeGen/AMDGPU/urem64.ll

llvm/test/CodeGen/AMDGPU/usubsat.ll

llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll

llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll

llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll

llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll

llvm/test/CodeGen/AMDGPU/widen-smrd-loads.ll

llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

llvm/test/CodeGen/AMDGPU/xor3.ll