[X86][AVX] Add missing X86ISD::VBROADCAST(128->256) isel patterns for AVX1 targets

[RKSimon]

Summary

An alternative to D109348, this adds fallback broadcast patterns on AVX1 targets instead.

I've added AVX2 test coverage to help show a missing fold - where the vbroadcastsd_ymm(vbroadcastss_load_xmm()) should be foldable to a single vbroadcastss_load_ymm() on AVX1 and AVX2 targets if we create the broadcast nodes.

[yubing]

llvm/test/CodeGen/X86/combine-concatvectors.ll

44

Thanks for creating this bugfix. This case only cover the code:

def : Pat<(v4f64 (X86VBroadcast v2f64:$src)),
          (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
            (v2f64 (VMOVDDUPrr VR128:$src)), sub_xmm),
            (v2f64 (VMOVDDUPrr VR128:$src)), 1)>;

I think we'd better add more cases.

[RKSimon]

llvm/test/CodeGen/X86/combine-concatvectors.ll

44

Its proving tricky to create tests for the other types, what about just adding this one isel pattern initially?

[yubing]

llvm/test/CodeGen/X86/combine-concatvectors.ll

44

I am OK with that.

[yubing]

This comment was removed by yubing.

[yubing]

LGTM

llvm/lib/Target/X86/X86InstrSSE.td

let Predicates = [HasAVX1Only] in {
   def : Pat<(v8f32 (X86VBroadcast FR32:$src)),
             (VINSERTF128rr (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)),
               (v4f32 (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)), sub_xmm),
               (v4f32 (VPERMILPSri (v4f32 (COPY_TO_REGCLASS FR32:$src, VR128)), 0)), 1)>;
   def : Pat<(v4f64 (X86VBroadcast FR64:$src)),
             (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
               (v2f64 (VMOVDDUPrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))), sub_xmm),
               (v2f64 (VMOVDDUPrr (v2f64 (COPY_TO_REGCLASS FR64:$src, VR128)))), 1)>;
+  def : Pat<(v4f64 (X86VBroadcast v2f64:$src)),
+            (VINSERTF128rr (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)),
+              (v2f64 (VMOVDDUPrr VR128:$src)), sub_xmm),
+              (v2f64 (VMOVDDUPrr VR128:$src)), 1)>;
 
   def : Pat<(v4i32 (X86VBroadcast GR32:$src)),
             (VPSHUFDri (VMOVDI2PDIrr GR32:$src), 0)>;
   def : Pat<(v8i32 (X86VBroadcast GR32:$src)),
             (VINSERTF128rr (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)),
               (v4i32 (VPSHUFDri (VMOVDI2PDIrr GR32:$src), 0)), sub_xmm),
               (v4i32 (VPSHUFDri (VMOVDI2PDIrr GR32:$src), 0)), 1)>;
   def : Pat<(v4i64 (X86VBroadcast GR64:$src)),

llvm/test/CodeGen/X86/combine-concatvectors.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx  | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx  | FileCheck %s --check-prefixes=CHECK,AVX1
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2
 
 define void @PR32957(<2 x float>* %in, <8 x float>* %out) {
 ; CHECK-LABEL: PR32957:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vmovsd {{.*#+}} xmm0 = mem[0],zero
 ; CHECK-NEXT:    vmovaps %ymm0, (%rsi)
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
bar:
   %extr = extractvalue { i8, double } %val, 1
   %bc = bitcast double %extr to <2 x float>
   br label %baz
 
 baz:
   %extr1 = extractelement <2 x float> %bc, i64 0
   unreachable
 }
+
+@qa_ = external unnamed_addr global [49216 x i8], align 32
+
+define void @concat_of_broadcast_v2f64_v4f64() {
+; AVX1-LABEL: concat_of_broadcast_v2f64_v4f64:
+; AVX1:       # %bb.0: # %alloca_0
+; AVX1-NEXT:    movq qa_@GOTPCREL(%rip), %rax
+; AVX1-NEXT:    movl $1091567616, 30256(%rax) # imm = 0x41100000
+; AVX1-NEXT:    movabsq $4294967297, %rcx # imm = 0x100000001
+; AVX1-NEXT:    movq %rcx, 46348(%rax)
+; AVX1-NEXT:    vmovaps {{.*#+}} xmm0 = <1.0E+0,1.0E+0,u,u>
+; AVX1-NEXT:    vmovddup {{.*#+}} xmm1 = xmm0[0,0]
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm1, %ymm1
+; AVX1-NEXT:    vmovups %ymm1, 48296(%rax)
+; AVX1-NEXT:    vmovlps %xmm0, 47372(%rax)
+; AVX1-NEXT:    vzeroupper
+; AVX1-NEXT:    retq
+;
+; AVX2-LABEL: concat_of_broadcast_v2f64_v4f64:
+; AVX2:       # %bb.0: # %alloca_0
+; AVX2-NEXT:    movq qa_@GOTPCREL(%rip), %rax
+; AVX2-NEXT:    movl $1091567616, 30256(%rax) # imm = 0x41100000
+; AVX2-NEXT:    movabsq $4294967297, %rcx # imm = 0x100000001
+; AVX2-NEXT:    movq %rcx, 46348(%rax)
+; AVX2-NEXT:    vbroadcastss {{.*#+}} xmm0 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0]
+; AVX2-NEXT:    vbroadcastsd %xmm0, %ymm1
+; AVX2-NEXT:    vmovups %ymm1, 48296(%rax)
+; AVX2-NEXT:    vmovlps %xmm0, 47372(%rax)
+; AVX2-NEXT:    vzeroupper
+; AVX2-NEXT:    retq
+alloca_0:
+  store float 9.000000e+00, float* bitcast (i8* getelementptr inbounds ([49216 x i8], [49216 x i8]* @qa_, i64 0, i64 30256) to float*), align 16
+  store <2 x i32> <i32 1, i32 1>, <2 x i32>* bitcast (i8* getelementptr inbounds ([49216 x i8], [49216 x i8]* @qa_, i64 0, i64 46348) to <2 x i32>*), align 4
+  br label %loop.4942
+
+loop.4942:                                        ; preds = %loop.4942, %alloca_0
+  br i1 undef, label %loop.4942, label %ifmerge.1298
+
+ifmerge.1298:                                     ; preds = %loop.4942
+  %gepload4638 = load float, float* bitcast (i8* getelementptr inbounds ([49216 x i8], [49216 x i8]* @qa_, i64 0, i64 28324) to float*), align 4
+  store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (i8* getelementptr inbounds ([49216 x i8], [49216 x i8]* @qa_, i64 0, i64 48296) to <2 x float>*), align 8
+  store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (i8* getelementptr inbounds ([49216 x i8], [49216 x i8]* @qa_, i64 0, i64 48304) to <2 x float>*), align 16
+  store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (i8* getelementptr inbounds ([49216 x i8], [49216 x i8]* @qa_, i64 0, i64 48312) to <2 x float>*), align 8
+  store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (i8* getelementptr inbounds ([49216 x i8], [49216 x i8]* @qa_, i64 0, i64 48320) to <2 x float>*), align 32
+  store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (i8* getelementptr inbounds ([49216 x i8], [49216 x i8]* @qa_, i64 0, i64 47372) to <2 x float>*), align 4
+  ret void
+}