[AArch64][MC] Merge FeaturePMU into FeaturePerfMon

[vhscampos]

Summary

FeaturePMU was created in AArch64 to accommodate one missing system
register, PMMIR_EL1, in commit ffcd7698aea7bcbb2b4edffc484793e1ff47b85d.

However, the Performance Monitors extension already had a target
feature, which is called FeaturePerfMon. Therefore, FeaturePMU is
redundant.

This patch removes FeaturePMU and merges its contents into
FeaturePerfMon.

[dnsampaio]

LGTM.

[rsandifo-arm]

Sorry to ask about an already-closed ticket, but: it looks like this makes the register unconditionally available, rather than making it conditional on FeaturePerfMon. Is that the intended behaviour? GNU as does still require v8.4 for this register.

Also, I think the register should be marked read-only rather than read-write.

[vhscampos]

Hi. Yes, it is intended behaviour. New system registers are usually available unconditionally. Typically only instructions are conditioned on target features.

For example, all the remaining PMU system registers are widely available.

About being read-only, it seems you are right. This is a bug. Thanks for noticing.

llvm/lib/Target/AArch64/AArch64.td

def FeatureAMVS : SubtargetFeature<
     "amvs", "HasAMVS", "true",
     "Enable v8.6-A Activity Monitors Virtualization support",
     [FeatureAM]>;
 
 def FeatureSEL2 : SubtargetFeature<
     "sel2", "HasSEL2", "true",
     "Enable v8.4-A Secure Exception Level 2 extension">;
 
-def FeaturePMU : SubtargetFeature<
-    "pmu", "HasPMU", "true",
-    "Enable v8.4-A PMU extension">;
-
 def FeatureTLB_RMI : SubtargetFeature<
     "tlb-rmi", "HasTLB_RMI", "true",
     "Enable v8.4-A TLB Range and Maintenance Instructions">;
 
 def FeatureFlagM : SubtargetFeature<
     "flagm", "HasFlagM", "true",
     "Enable v8.4-A Flag Manipulation Instructions">;
 

 
 def HasV8_3aOps : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
   "Support ARM v8.3a instructions", [HasV8_2aOps, FeatureRCPC, FeaturePAuth,
   FeatureJS, FeatureCCIDX, FeatureComplxNum]>;
 
 def HasV8_4aOps : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
   "Support ARM v8.4a instructions", [HasV8_3aOps, FeatureDotProd,
   FeatureNV, FeatureMPAM, FeatureDIT,
-  FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeaturePMU, FeatureTLB_RMI,
+  FeatureTRACEV8_4, FeatureAM, FeatureSEL2, FeatureTLB_RMI,
   FeatureFlagM, FeatureRCPC_IMMO]>;
 
 def HasV8_5aOps : SubtargetFeature<
   "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
   [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
    FeatureSSBS, FeatureSB, FeaturePredRes, FeatureCacheDeepPersist,
    FeatureBranchTargetId]>;
 

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def HasTRACEV8_4         : Predicate<"Subtarget->hasTRACEV8_4()">,
                        AssemblerPredicate<(all_of FeatureTRACEV8_4), "tracev8.4">;
 
 def HasAM            : Predicate<"Subtarget->hasAM()">,
                        AssemblerPredicate<(all_of FeatureAM), "am">;
 
 def HasSEL2          : Predicate<"Subtarget->hasSEL2()">,
                        AssemblerPredicate<(all_of FeatureSEL2), "sel2">;
 
-def HasPMU           : Predicate<"Subtarget->hasPMU()">,
-                       AssemblerPredicate<(all_of FeaturePMU), "pmu">;
-
 def HasTLB_RMI          : Predicate<"Subtarget->hasTLB_RMI()">,
                        AssemblerPredicate<(all_of FeatureTLB_RMI), "tlb-rmi">;
 
 def HasFlagM         : Predicate<"Subtarget->hasFlagM()">,
                        AssemblerPredicate<(all_of FeatureFlagM), "flagm">;
 
 def HasRCPC_IMMO      : Predicate<"Subtarget->hasRCPCImm()">,
                        AssemblerPredicate<(all_of FeatureRCPC_IMMO), "rcpc-immo">;

llvm/lib/Target/AArch64/AArch64Subtarget.h

protected:
 
   // ARMv8.4 extensions
   bool HasNV = false;
   bool HasMPAM = false;
   bool HasDIT = false;
   bool HasTRACEV8_4 = false;
   bool HasAM = false;
   bool HasSEL2 = false;
-  bool HasPMU = false;
   bool HasTLB_RMI = false;
   bool HasFlagM = false;
   bool HasRCPC_IMMO = false;
 
   bool HasLSLFast = false;
   bool HasRCPC = false;
   bool HasAggressiveFMA = false;
 
public:
   bool hasTRACEV8_4() const { return HasTRACEV8_4; }
   bool hasAM() const { return HasAM; }
   bool hasAMVS() const { return HasAMVS; }
   bool hasXS() const { return HasXS; }
   bool hasWFxT() const { return HasWFxT; }
   bool hasHCX() const { return HasHCX; }
   bool hasLS64() const { return HasLS64; }
   bool hasSEL2() const { return HasSEL2; }
-  bool hasPMU() const { return HasPMU; }
   bool hasTLB_RMI() const { return HasTLB_RMI; }
   bool hasFlagM() const { return HasFlagM; }
   bool hasRCPC_IMMO() const { return HasRCPC_IMMO; }
 
   bool addrSinkUsingGEPs() const override {
     // Keeping GEPs inbounds is important for exploiting AArch64
     // addressing-modes in ILP32 mode.
     return useAA() || isTargetILP32();

llvm/lib/Target/AArch64/AArch64SystemOperands.td

 def : RWSysReg<"PMSELR_EL0",         0b11, 0b011, 0b1001, 0b1100, 0b101>;
 def : RWSysReg<"PMCCNTR_EL0",        0b11, 0b011, 0b1001, 0b1101, 0b000>;
 def : RWSysReg<"PMXEVTYPER_EL0",     0b11, 0b011, 0b1001, 0b1101, 0b001>;
 def : RWSysReg<"PMXEVCNTR_EL0",      0b11, 0b011, 0b1001, 0b1101, 0b010>;
 def : RWSysReg<"PMUSERENR_EL0",      0b11, 0b011, 0b1001, 0b1110, 0b000>;
 def : RWSysReg<"PMINTENSET_EL1",     0b11, 0b000, 0b1001, 0b1110, 0b001>;
 def : RWSysReg<"PMINTENCLR_EL1",     0b11, 0b000, 0b1001, 0b1110, 0b010>;
 def : RWSysReg<"PMOVSSET_EL0",       0b11, 0b011, 0b1001, 0b1110, 0b011>;
+def : RWSysReg<"PMMIR_EL1",          0b11, 0b000, 0b1001, 0b1110, 0b110>;
 def : RWSysReg<"MAIR_EL1",           0b11, 0b000, 0b1010, 0b0010, 0b000>;
 def : RWSysReg<"MAIR_EL2",           0b11, 0b100, 0b1010, 0b0010, 0b000>;
 def : RWSysReg<"MAIR_EL3",           0b11, 0b110, 0b1010, 0b0010, 0b000>;
 def : RWSysReg<"AMAIR_EL1",          0b11, 0b000, 0b1010, 0b0011, 0b000>;
 def : RWSysReg<"AMAIR_EL2",          0b11, 0b100, 0b1010, 0b0011, 0b000>;
 def : RWSysReg<"AMAIR_EL3",          0b11, 0b110, 0b1010, 0b0011, 0b000>;
 def : RWSysReg<"VBAR_EL1",           0b11, 0b000, 0b1100, 0b0000, 0b000>;
 def : RWSysReg<"VBAR_EL2",           0b11, 0b100, 0b1100, 0b0000, 0b000>;

 def : RWSysReg<"CNTHPS_CVAL_EL2", 0b11, 0b100, 0b1110, 0b0101, 0b010>;
 def : RWSysReg<"CNTHPS_CTL_EL2",  0b11, 0b100, 0b1110, 0b0101, 0b001>;
 
 // v8.4a "Virtualization debug state" registers
 //                           Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"SDER32_EL2", 0b11, 0b100, 0b0001, 0b0011, 0b001>;
 } // FeatureSEL2
 
-// v8.4a PMU registers
-//                          Op0   Op1    CRn     CRm     Op2
-let Requires = [{ {AArch64::FeaturePMU} }] in {
-def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
-} // FeaturePMU
-
 // v8.4a RAS registers
 //                              Op0   Op1    CRn     CRm     Op2
 def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
 def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
 def : RWSysReg<"ERXMISC2_EL1",  0b11, 0b000, 0b0101, 0b0101, 0b010>;
 def : RWSysReg<"ERXMISC3_EL1",  0b11, 0b000, 0b0101, 0b0101, 0b011>;
 def : ROSysReg<"ERXPFGF_EL1",   0b11, 0b000, 0b0101, 0b0100, 0b100>;
 

llvm/test/MC/AArch64/armv8.4a-pmu.s

-// RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.4a < %s \
-// RUN: | FileCheck %s --check-prefix=CHECK
-
-// RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-v8.4a < %s 2>&1 \
-// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
-
-//------------------------------------------------------------------------------
-// ARMV8.4-A PMU
-//------------------------------------------------------------------------------
-
-// Read/Write registers:
-
-msr PMMIR_EL1, x0
-mrs x0, PMMIR_EL1
-
-//CHECK: msr     PMMIR_EL1, x0           // encoding: [0xc0,0x9e,0x18,0xd5]
-//CHECK: mrs     x0, PMMIR_EL1           // encoding: [0xc0,0x9e,0x38,0xd5]
-//CHECK-ERROR: error: expected writable system register or pstate
-//CHECK-ERROR: error: expected readable system register

llvm/test/MC/AArch64/basic-a64-instructions.s

// CHECK: tlbi    vaale1, x25             // encoding: [0xf9,0x87,0x08,0xd5]
   msr PMSELR_EL0, x12
   msr PMCCNTR_EL0, x12
   msr PMXEVTYPER_EL0, x12
   msr PMXEVCNTR_EL0, x12
   msr PMUSERENR_EL0, x12
   msr PMINTENSET_EL1, x12
   msr PMINTENCLR_EL1, x12
   msr PMOVSSET_EL0, x12
+  msr PMMIR_EL1, x12
   msr MAIR_EL1, x12
   msr MAIR_EL2, x12
   msr MAIR_EL3, x12
   msr AMAIR_EL1, x12
   msr AMAIR_EL2, x12
   msr AMAIR_EL3, x12
   msr VBAR_EL1, x12
   msr VBAR_EL2, x12

 // CHECK: msr      {{pmselr_el0|PMSELR_EL0}}, x12            // encoding: [0xac,0x9c,0x1b,0xd5]
 // CHECK: msr      {{pmccntr_el0|PMCCNTR_EL0}}, x12           // encoding: [0x0c,0x9d,0x1b,0xd5]
 // CHECK: msr      {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12        // encoding: [0x2c,0x9d,0x1b,0xd5]
 // CHECK: msr      {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12         // encoding: [0x4c,0x9d,0x1b,0xd5]
 // CHECK: msr      {{pmuserenr_el0|PMUSERENR_EL0}}, x12         // encoding: [0x0c,0x9e,0x1b,0xd5]
 // CHECK: msr      {{pmintenset_el1|PMINTENSET_EL1}}, x12        // encoding: [0x2c,0x9e,0x18,0xd5]
 // CHECK: msr      {{pmintenclr_el1|PMINTENCLR_EL1}}, x12        // encoding: [0x4c,0x9e,0x18,0xd5]
 // CHECK: msr      {{pmovsset_el0|PMOVSSET_EL0}}, x12          // encoding: [0x6c,0x9e,0x1b,0xd5]
+// CHECK: msr      {{pmmir_el1|PMMIR_EL1}}, x12        // encoding: [0xcc,0x9e,0x18,0xd5]
 // CHECK: msr      {{mair_el1|MAIR_EL1}}, x12              // encoding: [0x0c,0xa2,0x18,0xd5]
 // CHECK: msr      {{mair_el2|MAIR_EL2}}, x12              // encoding: [0x0c,0xa2,0x1c,0xd5]
 // CHECK: msr      {{mair_el3|MAIR_EL3}}, x12              // encoding: [0x0c,0xa2,0x1e,0xd5]
 // CHECK: msr      {{amair_el1|AMAIR_EL1}}, x12             // encoding: [0x0c,0xa3,0x18,0xd5]
 // CHECK: msr      {{amair_el2|AMAIR_EL2}}, x12             // encoding: [0x0c,0xa3,0x1c,0xd5]
 // CHECK: msr      {{amair_el3|AMAIR_EL3}}, x12             // encoding: [0x0c,0xa3,0x1e,0xd5]
 // CHECK: msr      {{vbar_el1|VBAR_EL1}}, x12              // encoding: [0x0c,0xc0,0x18,0xd5]
 // CHECK: msr      {{vbar_el2|VBAR_EL2}}, x12              // encoding: [0x0c,0xc0,0x1c,0xd5]
// CHECK: msr      {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12       // encoding: [0xcc,0xef,0x1b,0xd5]
   mrs x9, PMCEID1_EL0
   mrs x9, PMCCNTR_EL0
   mrs x9, PMXEVTYPER_EL0
   mrs x9, PMXEVCNTR_EL0
   mrs x9, PMUSERENR_EL0
   mrs x9, PMINTENSET_EL1
   mrs x9, PMINTENCLR_EL1
   mrs x9, PMOVSSET_EL0
+  mrs x9, PMMIR_EL1
   mrs x9, MAIR_EL1
   mrs x9, MAIR_EL2
   mrs x9, MAIR_EL3
   mrs x9, AMAIR_EL1
   mrs x9, AMAIR_EL2
   mrs x9, AMAIR_EL3
   mrs x9, VBAR_EL1
   mrs x9, VBAR_EL2

 // CHECK: mrs      x9, {{pmceid1_el0|PMCEID1_EL0}}            // encoding: [0xe9,0x9c,0x3b,0xd5]
 // CHECK: mrs      x9, {{pmccntr_el0|PMCCNTR_EL0}}            // encoding: [0x09,0x9d,0x3b,0xd5]
 // CHECK: mrs      x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}}         // encoding: [0x29,0x9d,0x3b,0xd5]
 // CHECK: mrs      x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}}          // encoding: [0x49,0x9d,0x3b,0xd5]
 // CHECK: mrs      x9, {{pmuserenr_el0|PMUSERENR_EL0}}          // encoding: [0x09,0x9e,0x3b,0xd5]
 // CHECK: mrs      x9, {{pmintenset_el1|PMINTENSET_EL1}}         // encoding: [0x29,0x9e,0x38,0xd5]
 // CHECK: mrs      x9, {{pmintenclr_el1|PMINTENCLR_EL1}}         // encoding: [0x49,0x9e,0x38,0xd5]
 // CHECK: mrs      x9, {{pmovsset_el0|PMOVSSET_EL0}}           // encoding: [0x69,0x9e,0x3b,0xd5]
+// CHECK: mrs      x9, {{pmmir_el1|PMMIR_EL1}}             // encoding: [0xc9,0x9e,0x38,0xd5]
 // CHECK: mrs      x9, {{mair_el1|MAIR_EL1}}               // encoding: [0x09,0xa2,0x38,0xd5]
 // CHECK: mrs      x9, {{mair_el2|MAIR_EL2}}               // encoding: [0x09,0xa2,0x3c,0xd5]
 // CHECK: mrs      x9, {{mair_el3|MAIR_EL3}}               // encoding: [0x09,0xa2,0x3e,0xd5]
 // CHECK: mrs      x9, {{amair_el1|AMAIR_EL1}}              // encoding: [0x09,0xa3,0x38,0xd5]
 // CHECK: mrs      x9, {{amair_el2|AMAIR_EL2}}              // encoding: [0x09,0xa3,0x3c,0xd5]
 // CHECK: mrs      x9, {{amair_el3|AMAIR_EL3}}              // encoding: [0x09,0xa3,0x3e,0xd5]
 // CHECK: mrs      x9, {{vbar_el1|VBAR_EL1}}               // encoding: [0x09,0xc0,0x38,0xd5]
 // CHECK: mrs      x9, {{vbar_el2|VBAR_EL2}}               // encoding: [0x09,0xc0,0x3c,0xd5]

llvm/test/MC/Disassembler/AArch64/armv8.4a-pmu.txt

-#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.4a --disassemble < %s | FileCheck %s
-#RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=-v8.4a --disassemble < %s | FileCheck %s --check-prefix=CHECK-NOV84
-
-[0xc0,0x9e,0x18,0xd5]
-[0xc0,0x9e,0x38,0xd5]
-
-#CHECK:  msr PMMIR_EL1, x0
-#CHECK:  mrs x0, PMMIR_EL1
-#CHECK-NOV84:  msr S3_0_C9_C14_6, x0
-#CHECK-NOV84:  mrs x0, S3_0_C9_C14_6

llvm/test/MC/Disassembler/AArch64/basic-a64-instructions.txt

 # CHECK: msr      {{pmselr_el0|PMSELR_EL0}}, x12
 # CHECK: msr      {{pmccntr_el0|PMCCNTR_EL0}}, x12
 # CHECK: msr      {{pmxevtyper_el0|PMXEVTYPER_EL0}}, x12
 # CHECK: msr      {{pmxevcntr_el0|PMXEVCNTR_EL0}}, x12
 # CHECK: msr      {{pmuserenr_el0|PMUSERENR_EL0}}, x12
 # CHECK: msr      {{pmintenset_el1|PMINTENSET_EL1}}, x12
 # CHECK: msr      {{pmintenclr_el1|PMINTENCLR_EL1}}, x12
 # CHECK: msr      {{pmovsset_el0|PMOVSSET_EL0}}, x12
+# CHECK: msr      {{pmmir_el1|PMMIR_EL1}}, x12
 # CHECK: msr      {{mair_el1|MAIR_EL1}}, x12
 # CHECK: msr      {{mair_el2|MAIR_EL2}}, x12
 # CHECK: msr      {{mair_el3|MAIR_EL3}}, x12
 # CHECK: msr      {{amair_el1|AMAIR_EL1}}, x12
 # CHECK: msr      {{amair_el2|AMAIR_EL2}}, x12
 # CHECK: msr      {{amair_el3|AMAIR_EL3}}, x12
 # CHECK: msr      {{vbar_el1|VBAR_EL1}}, x12
 # CHECK: msr      {{vbar_el2|VBAR_EL2}}, x12

 # CHECK: mrs      x9, {{pmceid1_el0|PMCEID1_EL0}}
 # CHECK: mrs      x9, {{pmccntr_el0|PMCCNTR_EL0}}
 # CHECK: mrs      x9, {{pmxevtyper_el0|PMXEVTYPER_EL0}}
 # CHECK: mrs      x9, {{pmxevcntr_el0|PMXEVCNTR_EL0}}
 # CHECK: mrs      x9, {{pmuserenr_el0|PMUSERENR_EL0}}
 # CHECK: mrs      x9, {{pmintenset_el1|PMINTENSET_EL1}}
 # CHECK: mrs      x9, {{pmintenclr_el1|PMINTENCLR_EL1}}
 # CHECK: mrs      x9, {{pmovsset_el0|PMOVSSET_EL0}}
+# CHECK: mrs      x9, {{pmmir_el1|PMMIR_EL1}}
 # CHECK: mrs      x9, {{mair_el1|MAIR_EL1}}
 # CHECK: mrs      x9, {{mair_el2|MAIR_EL2}}
 # CHECK: mrs      x9, {{mair_el3|MAIR_EL3}}
 # CHECK: mrs      x9, {{amair_el1|AMAIR_EL1}}
 # CHECK: mrs      x9, {{amair_el2|AMAIR_EL2}}
 # CHECK: mrs      x9, {{amair_el3|AMAIR_EL3}}
 # CHECK: mrs      x9, {{vbar_el1|VBAR_EL1}}
 # CHECK: mrs      x9, {{vbar_el2|VBAR_EL2}}

 0xac 0x9c 0x1b 0xd5
 0xc 0x9d 0x1b 0xd5
 0x2c 0x9d 0x1b 0xd5
 0x4c 0x9d 0x1b 0xd5
 0xc 0x9e 0x1b 0xd5
 0x2c 0x9e 0x18 0xd5
 0x4c 0x9e 0x18 0xd5
 0x6c 0x9e 0x1b 0xd5
+0xcc 0x9e 0x18 0xd5
 0xc 0xa2 0x18 0xd5
 0xc 0xa2 0x1c 0xd5
 0xc 0xa2 0x1e 0xd5
 0xc 0xa3 0x18 0xd5
 0xc 0xa3 0x1c 0xd5
 0xc 0xa3 0x1e 0xd5
 0xc 0xc0 0x18 0xd5
 0xc 0xc0 0x1c 0xd5

 0xe9 0x9c 0x3b 0xd5
 0x9 0x9d 0x3b 0xd5
 0x29 0x9d 0x3b 0xd5
 0x49 0x9d 0x3b 0xd5
 0x9 0x9e 0x3b 0xd5
 0x29 0x9e 0x38 0xd5
 0x49 0x9e 0x38 0xd5
 0x69 0x9e 0x3b 0xd5
+0xc9 0x9e 0x38 0xd5
 0x9 0xa2 0x38 0xd5
 0x9 0xa2 0x3c 0xd5
 0x9 0xa2 0x3e 0xd5
 0x9 0xa3 0x38 0xd5
 0x9 0xa3 0x3c 0xd5
 0x9 0xa3 0x3e 0xd5
 0x9 0xc0 0x38 0xd5
 0x9 0xc0 0x3c 0xd5