[RISCV] Make more optimization for multiplication in the zba extension with SH*ADD.

[jacquesguan]

Summary

This patch make the following optimization.

(mul x, 2 + power_of_2) -> (SH1ADD x, (SLLI x, bits))
(mul x, 4 + power_of_2) -> (SH2ADD x, (SLLI x, bits))
(mul x, 8 + power_of_2) -> (SH3ADD x, (SLLI x, bits))

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

1083

SH2ADD?

1086

SH3ADD?

[jacquesguan]

Fix wrong instruction.

[jacquesguan]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

1083

Thanks, fixed.

1086

Thanks, fixed.

[jacquesguan]

ping.

[benshi001]

This optimization has already been implemented in https://reviews.llvm.org/rG264b8e2a20b3124b80bdf6f17dc29d5869336375

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

 def CSImm12MulBy8 : PatLeaf<(imm), [{
   if (!N->hasOneUse())
     return false;
   int64_t C = N->getSExtValue();
   // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
   return !isInt<13>(C) && isInt<15>(C) && (C & 7) == 0;
 }]>;
 
+def CPow2Plus2 : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  int64_t C = N->getSExtValue();
+  return !isPowerOf2_64(C) && C > 2 && isPowerOf2_64(C - 2);
+}]>;
+
+def CPow2Plus4 : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  int64_t C = N->getSExtValue();
+  return !isPowerOf2_64(C) && C > 4 && isPowerOf2_64(C - 4);
+}]>;
+
+def CPow2Plus8 : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  int64_t C = N->getSExtValue();
+  return !isPowerOf2_64(C) && C > 8 && isPowerOf2_64(C - 8);
+}]>;
+
 def SimmShiftRightBy2XForm : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue() >> 2, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
 def SimmShiftRightBy3XForm : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue() >> 3, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
+def SimmMinus2Lg2XForm : SDNodeXForm<imm, [{
+  uint64_t I = N->getZExtValue();
+  return CurDAG->getTargetConstant(countTrailingZeros(I - 2), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+def SimmMinus4Lg2XForm : SDNodeXForm<imm, [{
+  uint64_t I = N->getZExtValue();
+  return CurDAG->getTargetConstant(countTrailingZeros(I - 4), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+def SimmMinus8Lg2XForm : SDNodeXForm<imm, [{
+  uint64_t I = N->getZExtValue();
+  return CurDAG->getTargetConstant(countTrailingZeros(I - 8), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 // Some of these templates should be moved to RISCVInstrFormats.td once the B
 // extension has been ratified.
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2),
           (SH2ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2),
           (SH3ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
           (SH3ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
           (SH3ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 
+def : Pat<(mul GPR:$rs1, CPow2Plus2:$i),
+          (SH1ADD GPR:$rs1, (SLLI GPR:$rs1,
+                                  (SimmMinus2Lg2XForm CPow2Plus2:$i)))>;
+def : Pat<(mul GPR:$rs1, CPow2Plus4:$i),
+          (SH1ADD GPR:$rs1, (SLLI GPR:$rs1,
+                                  (SimmMinus4Lg2XForm CPow2Plus4:$i)))>;
+def : Pat<(mul GPR:$rs1, CPow2Plus8:$i),
+          (SH1ADD GPR:$rs1, (SLLI GPR:$rs1,
+                                  (SimmMinus8Lg2XForm CPow2Plus8:$i)))>;
+
 def : Pat<(add GPR:$r, CSImm12MulBy4:$i),
           (SH2ADD (ADDI X0, (SimmShiftRightBy2XForm CSImm12MulBy4:$i)),
                   GPR:$r)>;
 def : Pat<(add GPR:$r, CSImm12MulBy8:$i),
           (SH3ADD (ADDI X0, (SimmShiftRightBy3XForm CSImm12MulBy8:$i)),
                   GPR:$r)>;
 
 def : Pat<(mul GPR:$r, C3LeftShift:$i),

llvm/test/CodeGen/RISCV/rv32zba.ll

 ; RV32I-LABEL: mul258:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 258
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32B-LABEL: mul258:
 ; RV32B:       # %bb.0:
-; RV32B-NEXT:    addi a1, zero, 258
-; RV32B-NEXT:    mul a0, a0, a1
+; RV32B-NEXT:    slli a1, a0, 8
+; RV32B-NEXT:    sh1add a0, a0, a1
 ; RV32B-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul258:
 ; RV32ZBA:       # %bb.0:
-; RV32ZBA-NEXT:    addi a1, zero, 258
-; RV32ZBA-NEXT:    mul a0, a0, a1
+; RV32ZBA-NEXT:    slli a1, a0, 8
+; RV32ZBA-NEXT:    sh1add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 258
   ret i32 %c
 }
 
 define i32 @mul260(i32 %a) {
 ; RV32I-LABEL: mul260:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 260
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32B-LABEL: mul260:
 ; RV32B:       # %bb.0:
-; RV32B-NEXT:    addi a1, zero, 260
-; RV32B-NEXT:    mul a0, a0, a1
+; RV32B-NEXT:    slli a1, a0, 8
+; RV32B-NEXT:    sh1add a0, a0, a1
 ; RV32B-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul260:
 ; RV32ZBA:       # %bb.0:
-; RV32ZBA-NEXT:    addi a1, zero, 260
-; RV32ZBA-NEXT:    mul a0, a0, a1
+; RV32ZBA-NEXT:    slli a1, a0, 8
+; RV32ZBA-NEXT:    sh1add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 260
   ret i32 %c
 }
 
 define i32 @mul264(i32 %a) {
 ; RV32I-LABEL: mul264:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 264
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32B-LABEL: mul264:
 ; RV32B:       # %bb.0:
-; RV32B-NEXT:    addi a1, zero, 264
-; RV32B-NEXT:    mul a0, a0, a1
+; RV32B-NEXT:    slli a1, a0, 8
+; RV32B-NEXT:    sh1add a0, a0, a1
 ; RV32B-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul264:
 ; RV32ZBA:       # %bb.0:
-; RV32ZBA-NEXT:    addi a1, zero, 264
-; RV32ZBA-NEXT:    mul a0, a0, a1
+; RV32ZBA-NEXT:    slli a1, a0, 8
+; RV32ZBA-NEXT:    sh1add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 264
   ret i32 %c
 }
 
+define i32 @mul514(i32 %a) {
+; RV32I-LABEL: mul514:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 514
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: mul514:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    slli a1, a0, 9
+; RV32B-NEXT:    sh1add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: mul514:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    slli a1, a0, 9
+; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = mul i32 %a, 514
+  ret i32 %c
+}
+
+define i32 @mul516(i32 %a) {
+; RV32I-LABEL: mul516:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 516
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: mul516:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    slli a1, a0, 9
+; RV32B-NEXT:    sh1add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: mul516:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    slli a1, a0, 9
+; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = mul i32 %a, 516
+  ret i32 %c
+}
+
+define i32 @mul520(i32 %a) {
+; RV32I-LABEL: mul520:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 520
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: mul520:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    slli a1, a0, 9
+; RV32B-NEXT:    sh1add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: mul520:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    slli a1, a0, 9
+; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = mul i32 %a, 520
+  ret i32 %c
+}
+
+define i32 @mul1026(i32 %a) {
+; RV32I-LABEL: mul1026:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 1026
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: mul1026:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    slli a1, a0, 10
+; RV32B-NEXT:    sh1add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: mul1026:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    slli a1, a0, 10
+; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = mul i32 %a, 1026
+  ret i32 %c
+}
+
+define i32 @mul1028(i32 %a) {
+; RV32I-LABEL: mul1028:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 1028
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: mul1028:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    slli a1, a0, 10
+; RV32B-NEXT:    sh1add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: mul1028:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    slli a1, a0, 10
+; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = mul i32 %a, 1028
+  ret i32 %c
+}
+
+define i32 @mul1032(i32 %a) {
+; RV32I-LABEL: mul1032:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    addi a1, zero, 1032
+; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: mul1032:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    slli a1, a0, 10
+; RV32B-NEXT:    sh1add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: mul1032:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    slli a1, a0, 10
+; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = mul i32 %a, 1032
+  ret i32 %c
+}
+
 define i32 @mul11(i32 %a) {
 ; RV32I-LABEL: mul11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 11
 ; RV32I-NEXT:    mul a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32B-LABEL: mul11:

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64I-LABEL: mul258:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 258
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: mul258:
 ; RV64B:       # %bb.0:
-; RV64B-NEXT:    addi a1, zero, 258
-; RV64B-NEXT:    mul a0, a0, a1
+; RV64B-NEXT:    slli a1, a0, 8
+; RV64B-NEXT:    sh1add a0, a0, a1
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: mul258:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    addi a1, zero, 258
-; RV64ZBA-NEXT:    mul a0, a0, a1
+; RV64ZBA-NEXT:    slli a1, a0, 8
+; RV64ZBA-NEXT:    sh1add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
   %c = mul i64 %a, 258
   ret i64 %c
 }
 
 define i64 @mul260(i64 %a) {
 ; RV64I-LABEL: mul260:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 260
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: mul260:
 ; RV64B:       # %bb.0:
-; RV64B-NEXT:    addi a1, zero, 260
-; RV64B-NEXT:    mul a0, a0, a1
+; RV64B-NEXT:    slli a1, a0, 8
+; RV64B-NEXT:    sh1add a0, a0, a1
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: mul260:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    addi a1, zero, 260
-; RV64ZBA-NEXT:    mul a0, a0, a1
+; RV64ZBA-NEXT:    slli a1, a0, 8
+; RV64ZBA-NEXT:    sh1add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
   %c = mul i64 %a, 260
   ret i64 %c
 }
 
 define i64 @mul264(i64 %a) {
 ; RV64I-LABEL: mul264:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, 264
 ; RV64I-NEXT:    mul a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: mul264:
 ; RV64B:       # %bb.0:
-; RV64B-NEXT:    addi a1, zero, 264
-; RV64B-NEXT:    mul a0, a0, a1
+; RV64B-NEXT:    slli a1, a0, 8
+; RV64B-NEXT:    sh1add a0, a0, a1
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: mul264:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    addi a1, zero, 264
-; RV64ZBA-NEXT:    mul a0, a0, a1
+; RV64ZBA-NEXT:    slli a1, a0, 8
+; RV64ZBA-NEXT:    sh1add a0, a0, a1
 ; RV64ZBA-NEXT:    ret
   %c = mul i64 %a, 264
   ret i64 %c
 }
 
+define i64 @mul514(i64 %a) {
+; RV64I-LABEL: mul514:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 514
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: mul514:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    slli a1, a0, 9
+; RV64B-NEXT:    sh1add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul514:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    slli a1, a0, 9
+; RV64ZBA-NEXT:    sh1add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 514
+  ret i64 %c
+}
+
+define i64 @mul516(i64 %a) {
+; RV64I-LABEL: mul516:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 516
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: mul516:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    slli a1, a0, 9
+; RV64B-NEXT:    sh1add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul516:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    slli a1, a0, 9
+; RV64ZBA-NEXT:    sh1add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 516
+  ret i64 %c
+}
+
+define i64 @mul520(i64 %a) {
+; RV64I-LABEL: mul520:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 520
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: mul520:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    slli a1, a0, 9
+; RV64B-NEXT:    sh1add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul520:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    slli a1, a0, 9
+; RV64ZBA-NEXT:    sh1add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 520
+  ret i64 %c
+}
+
+define i64 @mul1026(i64 %a) {
+; RV64I-LABEL: mul1026:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 1026
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: mul1026:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    slli a1, a0, 10
+; RV64B-NEXT:    sh1add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul1026:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    slli a1, a0, 10
+; RV64ZBA-NEXT:    sh1add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 1026
+  ret i64 %c
+}
+
+define i64 @mul1028(i64 %a) {
+; RV64I-LABEL: mul1028:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 1028
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: mul1028:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    slli a1, a0, 10
+; RV64B-NEXT:    sh1add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul1028:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    slli a1, a0, 10
+; RV64ZBA-NEXT:    sh1add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 1028
+  ret i64 %c
+}
+
+define i64 @mul1032(i64 %a) {
+; RV64I-LABEL: mul1032:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    addi a1, zero, 1032
+; RV64I-NEXT:    mul a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: mul1032:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    slli a1, a0, 10
+; RV64B-NEXT:    sh1add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: mul1032:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    slli a1, a0, 10
+; RV64ZBA-NEXT:    sh1add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = mul i64 %a, 1032
+  ret i64 %c
+}
+
 define i64 @imm_zextw() nounwind {
 ; RV64I-LABEL: imm_zextw:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a0, zero, 1
 ; RV64I-NEXT:    slli a0, a0, 32
 ; RV64I-NEXT:    addi a0, a0, -2
 ; RV64I-NEXT:    ret
 ;