[RISCV][test] Add new tests for add optimization in the zba extension

[benshi001]

Summary

These tests will should how (add x, imm) will be optimized to
(shxadd x, imm>>bits) if imm is not simm12 while (imm>>bits) is.

llvm/test/CodeGen/RISCV/rv32zba.ll

 ; RV32ZBA-LABEL: mul4104:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    slli a1, a0, 12
 ; RV32ZBA-NEXT:    sh3add a0, a0, a1
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 4104
   ret i32 %c
 }
+
+define i32 @add4104(i32 %a) {
+; RV32I-LABEL: add4104:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 1
+; RV32I-NEXT:    addi a1, a1, 8
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: add4104:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    lui a1, 1
+; RV32B-NEXT:    addi a1, a1, 8
+; RV32B-NEXT:    add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: add4104:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    lui a1, 1
+; RV32ZBA-NEXT:    addi a1, a1, 8
+; RV32ZBA-NEXT:    add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = add i32 %a, 4104
+  ret i32 %c
+}
+
+define i32 @add8208(i32 %a) {
+; RV32I-LABEL: add8208:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    lui a1, 2
+; RV32I-NEXT:    addi a1, a1, 16
+; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV32B-LABEL: add8208:
+; RV32B:       # %bb.0:
+; RV32B-NEXT:    lui a1, 2
+; RV32B-NEXT:    addi a1, a1, 16
+; RV32B-NEXT:    add a0, a0, a1
+; RV32B-NEXT:    ret
+;
+; RV32ZBA-LABEL: add8208:
+; RV32ZBA:       # %bb.0:
+; RV32ZBA-NEXT:    lui a1, 2
+; RV32ZBA-NEXT:    addi a1, a1, 16
+; RV32ZBA-NEXT:    add a0, a0, a1
+; RV32ZBA-NEXT:    ret
+  %c = add i32 %a, 8208
+  ret i32 %c
+}

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64ZBA-LABEL: mulw576:
 ; RV64ZBA:       # %bb.0:
 ; RV64ZBA-NEXT:    sh3add a0, a0, a0
 ; RV64ZBA-NEXT:    slliw a0, a0, 6
 ; RV64ZBA-NEXT:    ret
   %c = mul i32 %a, 576
   ret i32 %c
 }
+
+define i64 @add4104(i64 %a) {
+; RV64I-LABEL: add4104:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 1
+; RV64I-NEXT:    addiw a1, a1, 8
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: add4104:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    lui a1, 1
+; RV64B-NEXT:    addiw a1, a1, 8
+; RV64B-NEXT:    add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: add4104:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    lui a1, 1
+; RV64ZBA-NEXT:    addiw a1, a1, 8
+; RV64ZBA-NEXT:    add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = add i64 %a, 4104
+  ret i64 %c
+}
+
+define i64 @add8208(i64 %a) {
+; RV64I-LABEL: add8208:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    lui a1, 2
+; RV64I-NEXT:    addiw a1, a1, 16
+; RV64I-NEXT:    add a0, a0, a1
+; RV64I-NEXT:    ret
+;
+; RV64B-LABEL: add8208:
+; RV64B:       # %bb.0:
+; RV64B-NEXT:    lui a1, 2
+; RV64B-NEXT:    addiw a1, a1, 16
+; RV64B-NEXT:    add a0, a0, a1
+; RV64B-NEXT:    ret
+;
+; RV64ZBA-LABEL: add8208:
+; RV64ZBA:       # %bb.0:
+; RV64ZBA-NEXT:    lui a1, 2
+; RV64ZBA-NEXT:    addiw a1, a1, 16
+; RV64ZBA-NEXT:    add a0, a0, a1
+; RV64ZBA-NEXT:    ret
+  %c = add i64 %a, 8208
+  ret i64 %c
+}