[RISCV] Optimize add in the zba extension with SH*ADD

[benshi001]

Summary

Optimize (add x, c) to (SH*ADD (c>>b), x) if c
is not simm12 while (c>>b) is simm12 and c has
b trailing zeros.

[luismarques]

Wouldn't this also work for the sh1add case? If so, any reason for omitting from this patch?

[benshi001]

In D108193#2954069, @luismarques wrote:

Wouldn't this also work for the sh1add case? If so, any reason for omitting from this patch?

We have already optimized (add x, 4094) to (ADDI （ADDI x, 2047), 2047), so SH1ADD is not no long needed.

[luismarques]

In D108193#2954359, @benshi001 wrote:

We have already optimized (add x, 4094) to (ADDI （ADDI x, 2047), 2047), so SH1ADD is not no long needed.

Oh, right. You even mentioned in the comments the "PatLeaf AddiPair".

LGTM.

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

def C5LeftShift : PatLeaf<(imm), [{
   return C > 5 && ((C % 5) == 0) && isPowerOf2_64(C / 5);
 }]>;
 
 def C9LeftShift : PatLeaf<(imm), [{
   uint64_t C = N->getZExtValue();
   return C > 9 && ((C % 9) == 0) && isPowerOf2_64(C / 9);
 }]>;
 
+def CSImm12MulBy4 : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  int64_t C = N->getSExtValue();
+  // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
+  return !isInt<13>(C) && isInt<14>(C) && (C & 3) == 0;
+}]>;
+
+def CSImm12MulBy8 : PatLeaf<(imm), [{
+  if (!N->hasOneUse())
+    return false;
+  int64_t C = N->getSExtValue();
+  // Skip if C is simm12 or can be optimized by the PatLeaf AddiPair.
+  return !isInt<13>(C) && isInt<15>(C) && (C & 7) == 0;
+}]>;
+
+def SimmShiftRightBy2XForm : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getSExtValue() >> 2, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+def SimmShiftRightBy3XForm : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(N->getSExtValue() >> 3, SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction class templates
 //===----------------------------------------------------------------------===//
 
 // Some of these templates should be moved to RISCVInstrFormats.td once the B
 // extension has been ratified.
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 36)), GPR:$rs2),
           (SH2ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 24)), GPR:$rs2),
           (SH3ADD (SH1ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 40)), GPR:$rs2),
           (SH3ADD (SH2ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 def : Pat<(add (mul_oneuse GPR:$rs1, (XLenVT 72)), GPR:$rs2),
           (SH3ADD (SH3ADD GPR:$rs1, GPR:$rs1), GPR:$rs2)>;
 
+def : Pat<(add GPR:$r, CSImm12MulBy4:$i),
+          (SH2ADD (ADDI X0, (SimmShiftRightBy2XForm CSImm12MulBy4:$i)),
+                  GPR:$r)>;
+def : Pat<(add GPR:$r, CSImm12MulBy8:$i),
+          (SH3ADD (ADDI X0, (SimmShiftRightBy3XForm CSImm12MulBy8:$i)),
+                  GPR:$r)>;
+
 def : Pat<(mul GPR:$r, C3LeftShift:$i),
           (SLLI (SH1ADD GPR:$r, GPR:$r),
                 (TrailingZerosXForm C3LeftShift:$i))>;
 def : Pat<(mul GPR:$r, C5LeftShift:$i),
           (SLLI (SH2ADD GPR:$r, GPR:$r),
                 (TrailingZerosXForm C5LeftShift:$i))>;
 def : Pat<(mul GPR:$r, C9LeftShift:$i),
           (SLLI (SH3ADD GPR:$r, GPR:$r),

llvm/test/CodeGen/RISCV/rv32zba.ll

 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 8
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32B-LABEL: add4104:
 ; RV32B:       # %bb.0:
-; RV32B-NEXT:    lui a1, 1
-; RV32B-NEXT:    addi a1, a1, 8
-; RV32B-NEXT:    add a0, a0, a1
+; RV32B-NEXT:    addi a1, zero, 1026
+; RV32B-NEXT:    sh2add a0, a1, a0
 ; RV32B-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: add4104:
 ; RV32ZBA:       # %bb.0:
-; RV32ZBA-NEXT:    lui a1, 1
-; RV32ZBA-NEXT:    addi a1, a1, 8
-; RV32ZBA-NEXT:    add a0, a0, a1
+; RV32ZBA-NEXT:    addi a1, zero, 1026
+; RV32ZBA-NEXT:    sh2add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = add i32 %a, 4104
   ret i32 %c
 }
 
 define i32 @add8208(i32 %a) {
 ; RV32I-LABEL: add8208:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 2
 ; RV32I-NEXT:    addi a1, a1, 16
 ; RV32I-NEXT:    add a0, a0, a1
 ; RV32I-NEXT:    ret
 ;
 ; RV32B-LABEL: add8208:
 ; RV32B:       # %bb.0:
-; RV32B-NEXT:    lui a1, 2
-; RV32B-NEXT:    addi a1, a1, 16
-; RV32B-NEXT:    add a0, a0, a1
+; RV32B-NEXT:    addi a1, zero, 1026
+; RV32B-NEXT:    sh3add a0, a1, a0
 ; RV32B-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: add8208:
 ; RV32ZBA:       # %bb.0:
-; RV32ZBA-NEXT:    lui a1, 2
-; RV32ZBA-NEXT:    addi a1, a1, 16
-; RV32ZBA-NEXT:    add a0, a0, a1
+; RV32ZBA-NEXT:    addi a1, zero, 1026
+; RV32ZBA-NEXT:    sh3add a0, a1, a0
 ; RV32ZBA-NEXT:    ret
   %c = add i32 %a, 8208
   ret i32 %c
 }

llvm/test/CodeGen/RISCV/rv64zba.ll

 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 1
 ; RV64I-NEXT:    addiw a1, a1, 8
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: add4104:
 ; RV64B:       # %bb.0:
-; RV64B-NEXT:    lui a1, 1
-; RV64B-NEXT:    addiw a1, a1, 8
-; RV64B-NEXT:    add a0, a0, a1
+; RV64B-NEXT:    addi a1, zero, 1026
+; RV64B-NEXT:    sh2add a0, a1, a0
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: add4104:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    lui a1, 1
-; RV64ZBA-NEXT:    addiw a1, a1, 8
-; RV64ZBA-NEXT:    add a0, a0, a1
+; RV64ZBA-NEXT:    addi a1, zero, 1026
+; RV64ZBA-NEXT:    sh2add a0, a1, a0
 ; RV64ZBA-NEXT:    ret
   %c = add i64 %a, 4104
   ret i64 %c
 }
 
 define i64 @add8208(i64 %a) {
 ; RV64I-LABEL: add8208:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    lui a1, 2
 ; RV64I-NEXT:    addiw a1, a1, 16
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64B-LABEL: add8208:
 ; RV64B:       # %bb.0:
-; RV64B-NEXT:    lui a1, 2
-; RV64B-NEXT:    addiw a1, a1, 16
-; RV64B-NEXT:    add a0, a0, a1
+; RV64B-NEXT:    addi a1, zero, 1026
+; RV64B-NEXT:    sh3add a0, a1, a0
 ; RV64B-NEXT:    ret
 ;
 ; RV64ZBA-LABEL: add8208:
 ; RV64ZBA:       # %bb.0:
-; RV64ZBA-NEXT:    lui a1, 2
-; RV64ZBA-NEXT:    addiw a1, a1, 16
-; RV64ZBA-NEXT:    add a0, a0, a1
+; RV64ZBA-NEXT:    addi a1, zero, 1026
+; RV64ZBA-NEXT:    sh3add a0, a1, a0
 ; RV64ZBA-NEXT:    ret
   %c = add i64 %a, 8208
   ret i64 %c
 }