[DAGCombiner] Add one use restriction for the pattern (and (add x, c1), (lshr y, c2))

[wwei]

Summary

If the output of (add x, c1) happens to be the input(that is, y) of (lshr y, c2), the fold for (and (add x, c1), (lshr y, c2)) may get a wrong result.

[lebedev.ri]

There was some other patch for this, but i can't find it now.
There was more disscussion there.

[lebedev.ri]

Found, please see https://reviews.llvm.org/D107692#2934462

[wwei]

In D108103#2946161, @lebedev.ri wrote:

Found, please see https://reviews.llvm.org/D107692#2934462

Thanks for pointing out the duplicate fix, I will close this patch

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitANDLike(SDValue N0, SDValue N1, SDNode *N) {
 
   // fold (and x, undef) -> 0
   if (N0.isUndef() || N1.isUndef())
     return DAG.getConstant(0, DL, VT);
 
   if (SDValue V = foldLogicOfSetCCs(true, N0, N1, DL))
     return V;
 
-  if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
-      VT.getSizeInBits() <= 64) {
+  if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() &&
+      N1.getOpcode() == ISD::SRL && VT.getSizeInBits() <= 64) {
     if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
       if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
         // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
         // immediate for an add, but it is legal if its top c2 bits are set,
         // transform the ADD so the immediate doesn't need to be materialized
         // in a register.
         APInt ADDC = ADDI->getAPIntValue();
         APInt SRLC = SRLI->getAPIntValue();

llvm/test/CodeGen/AArch64/combine-and-like.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
 
 define i32 @f(i32 %a0) {
 ; CHECK-LABEL: f:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %1 = lshr i32 %a0, 2147483647
   %2 = add i32 %1, 2147483647
   %3 = and i32 %2, %1
   ret i32 %3
 }
+
+define i32 @f1(i32 %a0) {
+; CHECK-LABEL: f1:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w8, #65535
+; CHECK-NEXT:    add w8, w0, w8
+; CHECK-NEXT:    and w0, w8, w8, lsr #16
+; CHECK-NEXT:    ret
+  %1 = add i32 %a0, 65535
+  %2 = lshr i32 %1, 16
+  %3 = and i32 %1, %2
+  ret i32 %3
+}