[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert

[tmatheson]

Summary

This assert is intended to ensure that the high registers are not
selected when it is passed to one of the thumb UXT instructions. However
it was triggering even for 32 bit where no UXT instruction is emitted.

Fixes PR51313.

[tmatheson]

Remove commented lines

[dmgreen]

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

1650

I think it needs brackets around the ||

llvm/test/CodeGen/ARM/cmpxchg.mir

1

This needs to be rerun, to generate the check lines. It is also probably best if both the llc run lines have FileCheck's to check the output, even if they might be different.

[tmatheson]

Parenthesise condition and update_mir_test_checks

[tmatheson]

llvm/test/CodeGen/ARM/cmpxchg.mir

1

I'm not convinced it needs the extra FileCheck noise, when all we really want to check is that it doesn't crash.

[dmgreen]

LGTM. Thanks

llvm/test/CodeGen/ARM/cmpxchg.mir

1

It makes them easier to maintain, and the extra check lines are useful to make sure it looks OK.

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
   Register DesiredReg = MI.getOperand(3).getReg();
   Register NewReg = MI.getOperand(4).getReg();
 
   if (IsThumb) {
     assert(STI->hasV8MBaselineOps() &&
            "CMP_SWAP not expected to be custom expanded for Thumb1");
     assert((UxtOp == 0 || UxtOp == ARM::tUXTB || UxtOp == ARM::tUXTH) &&
            "ARMv8-M.baseline does not have t2UXTB/t2UXTH");
-    assert(ARM::tGPRRegClass.contains(DesiredReg) &&
+    assert(UxtOp == 0 || ARM::tGPRRegClass.contains(DesiredReg) &&
                              "DesiredReg used for UXT op must be tGPR");
   }
 
   MachineFunction *MF = MBB.getParent();
   auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
   auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
   auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
 
   MF->insert(++MBB.getIterator(), LoadCmpBB);

llvm/test/CodeGen/ARM/cmpxchg.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -o - %s -mtriple=armv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo | FileCheck %s
+# RUN: llc -o - %s -mtriple=thumbv7-unknown-linux-gnu -verify-machineinstrs -run-pass=arm-pseudo
 ---
 name: func
 tracksRegLiveness: true
 body: |
   bb.0:
     liveins: $r0_r1, $r4_r5, $r3, $lr
     ; CHECK-LABEL: name: func
     ; CHECK: successors: %bb.1(0x80000000)
bb.0:
     ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000)
     ; CHECK: liveins: $r4_r5, $r3
     ; CHECK: early-clobber $r2 = STREXD $r4_r5, $r3, 14 /* CC::al */, $noreg
     ; CHECK: CMPri killed $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
     ; CHECK: Bcc %bb.1, 1 /* CC::ne */, killed $cpsr
     ; CHECK: .3:
     dead early-clobber renamable $r0_r1, dead early-clobber renamable $r2 = CMP_SWAP_64 killed renamable $r3, killed renamable $r4_r5, renamable $r4_r5 :: (volatile load store monotonic monotonic (s64))
 ...
+---
+name: func2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $r1, $r2, $r3, $r12, $lr
+    dead early-clobber renamable $r1, dead early-clobber renamable $r2 = CMP_SWAP_32 killed renamable $r3, killed renamable $r12, killed renamable $lr
+...