[AArch64] Prefer ZIP1 over INS to lower concat_vectors.

[efriedma]

Summary

ZIP1 should have comparable performance, and gives the register allocator more flexibility.

[dmgreen]

ZIP1 should have comparable performance

I think on a CPU with 64bit NEON pipelines a zip will count as a 128bit instruction, a INS as a single 64bit instruction.
i.e Note 1 in 4.17 of the Cortex-A55 optimization guide: https://developer.arm.com/documentation/epm128372/2-0/

[efriedma]

Oh, that's unfortunate... I'll just abandon this for now, then; it's not blocking anything for me.

I see a couple ways forward here:

1. Specialize the generated code based on the target CPU.
2. Generate zip1, but add an optimization after regalloc to transform zip1 to ins if the destination is equal to one of the source registers.

llvm/lib/Target/AArch64/AArch64InstrInfo.td

def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
           (f64 (CPYi64 V128:$Rn, VectorIndexD:$idx))>;
 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
           (f32 (CPYi32 V128:$Rn, VectorIndexS:$idx))>;
 def : Pat<(vector_extract (v8f16 V128:$Rn), VectorIndexH:$idx),
           (f16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
 def : Pat<(vector_extract (v8bf16 V128:$Rn), VectorIndexH:$idx),
           (bf16 (CPYi16 V128:$Rn, VectorIndexH:$idx))>;
 
-// All concat_vectors operations are canonicalised to act on i64 vectors for
-// AArch64. In the general case we need an instruction, which had just as well be
-// INS.
+// The only legal concat_vectors operation on AArch64 without SVE is
+// concatenating two 64-bit vectors. In the general case, lower it to ZIP1.
 class ConcatPat<ValueType DstTy, ValueType SrcTy>
   : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
-        (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
-                     (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
+        (ZIP1v2i64 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
+                   (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub))>;
 
 def : ConcatPat<v2i64, v1i64>;
 def : ConcatPat<v2f64, v1f64>;
 def : ConcatPat<v4i32, v2i32>;
 def : ConcatPat<v4f32, v2f32>;
 def : ConcatPat<v8i16, v4i16>;
 def : ConcatPat<v8f16, v4f16>;
 def : ConcatPat<v8bf16, v4bf16>;

llvm/test/CodeGen/AArch64/GlobalISel/select-concat-vectors.mir

 body:             |
   bb.0:
   liveins: $d0, $d1
     ; CHECK-LABEL: name: legal_v4s32_v2s32
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
     ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
-    ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
+    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
+    ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
     ; CHECK: $q0 = COPY [[INSvi64lane]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<2 x s32>) = COPY $d0
     %1:fpr(<2 x s32>) = COPY $d1
     %2:fpr(<4 x s32>) = G_CONCAT_VECTORS %0(<2 x s32>), %1(<2 x s32>)
     $q0 = COPY %2(<4 x s32>)
     RET_ReallyLR implicit $q0
 

 body:             |
   bb.0:
   liveins: $d0, $d1
     ; CHECK-LABEL: name: legal_v8s16_v4s16
     ; CHECK: liveins: $d0, $d1
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
     ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
+    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
     ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.dsub
-    ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
+    ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
+    ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
     ; CHECK: $q0 = COPY [[INSvi64lane]]
     ; CHECK: RET_ReallyLR implicit $q0
     %0:fpr(<4 x s16>) = COPY $d0
     %1:fpr(<4 x s16>) = COPY $d1
     %2:fpr(<8 x s16>) = G_CONCAT_VECTORS %0(<4 x s16>), %1(<4 x s16>)
     $q0 = COPY %2(<8 x s16>)
     RET_ReallyLR implicit $q0
 
 ...

llvm/test/CodeGen/AArch64/arm64-neon-copy.ll

entry:
   %f = insertelement <2 x i32> undef, i32 %e, i32 0
   %h = shufflevector <2 x i32> %d, <2 x i32> %f, <2 x i32> <i32 0, i32 2>
   ret <2 x i32> %h
 }
 
 define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
   ret <16 x i8> %vecinit30
 }
 
 define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecext = extractelement <8 x i8> %x, i32 0
   %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
   %vecext1 = extractelement <8 x i8> %x, i32 1
   %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
   %vecext3 = extractelement <8 x i8> %x, i32 2
   %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
entry:
   %vecinit30 = shufflevector <16 x i8> %vecinit14, <16 x i8> %y, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23>
   ret <16 x i8> %vecinit30
 }
 
 define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecext = extractelement <16 x i8> %x, i32 0
   %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
   %vecext1 = extractelement <16 x i8> %x, i32 1
   %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
   %vecext3 = extractelement <16 x i8> %x, i32 2
   %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
entry:
   ret <16 x i8> %vecinit30
 }
 
 define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 {
 ; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecext = extractelement <8 x i8> %x, i32 0
   %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0
   %vecext1 = extractelement <8 x i8> %x, i32 1
   %vecinit2 = insertelement <16 x i8> %vecinit, i8 %vecext1, i32 1
   %vecext3 = extractelement <8 x i8> %x, i32 2
   %vecinit4 = insertelement <16 x i8> %vecinit2, i8 %vecext3, i32 2
entry:
   %vecext29 = extractelement <8 x i8> %y, i32 7
   %vecinit30 = insertelement <16 x i8> %vecinit28, i8 %vecext29, i32 15
   ret <16 x i8> %vecinit30
 }
 
 define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
   ret <8 x i16> %vecinit14
 }
 
 define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecext = extractelement <4 x i16> %x, i32 0
   %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
   %vecext1 = extractelement <4 x i16> %x, i32 1
   %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
   %vecext3 = extractelement <4 x i16> %x, i32 2
   %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
   %vecext5 = extractelement <4 x i16> %x, i32 3
   %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
   %vecinit14 = shufflevector <8 x i16> %vecinit6, <8 x i16> %y, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
   ret <8 x i16> %vecinit14
 }
 
 define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecext = extractelement <8 x i16> %x, i32 0
   %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
   %vecext1 = extractelement <8 x i16> %x, i32 1
   %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
   %vecext3 = extractelement <8 x i16> %x, i32 2
   %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
entry:
   ret <8 x i16> %vecinit14
 }
 
 define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 {
 ; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecext = extractelement <4 x i16> %x, i32 0
   %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0
   %vecext1 = extractelement <4 x i16> %x, i32 1
   %vecinit2 = insertelement <8 x i16> %vecinit, i16 %vecext1, i32 1
   %vecext3 = extractelement <4 x i16> %x, i32 2
   %vecinit4 = insertelement <8 x i16> %vecinit2, i16 %vecext3, i32 2
   %vecext5 = extractelement <4 x i16> %x, i32 3
   %vecinit6 = insertelement <8 x i16> %vecinit4, i16 %vecext5, i32 3
   %vecext7 = extractelement <4 x i16> %y, i32 0
   %vecinit8 = insertelement <8 x i16> %vecinit6, i16 %vecext7, i32 4
   %vecext9 = extractelement <4 x i16> %y, i32 1
   %vecinit10 = insertelement <8 x i16> %vecinit8, i16 %vecext9, i32 5
   %vecext11 = extractelement <4 x i16> %y, i32 2
   %vecinit12 = insertelement <8 x i16> %vecinit10, i16 %vecext11, i32 6
   %vecext13 = extractelement <4 x i16> %y, i32 3
   %vecinit14 = insertelement <8 x i16> %vecinit12, i16 %vecext13, i32 7
   ret <8 x i16> %vecinit14
 }
 
 define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecext = extractelement <2 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
   %vecext1 = extractelement <2 x i32> %x, i32 1
   %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
   %vecinit6 = shufflevector <4 x i32> %vecinit2, <4 x i32> %y, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecext = extractelement <4 x i32> %x, i32 0
   %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0
   %vecext1 = extractelement <4 x i32> %x, i32 1
   %vecinit2 = insertelement <4 x i32> %vecinit, i32 %vecext1, i32 1
   %vecext3 = extractelement <2 x i32> %y, i32 0
   %vecinit4 = insertelement <4 x i32> %vecinit2, i32 %vecext3, i32 2
   %vecext5 = extractelement <2 x i32> %y, i32 1
   %vecinit6 = insertelement <4 x i32> %vecinit4, i32 %vecext5, i32 3
   ret <4 x i32> %vecinit6
 }
 
 define <4 x i32> @test_concat_v4i32_v2i32_v2i32(<2 x i32> %x, <2 x i32> %y) #0 {
 ; CHECK-LABEL: test_concat_v4i32_v2i32_v2i32:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecinit6 = shufflevector <2 x i32> %x, <2 x i32> %y, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %vecinit6
 }
 
 define <2 x i64> @test_concat_v2i64_v2i64_v2i64(<2 x i64> %x, <2 x i64> %y) #0 {
 ; CHECK-LABEL: test_concat_v2i64_v2i64_v2i64:
entry:
   ret <2 x i64> %vecinit2
 }
 
 define <2 x i64> @test_concat_v2i64_v1i64_v1i64(<1 x i64> %x, <1 x i64> %y) #0 {
 ; CHECK-LABEL: test_concat_v2i64_v1i64_v1i64:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %vecext = extractelement <1 x i64> %x, i32 0
   %vecinit = insertelement <2 x i64> undef, i64 %vecext, i32 0
   %vecext1 = extractelement <1 x i64> %y, i32 0
   %vecinit2 = insertelement <2 x i64> %vecinit, i64 %vecext1, i32 1
   ret <2 x i64> %vecinit2
 }

llvm/test/CodeGen/AArch64/arm64-vcombine.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
 
 ; LowerCONCAT_VECTORS() was reversing the order of two parts.
 ; rdar://11558157
 ; rdar://11559553
 define <16 x i8> @test(<16 x i8> %q0, <16 x i8> %q1, i8* nocapture %dest) nounwind {
-entry:
 ; CHECK-LABEL: test:
-; CHECK: mov.d v0[1], v1[0]
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    zip1.2d v0, v0, v1
+; CHECK-NEXT:    ret
+entry:
   %0 = bitcast <16 x i8> %q0 to <2 x i64>
   %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> zeroinitializer
   %1 = bitcast <16 x i8> %q1 to <2 x i64>
   %shuffle.i4 = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer
   %shuffle.i3 = shufflevector <1 x i64> %shuffle.i, <1 x i64> %shuffle.i4, <2 x i32> <i32 0, i32 1>
   %2 = bitcast <2 x i64> %shuffle.i3 to <16 x i8>
   ret <16 x i8> %2
 }

llvm/test/CodeGen/AArch64/bf16-vector-shuffle.ll

 }
 
 ; bfloat16x8_t test_vcombine_bf16(bfloat16x4_t low, bfloat16x4_t high) { return vcombine_bf16(low, high); }
 define <8 x bfloat> @test_vcombine_bf16(<4 x bfloat> %low, <4 x bfloat> %high) nounwind {
 ; CHECK-LABEL: test_vcombine_bf16:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %shuffle.i = shufflevector <4 x bfloat> %low, <4 x bfloat> %high, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x bfloat> %shuffle.i
 }
 
 ; bfloat16x4_t test_vget_high_bf16(bfloat16x8_t a) { return vget_high_bf16(a); }
 define <4 x bfloat> @test_vget_high_bf16(<8 x bfloat> %a) nounwind {

llvm/test/CodeGen/AArch64/concat-vector.ll

; CHECK-NEXT:    ret
    ret <8 x i8> %v8i8
 }
 
 define <16 x i8> @concat3(<8 x i8> %A, <8 x i8> %B) {
 ; CHECK-LABEL: concat3:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
    %v16i8 = shufflevector <8 x i8> %A, <8 x i8> %B, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
    ret <16 x i8> %v16i8
 }
 
 define <4 x i16> @concat4(<2 x i16> %A, <2 x i16> %B) {
 ; CHECK-LABEL: concat4:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    uzp1 v0.4h, v0.4h, v1.4h
 ; CHECK-NEXT:    ret
    %v4i16 = shufflevector <2 x i16> %A, <2 x i16> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    ret <4 x i16> %v4i16
 }
 
 define <8 x i16> @concat5(<4 x i16> %A, <4 x i16> %B) {
 ; CHECK-LABEL: concat5:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
    %v8i16 = shufflevector <4 x i16> %A, <4 x i16> %B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    ret <8 x i16> %v8i16
 }
 
 define <16 x i16> @concat6(<8 x i16>* %A, <8 x i16>* %B) {
 ; CHECK-LABEL: concat6:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ldr q0, [x0]
 ; CHECK-NEXT:    ldr q1, [x1]
 ; CHECK-NEXT:    ret
    %tmp1 = load <8 x i16>, <8 x i16>* %A
    %tmp2 = load <8 x i16>, <8 x i16>* %B
    %v16i16 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
    ret <16 x i16> %v16i16
 }
 
 define <4 x i32> @concat7(<2 x i32> %A, <2 x i32> %B) {
 ; CHECK-LABEL: concat7:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
    %v4i32 = shufflevector <2 x i32> %A, <2 x i32> %B, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
    ret <4 x i32> %v4i32
 }
 
 define <8 x i32> @concat8(<4 x i32>* %A, <4 x i32>* %B) {
 ; CHECK-LABEL: concat8:
 ; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
    ret <4 x half> %v4half
 }
 
 define <8 x half> @concat10(<4 x half> %A, <4 x half> %B) {
 ; CHECK-LABEL: concat10:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
    %v8half= shufflevector <4 x half> %A, <4 x half> %B, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
    ret <8 x half> %v8half
 }
 
 define <16 x half> @concat11(<8 x half> %A, <8 x half> %B) {
 ; CHECK-LABEL: concat11:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ret
    %v16half= shufflevector <8 x half> %A, <8 x half> %B, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
    ret <16 x half> %v16half
 }

llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64 < %s | FileCheck %s
 
 ; This test is reduced fom https://github.com/android/ndk/issues/1207 for an
 ; issue with the following DAGCobmine operation:
 ;   truncate(build_vector(x,y)) -> build_vector(truncate(x),truncate(y))
 ; The combine should avoid creating illegal types if types have already been
 ; legalized.
 
 define void @no_combine(i32 %p) local_unnamed_addr {
 ; CHECK-LABEL: no_combine:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    dup v0.4s, w0
 ; CHECK-NEXT:    movi v1.4h, #4
 ; CHECK-NEXT:    xtn v0.4h, v0.4s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    xtn v1.8b, v0.8h
 ; CHECK-NEXT:    xtn2 v1.16b, v0.8h
 ; CHECK-NEXT:    str q1, [x8]
 ; CHECK-NEXT:    ret
 
 ; The two shufflevector operations are needed to force the DAGCombine to happen
 ; after type legalization and before operation legalization.  Removing either
 ; makes the combine to happen before type legalization and the issue no longer

llvm/test/CodeGen/AArch64/fp16-v16-instructions.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-none-eabi | FileCheck %s
 
 
 define <16 x half> @sitofp_i32(<16 x i32> %a) #0 {
 ; CHECK-LABEL: sitofp_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    scvtf v1.4s, v1.4s
 ; CHECK-NEXT:    scvtf v0.4s, v0.4s
 ; CHECK-NEXT:    scvtf v3.4s, v3.4s
 ; CHECK-NEXT:    scvtf v2.4s, v2.4s
-; CHECK-NEXT:    fcvtn v4.4h, v1.4s
+; CHECK-NEXT:    fcvtn v1.4h, v1.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
 ; CHECK-NEXT:    fcvtn v3.4h, v3.4s
-; CHECK-NEXT:    fcvtn v1.4h, v2.4s
-; CHECK-NEXT:    mov v0.d[1], v4.d[0]
-; CHECK-NEXT:    mov v1.d[1], v3.d[0]
+; CHECK-NEXT:    fcvtn v2.4h, v2.4s
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    zip1 v1.2d, v2.2d, v3.2d
 ; CHECK-NEXT:    ret
 
   %1 = sitofp <16 x i32> %a to <16 x half>
   ret <16 x half> %1
 }
 
 
 define <16 x half> @sitofp_i64(<16 x i64> %a) #0 {

 ; CHECK-NEXT:    fcvtn v2.2s, v2.2d
 ; CHECK-NEXT:    fcvtn v0.2s, v0.2d
 ; CHECK-NEXT:    fcvtn v6.2s, v6.2d
 ; CHECK-NEXT:    fcvtn v4.2s, v4.2d
 ; CHECK-NEXT:    fcvtn2 v2.4s, v3.2d
 ; CHECK-NEXT:    fcvtn2 v0.4s, v1.2d
 ; CHECK-NEXT:    fcvtn2 v6.4s, v7.2d
 ; CHECK-NEXT:    fcvtn2 v4.4s, v5.2d
-; CHECK-NEXT:    fcvtn v2.4h, v2.4s
+; CHECK-NEXT:    fcvtn v1.4h, v2.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-NEXT:    fcvtn v3.4h, v6.4s
-; CHECK-NEXT:    fcvtn v1.4h, v4.4s
-; CHECK-NEXT:    mov v0.d[1], v2.d[0]
-; CHECK-NEXT:    mov v1.d[1], v3.d[0]
+; CHECK-NEXT:    fcvtn v2.4h, v6.4s
+; CHECK-NEXT:    fcvtn v3.4h, v4.4s
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    zip1 v1.2d, v3.2d, v2.2d
 ; CHECK-NEXT:    ret
 
 
 
 
   %1 = sitofp <16 x i64> %a to <16 x half>
   ret <16 x half> %1
 }
 
 
 define <16 x half> @uitofp_i32(<16 x i32> %a) #0 {
 ; CHECK-LABEL: uitofp_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ucvtf v1.4s, v1.4s
 ; CHECK-NEXT:    ucvtf v0.4s, v0.4s
 ; CHECK-NEXT:    ucvtf v3.4s, v3.4s
 ; CHECK-NEXT:    ucvtf v2.4s, v2.4s
-; CHECK-NEXT:    fcvtn v4.4h, v1.4s
+; CHECK-NEXT:    fcvtn v1.4h, v1.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
 ; CHECK-NEXT:    fcvtn v3.4h, v3.4s
-; CHECK-NEXT:    fcvtn v1.4h, v2.4s
-; CHECK-NEXT:    mov v0.d[1], v4.d[0]
-; CHECK-NEXT:    mov v1.d[1], v3.d[0]
+; CHECK-NEXT:    fcvtn v2.4h, v2.4s
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    zip1 v1.2d, v2.2d, v3.2d
 ; CHECK-NEXT:    ret
 
   %1 = uitofp <16 x i32> %a to <16 x half>
   ret <16 x half> %1
 }
 
 
 define <16 x half> @uitofp_i64(<16 x i64> %a) #0 {

 ; CHECK-NEXT:    fcvtn v2.2s, v2.2d
 ; CHECK-NEXT:    fcvtn v0.2s, v0.2d
 ; CHECK-NEXT:    fcvtn v6.2s, v6.2d
 ; CHECK-NEXT:    fcvtn v4.2s, v4.2d
 ; CHECK-NEXT:    fcvtn2 v2.4s, v3.2d
 ; CHECK-NEXT:    fcvtn2 v0.4s, v1.2d
 ; CHECK-NEXT:    fcvtn2 v6.4s, v7.2d
 ; CHECK-NEXT:    fcvtn2 v4.4s, v5.2d
-; CHECK-NEXT:    fcvtn v2.4h, v2.4s
+; CHECK-NEXT:    fcvtn v1.4h, v2.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-NEXT:    fcvtn v3.4h, v6.4s
-; CHECK-NEXT:    fcvtn v1.4h, v4.4s
-; CHECK-NEXT:    mov v0.d[1], v2.d[0]
-; CHECK-NEXT:    mov v1.d[1], v3.d[0]
+; CHECK-NEXT:    fcvtn v2.4h, v6.4s
+; CHECK-NEXT:    fcvtn v3.4h, v4.4s
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    zip1 v1.2d, v3.2d, v2.2d
 ; CHECK-NEXT:    ret
 
 
 
 
   %1 = uitofp <16 x i64> %a to <16 x half>
   ret <16 x half> %1
 }
 
 attributes #0 = { nounwind }

llvm/test/CodeGen/AArch64/fp16-v8-instructions.ll

entry:
   ret void
 }
 
 define <8 x half> @s_to_h(<8 x float> %a) {
 ; CHECK-LABEL: s_to_h:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcvtn v1.4h, v1.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
   %1 = fptrunc <8 x float> %a to <8 x half>
   ret <8 x half> %1
 }
 
 define <8 x half> @d_to_h(<8 x double> %a) {
 ; CHECK-LABEL: d_to_h:
 ; CHECK:       // %bb.0:

 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    sshll v0.8h, v0.8b, #0
 ; CHECK-NEXT:    sshll2 v1.4s, v0.8h, #0
 ; CHECK-NEXT:    sshll v0.4s, v0.4h, #0
 ; CHECK-NEXT:    scvtf v1.4s, v1.4s
 ; CHECK-NEXT:    scvtf v0.4s, v0.4s
 ; CHECK-NEXT:    fcvtn v1.4h, v1.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
   %1 = sitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @sitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-CVT-LABEL: sitofp_i16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    sshll2 v1.4s, v0.8h, #0
 ; CHECK-CVT-NEXT:    sshll v0.4s, v0.4h, #0
 ; CHECK-CVT-NEXT:    scvtf v1.4s, v1.4s
 ; CHECK-CVT-NEXT:    scvtf v0.4s, v0.4s
 ; CHECK-CVT-NEXT:    fcvtn v1.4h, v1.4s
 ; CHECK-CVT-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-CVT-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-CVT-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: sitofp_i16:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    scvtf v0.8h, v0.8h
 ; CHECK-FP16-NEXT:    ret
   %1 = sitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @sitofp_i32(<8 x i32> %a) #0 {
 ; CHECK-LABEL: sitofp_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    scvtf v1.4s, v1.4s
 ; CHECK-NEXT:    scvtf v0.4s, v0.4s
 ; CHECK-NEXT:    fcvtn v1.4h, v1.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
   %1 = sitofp <8 x i32> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @sitofp_i64(<8 x i64> %a) #0 {
 ; CHECK-LABEL: sitofp_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    scvtf v2.2d, v2.2d
 ; CHECK-NEXT:    scvtf v0.2d, v0.2d
 ; CHECK-NEXT:    scvtf v3.2d, v3.2d
 ; CHECK-NEXT:    scvtf v1.2d, v1.2d
 ; CHECK-NEXT:    fcvtn v2.2s, v2.2d
 ; CHECK-NEXT:    fcvtn v0.2s, v0.2d
 ; CHECK-NEXT:    fcvtn2 v2.4s, v3.2d
 ; CHECK-NEXT:    fcvtn2 v0.4s, v1.2d
 ; CHECK-NEXT:    fcvtn v1.4h, v2.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
   %1 = sitofp <8 x i64> %a to <8 x half>
   ret <8 x half> %1
 }
 
 define <8 x half> @uitofp_i8(<8 x i8> %a) #0 {
 ; CHECK-LABEL: uitofp_i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ushll v0.8h, v0.8b, #0
 ; CHECK-NEXT:    ushll2 v1.4s, v0.8h, #0
 ; CHECK-NEXT:    ushll v0.4s, v0.4h, #0
 ; CHECK-NEXT:    ucvtf v1.4s, v1.4s
 ; CHECK-NEXT:    ucvtf v0.4s, v0.4s
 ; CHECK-NEXT:    fcvtn v1.4h, v1.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
   %1 = uitofp <8 x i8> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @uitofp_i16(<8 x i16> %a) #0 {
 ; CHECK-CVT-LABEL: uitofp_i16:
 ; CHECK-CVT:       // %bb.0:
 ; CHECK-CVT-NEXT:    ushll2 v1.4s, v0.8h, #0
 ; CHECK-CVT-NEXT:    ushll v0.4s, v0.4h, #0
 ; CHECK-CVT-NEXT:    ucvtf v1.4s, v1.4s
 ; CHECK-CVT-NEXT:    ucvtf v0.4s, v0.4s
 ; CHECK-CVT-NEXT:    fcvtn v1.4h, v1.4s
 ; CHECK-CVT-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-CVT-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-CVT-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-CVT-NEXT:    ret
 ;
 ; CHECK-FP16-LABEL: uitofp_i16:
 ; CHECK-FP16:       // %bb.0:
 ; CHECK-FP16-NEXT:    ucvtf v0.8h, v0.8h
 ; CHECK-FP16-NEXT:    ret
   %1 = uitofp <8 x i16> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @uitofp_i32(<8 x i32> %a) #0 {
 ; CHECK-LABEL: uitofp_i32:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ucvtf v1.4s, v1.4s
 ; CHECK-NEXT:    ucvtf v0.4s, v0.4s
 ; CHECK-NEXT:    fcvtn v1.4h, v1.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
   %1 = uitofp <8 x i32> %a to <8 x half>
   ret <8 x half> %1
 }
 
 
 define <8 x half> @uitofp_i64(<8 x i64> %a) #0 {
 ; CHECK-LABEL: uitofp_i64:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ucvtf v2.2d, v2.2d
 ; CHECK-NEXT:    ucvtf v0.2d, v0.2d
 ; CHECK-NEXT:    ucvtf v3.2d, v3.2d
 ; CHECK-NEXT:    ucvtf v1.2d, v1.2d
 ; CHECK-NEXT:    fcvtn v2.2s, v2.2d
 ; CHECK-NEXT:    fcvtn v0.2s, v0.2d
 ; CHECK-NEXT:    fcvtn2 v2.4s, v3.2d
 ; CHECK-NEXT:    fcvtn2 v0.4s, v1.2d
 ; CHECK-NEXT:    fcvtn v1.4h, v2.4s
 ; CHECK-NEXT:    fcvtn v0.4h, v0.4s
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
   %1 = uitofp <8 x i64> %a to <8 x half>
   ret <8 x half> %1
 }
 
 define void @test_insert_at_zero(half %a, <8 x half>* %b) #0 {
 ; CHECK-LABEL: test_insert_at_zero:
 ; CHECK:       // %bb.0:

llvm/test/CodeGen/AArch64/fp16-vector-shuffle.ll

 }
 
 ; float16x8_t vcombine(float16x4_t a, float16x4_t b) { return vcombine_f16(a, b); }
 define <8 x half> @vcombine(<4 x half> %a, <4 x half> %b) #0 {
 ; CHECK-LABEL: vcombine:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    ret
 entry:
   %shuffle.i = shufflevector <4 x half> %a, <4 x half> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x half> %shuffle.i
 }
 
 ; float16x4_t get_high(float16x8_t a) { return vget_high_f16(a); }
 define <4 x half> @get_high(<8 x half> %a) #0 {

llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll

 
 define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: vselect_equivalent_shuffle_v8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    adrp x8, .LCPI89_0
 ; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI89_0]
 ; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
 ; CHECK-NEXT:    // kill: def $d1 killed $d1 def $q1
-; CHECK-NEXT:    mov v0.d[1], v1.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    tbl v0.8b, { v0.16b }, v2.8b
 ; CHECK-NEXT:    ret
   %c = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i8> %c
 }
 
 define <8 x i16> @vselect_equivalent_shuffle_v8i16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: vselect_equivalent_shuffle_v8i16:

llvm/test/CodeGen/AArch64/shuffle-mask-legal.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s
 
 ; A shuffle mask with all undef elements is always legal.
 
 define <4 x i32> @PR41535(<2 x i32> %p1, <2 x i32> %p2) {
 ; CHECK-LABEL: PR41535:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ext v0.8b, v0.8b, v1.8b, #4
-; CHECK-NEXT:    mov v0.d[1], v0.d[0]
+; CHECK-NEXT:    zip1 v0.2d, v0.2d, v0.2d
 ; CHECK-NEXT:    ret
   %cat1 = shufflevector <2 x i32> %p1, <2 x i32> undef, <4 x i32> <i32 undef, i32 1, i32 undef, i32 undef>
   %cat2 = shufflevector <2 x i32> %p2, <2 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
   %r = shufflevector <4 x i32> %cat1, <4 x i32> %cat2, <4 x i32> <i32 undef, i32 undef, i32 1, i32 4>
   ret <4 x i32> %r
 }

llvm/test/CodeGen/AArch64/speculation-hardening-loads.ll

entry:
   store <4 x i32> %shuffle, <4 x i32>* %dst, align 4
   ret void
 ; CHECK-LABEL: f_implicitdef_vector_load
 ; CHECK:       cmp     sp, #0
 ; CHECK-NEXT:  csetm   x16, ne
 ; CHECK-NEXT:  and     x1, x1, x16
 ; CHECK-NEXT:  csdb
 ; CHECK-NEXT:  ldr     d0, [x1]
-; CHECK-NEXT:  mov     v0.d[1], v0.d[0]
+; CHECK-NEXT:  zip1    v0.2d, v0.2d, v0.2d
 ; CHECK-NEXT:  str     q0, [x0]
 ; CHECK-NEXT:  mov     [[TMPREG:x[0-9]+]], sp
 ; CHECK-NEXT:  and     [[TMPREG]], [[TMPREG]], x16
 ; CHECK-NEXT:  mov     sp, [[TMPREG]]
 ; CHECK-NEXT:  ret
 }
 
 define <2 x double> @f_usedefvectorload(double* %a, double* %b) speculative_load_hardening {

llvm/test/CodeGen/AArch64/sve-fixed-length-concat.ll

 ; CHECK-NEXT: ret
   %res = shufflevector <4 x i8> %op1, <4 x i8> %op2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i8> %res
 }
 
 ; Don't use SVE for 128-bit vectors.
 define <16 x i8> @concat_v16i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
 ; CHECK-LABEL: concat_v16i8:
-; CHECK: mov v0.d[1], v1.d[0]
+; CHECK: zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT: ret
   %res = shufflevector <8 x i8> %op1, <8 x i8> %op2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7,
                                                                  i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
   ret <16 x i8> %res
 }
 
 define void @concat_v32i8(<16 x i8>* %a, <16 x i8>* %b, <32 x i8>* %c) #0 {
 ; CHECK-LABEL: concat_v32i8:

 ; CHECK-NEXT: ret
   %res = shufflevector <2 x i16> %op1, <2 x i16> %op2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i16> %res
 }
 
 ; Don't use SVE for 128-bit vectors.
 define <8 x i16> @concat_v8i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
 ; CHECK-LABEL: concat_v8i16:
-; CHECK: mov v0.d[1], v1.d[0]
+; CHECK: zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT: ret
   %res = shufflevector <4 x i16> %op1, <4 x i16> %op2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %res
 }
 
 define void @concat_v16i16(<8 x i16>* %a, <8 x i16>* %b, <16 x i16>* %c) #0 {
 ; CHECK-LABEL: concat_v16i16:
 ; CHECK: ldr q[[OP1:[0-9]+]], [x0]

 ; CHECK-NEXT: ret
   %res = shufflevector <1 x i32> %op1, <1 x i32> %op2, <2 x i32> <i32 0, i32 1>
   ret <2 x i32> %res
 }
 
 ; Don't use SVE for 128-bit vectors.
 define <4 x i32> @concat_v4i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
 ; CHECK-LABEL: concat_v4i32:
-; CHECK: mov v0.d[1], v1.d[0]
+; CHECK: zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT: ret
   %res = shufflevector <2 x i32> %op1, <2 x i32> %op2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x i32> %res
 }
 
 define void @concat_v8i32(<4 x i32>* %a, <4 x i32>* %b, <8 x i32>* %c) #0 {
 ; CHECK-LABEL: concat_v8i32:
 ; CHECK: ldr q[[OP1:[0-9]+]], [x0]

 
 ;
 ; i64
 ;
 
 ; Don't use SVE for 128-bit vectors.
 define <2 x i64> @concat_v2i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
 ; CHECK-LABEL: concat_v2i64:
-; CHECK: mov v0.d[1], v1.d[0]
+; CHECK: zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT: ret
   %res = shufflevector <1 x i64> %op1, <1 x i64> %op2, <2 x i32> <i32 0, i32 1>
   ret <2 x i64> %res
 }
 
 define void @concat_v4i64(<2 x i64>* %a, <2 x i64>* %b, <4 x i64>* %c) #0 {
 ; CHECK-LABEL: concat_v4i64:
 ; CHECK: ldr q[[OP1:[0-9]+]], [x0]

 ; CHECK-NEXT: ret
   %res = shufflevector <2 x half> %op1, <2 x half> %op2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x half> %res
 }
 
 ; Don't use SVE for 128-bit vectors.
 define <8 x half> @concat_v8f16(<4 x half> %op1, <4 x half> %op2) #0 {
 ; CHECK-LABEL: concat_v8f16:
-; CHECK: mov v0.d[1], v1.d[0]
+; CHECK: zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT: ret
   %res = shufflevector <4 x half> %op1, <4 x half> %op2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
   ret <8 x half> %res
 }
 
 define void @concat_v16f16(<8 x half>* %a, <8 x half>* %b, <16 x half>* %c) #0 {
 ; CHECK-LABEL: concat_v16f16:
 ; CHECK: ldr q[[OP1:[0-9]+]], [x0]

 ; CHECK-NEXT: ret
   %res = shufflevector <1 x float> %op1, <1 x float> %op2, <2 x i32> <i32 0, i32 1>
   ret <2 x float> %res
 }
 
 ; Don't use SVE for 128-bit vectors.
 define <4 x float> @concat_v4f32(<2 x float> %op1, <2 x float> %op2) #0 {
 ; CHECK-LABEL: concat_v4f32:
-; CHECK: mov v0.d[1], v1.d[0]
+; CHECK: zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT: ret
   %res = shufflevector <2 x float> %op1, <2 x float> %op2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
   ret <4 x float> %res
 }
 
 define void @concat_v8f32(<4 x float>* %a, <4 x float>* %b, <8 x float>* %c) #0 {
 ; CHECK-LABEL: concat_v8f32:
 ; CHECK: ldr q[[OP1:[0-9]+]], [x0]

 
 ;
 ; f64
 ;
 
 ; Don't use SVE for 128-bit vectors.
 define <2 x double> @concat_v2f64(<1 x double> %op1, <1 x double> %op2) #0 {
 ; CHECK-LABEL: concat_v2f64:
-; CHECK: mov v0.d[1], v1.d[0]
+; CHECK: zip1 v0.2d, v0.2d, v1.2d
 ; CHECK-NEXT: ret
   %res = shufflevector <1 x double> %op1, <1 x double> %op2, <2 x i32> <i32 0, i32 1>
   ret <2 x double> %res
 }
 
 define void @concat_v4f64(<2 x double>* %a, <2 x double>* %b, <4 x double>* %c) #0 {
 ; CHECK-LABEL: concat_v4f64:
 ; CHECK: ldr q[[OP1:[0-9]+]], [x0]

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-extend-trunc.ll

 ; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #4
 ; VBITS_EQ_256-DAG: ld1d { [[LO:z[0-9]+]].d }, [[PG1]]/z, [x0]
 ; VBITS_EQ_256-DAG: ld1d { [[HI:z[0-9]+]].d }, [[PG1]]/z, [x0, x[[NUMELTS]], lsl #3]
 ; VBITS_EQ_256-DAG: ptrue [[PG2:p[0-9]+]].d
 ; VBITS_EQ_256-DAG: fcvt [[CVT_LO:z[0-9]+]].h, [[PG2]]/m, [[LO]].d
 ; VBITS_EQ_256-DAG: fcvt [[CVT_HI:z[0-9]+]].h, [[PG2]]/m, [[HI]].d
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_LO:z[0-9]+]].s, [[CVT_LO]].s, [[CVT_LO]].s
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_HI:z[0-9]+]].s, [[CVT_HI]].s, [[CVT_HI]].s
-; VBITS_EQ_256-DAG: uzp1 z0.h, [[UZP_LO]].h, [[UZP_LO]].h
+; VBITS_EQ_256-DAG: uzp1 z[[RES_LO:[0-9]+]].h, [[UZP_LO]].h, [[UZP_LO]].h
 ; VBITS_EQ_256-DAG: uzp1 z[[RES_HI:[0-9]+]].h, [[UZP_HI]].h, [[UZP_HI]].h
-; VBITS_EQ_256-DAG: mov v0.d[1], v[[RES_HI]].d[0]
+; VBITS_EQ_256-DAG: zip1 v0.2d, v[[RES_LO:[0-9]+]].2d, v[[RES_HI:[0-9]+]].2d
   %op1 = load <8 x double>, <8 x double>* %a
   %res = fptrunc <8 x double> %op1 to <8 x half>
   ret <8 x half> %res
 }
 
 define void @fcvt_v16f64_v16f16(<16 x double>* %a, <16 x half>* %b) #0 {
 ; CHECK-LABEL: fcvt_v16f64_v16f16:
 ; VBITS_GE_1024: ptrue [[PG1:p[0-9]+]].d, vl16

llvm/test/CodeGen/AArch64/sve-fixed-length-fp-to-int.ll

 ; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #4
 ; VBITS_EQ_256-DAG: ld1d { [[LO:z[0-9]+]].d }, [[PG]]/z, [x0]
 ; VBITS_EQ_256-DAG: ld1d { [[HI:z[0-9]+]].d }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #3]
 ; VBITS_EQ_256-DAG: ptrue [[PG2:p[0-9]+]].d
 ; VBITS_EQ_256-DAG: fcvtzu [[CVT_HI:z[0-9]+]].d, [[PG2]]/m, [[HI]].d
 ; VBITS_EQ_256-DAG: fcvtzu [[CVT_LO:z[0-9]+]].d, [[PG2]]/m, [[LO]].d
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_LO:z[0-9]+]].s, [[CVT_LO]].s, [[CVT_LO]].s
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_HI:z[0-9]+]].s, [[CVT_HI]].s, [[CVT_HI]].s
-; VBITS_EQ_256-DAG: uzp1 z0.h, [[UZP_LO]].h, [[UZP_LO]].h
+; VBITS_EQ_256-DAG: uzp1 z[[RES_LO:[0-9]+]].h, [[UZP_LO]].h, [[UZP_LO]].h
 ; VBITS_EQ_256-DAG: uzp1 z[[RES_HI:[0-9]+]].h, [[UZP_HI]].h, [[UZP_HI]].h
-; VBITS_EQ_256-NEXT: mov v0.d[1], v[[RES_HI]].d[0]
+; VBITS_EQ_256-NEXT: zip1 v0.2d, v[[RES_LO:[0-9]+]].2d, v[[RES_HI:[0-9]+]].2d
 ; VBITS_EQ_256-NEXT: ret
   %op1 = load <8 x double>, <8 x double>* %a
   %res = fptoui <8 x double> %op1 to <8 x i16>
   ret <8 x i16> %res
 }
 
 define void @fcvtzu_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) #0 {
 ; CHECK-LABEL: fcvtzu_v16f64_v16i16:

 ; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #4
 ; VBITS_EQ_256-DAG: ld1d { [[LO:z[0-9]+]].d }, [[PG]]/z, [x0]
 ; VBITS_EQ_256-DAG: ld1d { [[HI:z[0-9]+]].d }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #3]
 ; VBITS_EQ_256-DAG: ptrue [[PG2:p[0-9]+]].d
 ; VBITS_EQ_256-DAG: fcvtzs [[CVT_HI:z[0-9]+]].d, [[PG2]]/m, [[HI]].d
 ; VBITS_EQ_256-DAG: fcvtzs [[CVT_LO:z[0-9]+]].d, [[PG2]]/m, [[LO]].d
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_LO:z[0-9]+]].s, [[CVT_LO]].s, [[CVT_LO]].s
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_HI:z[0-9]+]].s, [[CVT_HI]].s, [[CVT_HI]].s
-; VBITS_EQ_256-DAG: uzp1 z0.h, [[UZP_LO]].h, [[UZP_LO]].h
+; VBITS_EQ_256-DAG: uzp1 z[[RES_LO:[0-9]+]].h, [[UZP_LO]].h, [[UZP_LO]].h
 ; VBITS_EQ_256-DAG: uzp1 z[[RES_HI:[0-9]+]].h, [[UZP_HI]].h, [[UZP_HI]].h
-; VBITS_EQ_256-NEXT: mov v0.d[1], v[[RES_HI]].d[0]
+; VBITS_EQ_256-NEXT: zip1 v0.2d, v[[RES_LO:[0-9]+]].2d, v[[RES_HI:[0-9]+]].2d
 ; VBITS_EQ_256-NEXT: ret
   %op1 = load <8 x double>, <8 x double>* %a
   %res = fptosi <8 x double> %op1 to <8 x i16>
   ret <8 x i16> %res
 }
 
 define void @fcvtzs_v16f64_v16i16(<16 x double>* %a, <16 x i16>* %b) #0 {
 ; CHECK-LABEL: fcvtzs_v16f64_v16i16:

llvm/test/CodeGen/AArch64/sve-fixed-length-int-to-fp.ll

 ; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #4
 ; VBITS_EQ_256-DAG: ld1d { [[LO:z[0-9]+]].d }, [[PG]]/z, [x0]
 ; VBITS_EQ_256-DAG: ld1d { [[HI:z[0-9]+]].d }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #3]
 ; VBITS_EQ_256-DAG: ptrue [[PG2:p[0-9]+]].d
 ; VBITS_EQ_256-DAG: ucvtf [[CVT_LO:z[0-9]+]].h, [[PG2]]/m, [[LO]].d
 ; VBITS_EQ_256-DAG: ucvtf [[CVT_HI:z[0-9]+]].h, [[PG2]]/m, [[HI]].d
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_LO:z[0-9]+]].s, [[CVT_LO]].s, [[CVT_LO]].s
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_HI:z[0-9]+]].s, [[CVT_HI]].s, [[CVT_HI]].s
-; VBITS_EQ_256-DAG: uzp1 z0.h, [[UZP_LO]].h, [[UZP_LO]].h
+; VBITS_EQ_256-DAG: uzp1 z[[RES_LO:[0-9]+]].h, [[UZP_LO]].h, [[UZP_LO]].h
 ; VBITS_EQ_256-DAG: uzp1 z[[RES_HI:[0-9]+]].h, [[UZP_HI]].h, [[UZP_HI]].h
-; VBITS_EQ_256-NEXT: mov v0.d[1], v[[RES_HI]].d[0]
+; VBITS_EQ_256-DAG: zip1 v0.2d, v[[RES_LO:[0-9]+]].2d, v[[RES_HI:[0-9]+]].2d
 ; VBITS_EQ_256-NEXT: ret
   %op1 = load <8 x i64>, <8 x i64>* %a
   %res = uitofp <8 x i64> %op1 to <8 x half>
   ret <8 x half> %res
 }
 
 define void @ucvtf_v16i64_v16f16(<16 x i64>* %a, <16 x half>* %b) #0 {
 ; CHECK-LABEL: ucvtf_v16i64_v16f16:

 ; VBITS_EQ_256-DAG: ld1d { [[HI:z[0-9]+]].d }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #3]
 ; VBITS_EQ_256-DAG: ptrue [[PG2:p[0-9]+]].d
 ; VBITS_EQ_256-DAG: scvtf [[CVT_LO:z[0-9]+]].h, [[PG2]]/m, [[LO]].d
 ; VBITS_EQ_256-DAG: scvtf [[CVT_HI:z[0-9]+]].h, [[PG2]]/m, [[HI]].d
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_LO:z[0-9]+]].s, [[CVT_LO]].s, [[CVT_LO]].s
 ; VBITS_EQ_256-DAG: uzp1 [[UZP_HI:z[0-9]+]].s, [[CVT_HI]].s, [[CVT_HI]].s
 ; VBITS_EQ_256-DAG: uzp1 z[[RES_LO:[0-9]+]].h, [[UZP_LO]].h, [[UZP_LO]].h
 ; VBITS_EQ_256-DAG: uzp1 z[[RES_HI:[0-9]+]].h, [[UZP_HI]].h, [[UZP_HI]].h
-; VBITS_EQ_256-NEXT: mov v[[RES_LO]].d[1], v[[RES_HI]].d[0]
+; VBITS_EQ_256-NEXT: zip1 v0.2d, v[[RES_LO]].2d, v[[RES_HI]].2d
 ; VBITS_EQ_256-NEXT: ret
   %op1 = load <8 x i64>, <8 x i64>* %a
   %res = sitofp <8 x i64> %op1 to <8 x half>
   ret <8 x half> %res
 }
 
 define void @scvtf_v16i64_v16f16(<16 x i64>* %a, <16 x half>* %b) #0 {
 ; CHECK-LABEL: scvtf_v16i64_v16f16:

llvm/test/CodeGen/AArch64/sve-fixed-length-masked-gather.ll

 ; VBITS_EQ_256-DAG: cmpne [[MASK_LO:p[0-9]+]].d, [[PG]]/z, [[UPK2_LO]].d, #0
 ; VBITS_EQ_256-DAG: cmpne [[MASK_HI:p[0-9]+]].d, [[PG]]/z, [[UPK2_HI]].d, #0
 ; VBITS_EQ_256-DAG: ld1h { [[RES_LO:z[0-9]+]].d }, [[MASK_LO]]/z, {{\[}}[[PTRS_LO]].d]
 ; VBITS_EQ_256-DAG: ld1h { [[RES_HI:z[0-9]+]].d }, [[MASK_HI]]/z, {{\[}}[[PTRS_HI]].d]
 ; VBITS_EQ_256-DAG: uzp1 [[UZP1_LO:z[0-9]+]].s, [[RES_LO]].s, [[RES_LO]].s
 ; VBITS_EQ_256-DAG: uzp1 z[[UZP2_LO:[0-9]+]].h, [[UZP1_LO]].h, [[UZP1_LO]].h
 ; VBITS_EQ_256-DAG: uzp1 [[UZP1_HI:z[0-9]+]].s, [[RES_HI]].s, [[RES_HI]].s
 ; VBITS_EQ_256-DAG: uzp1 z[[UZP2_HI:[0-9]+]].h, [[UZP1_HI]].h, [[UZP1_HI]].h
-; VBITS_EQ_256-NEXT: mov v[[UZP2_LO]].d[1], v[[UZP2_HI]].d[0]
-; VBITS_EQ_256-NEXT: str q[[UZP2_LO]], [x0]
+; VBITS_EQ_256-NEXT: zip1 v[[RESULT:[0-9]+]].2d, v[[UZP2_LO]].2d, v[[UZP2_HI]].2d
+; VBITS_EQ_256-NEXT: str q[[RESULT]], [x0]
 ; VBITS_EQ_256-NEXT: ret
   %cval = load <8 x i16>, <8 x i16>* %a
   %ptrs = load <8 x i16*>, <8 x i16*>* %b
   %mask = icmp eq <8 x i16> %cval, zeroinitializer
   %vals = call <8 x i16> @llvm.masked.gather.v8i16(<8 x i16*> %ptrs, i32 8, <8 x i1> %mask, <8 x i16> undef)
   store <8 x i16> %vals, <8 x i16>* %a
   ret void
 }

llvm/test/CodeGen/AArch64/sve-fixed-length-trunc-stores.ll

 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].d, vl4
 ; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #4
 ; VBITS_EQ_256-DAG: ld1d { [[DWORDS_LO:z[0-9]+]].d }, [[PG]]/z, [x0]
 ; VBITS_EQ_256-DAG: ld1d { [[DWORDS_HI:z[0-9]+]].d }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #3]
 ; VBITS_EQ_256-DAG: uzp1 [[WORDS_LO:z[0-9]+]].s, [[DWORDS_LO]].s, [[DWORDS_LO]].s
 ; VBITS_EQ_256-DAG: uzp1 [[WORDS_HI:z[0-9]+]].s, [[DWORDS_HI]].s, [[DWORDS_HI]].s
 ; VBITS_EQ_256-DAG: uzp1 z[[HALFS_LO:[0-9]+]].h, [[WORDS_LO]].h, [[WORDS_LO]].h
 ; VBITS_EQ_256-DAG: uzp1 z[[HALFS_HI:[0-9]+]].h, [[WORDS_HI]].h, [[WORDS_HI]].h
-; VBITS_EQ_256-NEXT: mov v[[HALFS_LO]].d[1], v[[HALFS_HI]].d[0]
-; VBITS_EQ_256-NEXT: str q[[HALFS_LO]], [x1]
+; VBITS_EQ_256-NEXT: zip1 v[[HALFS_STORE:[0-9]+]].2d, v[[HALFS_LO]].2d, v[[HALFS_HI]].2d
+; VBITS_EQ_256-NEXT: str q[[HALFS_STORE]], [x1]
 ; VBITS_EQ_256-NEXT: ret
   %a = load <8 x i64>, <8 x i64>* %ap
   %val = trunc <8 x i64> %a to <8 x i16>
   store <8 x i16> %val, <8 x i16>* %dest
   ret void
 }
 
 define void @store_trunc_v8i64i32(<8 x i64>* %ap, <8 x i32>* %dest) #0 {

 ; VBITS_EQ_256-DAG: ptrue [[PG:p[0-9]+]].s, vl8
 ; VBITS_EQ_256-DAG: mov x[[NUMELTS:[0-9]+]], #8
 ; VBITS_EQ_256-DAG: ld1w { [[WORDS_LO:z[0-9]+]].s }, [[PG]]/z, [x0]
 ; VBITS_EQ_256-DAG: ld1w { [[WORDS_HI:z[0-9]+]].s }, [[PG]]/z, [x0, x[[NUMELTS]], lsl #2]
 ; VBITS_EQ_256-DAG: uzp1 [[HALFS_LO:z[0-9]+]].h, [[WORDS_LO]].h, [[WORDS_LO]].h
 ; VBITS_EQ_256-DAG: uzp1 [[HALFS_HI:z[0-9]+]].h, [[WORDS_HI]].h, [[WORDS_HI]].h
 ; VBITS_EQ_256-DAG: uzp1 z[[BYTES_LO:[0-9]+]].b, [[HALFS_LO]].b, [[HALFS_LO]].b
 ; VBITS_EQ_256-DAG: uzp1 z[[BYTES_HI:[0-9]+]].b, [[HALFS_HI]].b, [[HALFS_HI]].b
-; VBITS_EQ_256-NEXT: mov v[[BYTES_LO]].d[1], v[[BYTES_HI]].d[0]
-; VBITS_EQ_256-NEXT: str q[[BYTES_LO]], [x1]
+; VBITS_EQ_256-NEXT: zip1 v[[BYTES_STORE:[0-9]+]].2d, v[[BYTES_LO]].2d, v[[BYTES_HI]].2d
+; VBITS_EQ_256-NEXT: str q[[BYTES_STORE]], [x1]
 ; VBITS_EQ_256-NEXT: ret
   %a = load <16 x i32>, <16 x i32>* %ap
   %val = trunc <16 x i32> %a to <16 x i8>
   store <16 x i8> %val, <16 x i8>* %dest
   ret void
 }
 
 define void @store_trunc_v16i32i16(<16 x i32>* %ap, <16 x i16>* %dest) #0 {

llvm/test/CodeGen/AArch64/vector-fcopysign.ll

 ; NOFP16-NEXT:    mov.h   v0[5], v5[0]
 ; NOFP16-NEXT:    mov.h   v0[6], v6[0]
 ; NOFP16-NEXT:    fcvt    h1, s4
 ; NOFP16-NEXT:    mov.h   v0[7]
 ; NOFP16-NEXT:    ret
 
 ; FP16-NEXT:    fcvtn   v2.4h, v2.4s
 ; FP16-NEXT:    fcvtn   v1.4h, v1.4s
-; FP16-NEXT:    mov.d   v1[1], v2[0]
+; FP16-NEXT:    zip1.2d v1, v1, v2
 ; FP16-NEXT:    movi.8h v2, #128, lsl #8
 ; FP16-NEXT:    bit.16b v0, v1, v2
 ; FP16-NEXT:    ret
   %tmp0 = fptrunc <8 x float> %b to <8 x half>
   %r = call <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %tmp0)
   ret <8 x half> %r
 }
 
 declare <8 x half> @llvm.copysign.v8f16(<8 x half> %a, <8 x half> %b) #0
 
 attributes #0 = { nounwind }