[AMDGPU] Support non-strictly stronger memory orderings in SIMemoryLegalizer

[t-tye]

Summary

C++20 no longer requires the failure memory ordering to be no stronger than the
success memory ordering. Adjust assert in AMD GPU SIMemoryLegalizer, and merge
instruction memory orderings

Add common operation to merge memory orders that allows non strict memory
orderings to be combined. Use it in SIMemoryLegalizer and
MachineMemOperand::getMergedOrdering.

[foad]

llvm/include/llvm/Support/AtomicOrdering.h

140–141

You don't need any of these innermost parentheses.

[foad]

llvm/include/llvm/Support/AtomicOrdering.h

136

Typo "A0" for "AO".

[efriedma]

No testcases?

llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

656–657

Isn't this just equivalent to FailureOrdering = MMO->getFailureOrdering()?

[efriedma]

llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

656–657

Oh, this is a loop; nevermind.

[arsenm]

Has the IR atomic semantics been updated to match the C++20 change yet?

[efriedma]

@arsenm See D98995, and my followups D103284/D103342. Not sure if everything is 100% fixed, but at least the basics are working.

[t-tye]

Remove unnecessary ()s.

Correct comment A0->AO.

Added tests.

[t-tye]

In D106729#2904861, @efriedma wrote:

No testcases?

Added tests.

llvm/include/llvm/Support/AtomicOrdering.h

136

Corrected.

140–141

Removed innermost parenthesis.

[rampitec]

Legalizer part LGTM. Not sure though how will it affect the rest of the languages since it implements C++20.

[t-tye]

@rampitec I believe the other changes do not change the behavior from the perspective of the C++ 20 standard.

@efriedma do those changes look ok?

[efriedma]

Haven't looked at the test changes in detail, but code changes look fine.

[t-tye]

In D106729#2935273, @efriedma wrote:

Haven't looked at the test changes in detail, but code changes look fine.

Thanks @efriedma. @rampitec reviewed the other code so I will proceed to commit.

llvm/include/llvm/CodeGen/MachineMemOperand.h

public:
   AtomicOrdering getFailureOrdering() const {
     return static_cast<AtomicOrdering>(AtomicInfo.FailureOrdering);
   }
 
   /// Return a single atomic ordering that is at least as strong as both the
   /// success and failure orderings for an atomic operation.  (For operations
   /// other than cmpxchg, this is equivalent to getSuccessOrdering().)
   AtomicOrdering getMergedOrdering() const {
-    AtomicOrdering Ordering = getSuccessOrdering();
-    AtomicOrdering FailureOrdering = getFailureOrdering();
-    if (FailureOrdering == AtomicOrdering::SequentiallyConsistent)
-      return AtomicOrdering::SequentiallyConsistent;
-    if (FailureOrdering == AtomicOrdering::Acquire) {
-      if (Ordering == AtomicOrdering::Monotonic)
-        return AtomicOrdering::Acquire;
-      if (Ordering == AtomicOrdering::Release)
-        return AtomicOrdering::AcquireRelease;
-    }
-    return Ordering;
+    return getMergedAtomicOrdering(getSuccessOrdering(), getFailureOrdering());
   }
 
   bool isLoad() const { return FlagVals & MOLoad; }
   bool isStore() const { return FlagVals & MOStore; }
   bool isVolatile() const { return FlagVals & MOVolatile; }
   bool isNonTemporal() const { return FlagVals & MONonTemporal; }
   bool isDereferenceable() const { return FlagVals & MODereferenceable; }
   bool isInvariant() const { return FlagVals & MOInvariant; }

llvm/include/llvm/Support/AtomicOrdering.h

 inline bool isAcquireOrStronger(AtomicOrdering AO) {
   return isAtLeastOrStrongerThan(AO, AtomicOrdering::Acquire);
 }
 
 inline bool isReleaseOrStronger(AtomicOrdering AO) {
   return isAtLeastOrStrongerThan(AO, AtomicOrdering::Release);
 }
 
+/// Return a single atomic ordering that is at least as strong as both the \p AO
+/// and \p Other orderings for an atomic operation.
+inline AtomicOrdering getMergedAtomicOrdering(AtomicOrdering AO,
+                                              AtomicOrdering Other) {
+  if ((AO == AtomicOrdering::Acquire && Other == AtomicOrdering::Release) ||
+      (AO == AtomicOrdering::Release && Other == AtomicOrdering::Acquire))
+    return AtomicOrdering::AcquireRelease;
+  return isStrongerThan(AO, Other) ? AO : Other;
+}
+
 inline AtomicOrderingCABI toCABI(AtomicOrdering AO) {
   static const AtomicOrderingCABI lookup[8] = {
       /* NotAtomic */ AtomicOrderingCABI::relaxed,
       /* Unordered */ AtomicOrderingCABI::relaxed,
       /* relaxed   */ AtomicOrderingCABI::relaxed,
       /* consume   */ AtomicOrderingCABI::consume,
       /* acquire   */ AtomicOrderingCABI::acquire,
       /* release   */ AtomicOrderingCABI::release,

llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

if (Ordering == AtomicOrdering::NotAtomic) {
              FailureOrdering == AtomicOrdering::NotAtomic);
       return;
     }
 
     assert(Scope != SIAtomicScope::NONE &&
            (OrderingAddrSpace & SIAtomicAddrSpace::ATOMIC) !=
                SIAtomicAddrSpace::NONE &&
            (InstrAddrSpace & SIAtomicAddrSpace::ATOMIC) !=
-               SIAtomicAddrSpace::NONE &&
-           !isStrongerThan(FailureOrdering, Ordering));
+               SIAtomicAddrSpace::NONE);
 
     // There is also no cross address space ordering if the ordering
     // address space is the same as the instruction address space and
     // only contains a single address space.
     if ((OrderingAddrSpace == InstrAddrSpace) &&
         isPowerOf2_32(uint32_t(InstrAddrSpace)))
       this->IsCrossAddressSpaceOrdering = false;
 
if (OpOrdering != AtomicOrdering::NotAtomic) {
           MMI->isSyncScopeInclusion(SSID, MMO->getSyncScopeID());
       if (!IsSyncScopeInclusion) {
         reportUnsupported(MI,
           "Unsupported non-inclusive atomic synchronization scope");
         return None;
       }
 
       SSID = IsSyncScopeInclusion.getValue() ? SSID : MMO->getSyncScopeID();
-      Ordering = isStrongerThan(Ordering, OpOrdering)
-                     ? Ordering
-                     : MMO->getSuccessOrdering();
+      Ordering = getMergedAtomicOrdering(Ordering, OpOrdering);
       assert(MMO->getFailureOrdering() != AtomicOrdering::Release &&
              MMO->getFailureOrdering() != AtomicOrdering::AcquireRelease);
       FailureOrdering =
-          isStrongerThan(FailureOrdering, MMO->getFailureOrdering()) ?
-              FailureOrdering : MMO->getFailureOrdering();
+          getMergedAtomicOrdering(FailureOrdering, MMO->getFailureOrdering());
     }
   }
 
   SIAtomicScope Scope = SIAtomicScope::NONE;
   SIAtomicAddrSpace OrderingAddrSpace = SIAtomicAddrSpace::NONE;
   bool IsCrossAddressSpaceOrdering = false;
   if (Ordering != AtomicOrdering::NotAtomic) {
     auto ScopeOrNone = toSIAtomicScope(SSID, InstrAddrSpace);