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[amdgpu] Handle the case where there is no scavenged register.
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Authored by hliao on Jul 21 2021, 8:07 AM.

Details

Reviewers
arsenm
rampitec
Summary
  • When an unconditional branch is expanded into an indirect branch, if there is no scavenged register, an SGPR pair needs spilling to enable the destination PC calculation. In addition, before jumping into the destination, that clobbered SGPR pair need restoring.
  • As SGPR cannot be spilled to or restored from memory directly, the spilling/restoring of that SGPR pair reuses the regular SGPR spilling support but without spilling it into memory. As that spilling and restoring points are fully controlled, we only need to spill that SGPR into the temporary VGPR, which needs spilling into its emergency slot.
  • The target-specific hook is revised to take additional restore block, where the restoring code is filled. After that, the relaxation will place that restore block directly before the destination block and insert an unconditional branch in any fall-through block into the destination block.

Diff Detail

Event Timeline

hliao created this revision.Jul 21 2021, 8:07 AM
hliao requested review of this revision.Jul 21 2021, 8:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 21 2021, 8:07 AM
hliao updated this revision to Diff 361744.Jul 26 2021, 12:00 PM

Rebase and kindly ping for review.

hliao updated this revision to Diff 364125.Aug 4 2021, 8:25 AM

Rebase and kindly PING for review.

arsenm added inline comments.Aug 6 2021, 6:26 AM
llvm/include/llvm/CodeGen/TargetInstrInfo.h
586

typo Optiionally

llvm/lib/CodeGen/BranchRelaxation.cpp
484–485

I'm pretty sure this is illegal, you can't have a branch to the entry block

llvm/test/CodeGen/AMDGPU/branch-relax-spill.ll
331

Where did this frame index come from?