[docs]Examples to show implementation of GISel in AArch64

[pooja2299]

Summary

Examples showing the IRTranslator phase of GISel is added. The lowering formal arguments and return values of call lowering part is shown. Examples of lowering function call is yet to be added.

[xgupta]

I think we need something similar to https://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector.

[paquette]

I think that including entire code snippets will probably rot over time and potentially confuse readers.

I think in general, it would be good to focus on high-level concepts so that we don't need to do as much work keeping this in sync with the code.

Also, I'm not sure if we have documentation on terminology like "incoming arguments". If we do, I think it would be useful to link to the documentation for the terminology.

llvm/docs/GlobalISel/AArch64examples.rst

2

Maybe more concise?

12

Can you expand on this a little?

• What kinds of examples does this documentation contain?
• What can the reader expect to find in this documentation?

22

I think that this code sample may rot over time. I think it would be better to describe, at a high level

• What lowering incoming arguments means
• What must be done to lower incoming arguments

And then say "see AArch64CallLowering::lowerFormalArguments" for a sample.

[pooja2299]

In D105798#2872479, @paquette wrote:

I think that including entire code snippets will probably rot over time and potentially confuse readers.

I think in general, it would be good to focus on high-level concepts so that we don't need to do as much work keeping this in sync with the code.

Also, I'm not sure if we have documentation on terminology like "incoming arguments". If we do, I think it would be useful to link to the documentation for the terminology.

yes sure. Thanks for your feedback. This is the basic structure that i thought to made . I will be writing more descriptions and will add only the relevant code. I just wanted to get a quick feedback from you all , so that I get an idea what needs to be added and deleted. Your reviews are really helpful. Thanks! I will update soon.

[pooja2299]

In D105798#2870627, @xgupta wrote:

I think we need something similar to https://llvm.org/docs/WritingAnLLVMBackend.html#instruction-selector.

okk. Thanks for giving a reference for the documentation structure.

[pooja2299]

llvm/docs/GlobalISel/AArch64examples.rst

2

Okk. Seems precise to me.

12

Yes, sure.

22

okk

[arsenm]

llvm/docs/GlobalISel/AArch64examples.rst

22

I agree, this will bitrot and is also too specific to AArch64

130

Most of this stuff shouldn't really be here, the generic code should be handling this so it's not great to say this is how you should handle returns

llvm/docs/GlobalISel/AArch64examples.rst

+===============================
+GISel Implementation In AArch64 
+===============================
+
+.. contents::
+   :local:
+   :depth: 1
+
+Introduction
+------------
+
+Illustrating with examples to show the implementation of GlobalISel in AArch64.
+
+IRTranslator
+------------
+To translate LLVM IR function to Generic MIR function. 
+
+Call Lowering
+^^^^^^^^^^^^^
+Lowering formal arguments:
+To lower incoming arguments.
+.. code-block:: none
+   bool AArch64CallLowering::lowerFormalArguments(
+     MachineIRBuilder &MIRBuilder, const Function &F,
+     ArrayRef<ArrayRef<Register>> VRegs, FunctionLoweringInfo &FLI) const {
+   MachineFunction &MF = MIRBuilder.getMF();
+   MachineBasicBlock &MBB = MIRBuilder.getMBB();
+   MachineRegisterInfo &MRI = MF.getRegInfo();
+   auto &DL = F.getParent()->getDataLayout();
+  
+   SmallVector<ArgInfo, 8> SplitArgs;
+   unsigned i = 0;
+   for (auto &Arg : F.args()) {
+     if (DL.getTypeStoreSize(Arg.getType()).isZero())
+       continue;
+  
+     ArgInfo OrigArg{VRegs[i], Arg, i};
+     setArgFlags(OrigArg, i + AttributeList::FirstArgIndex, DL, F);
+  
+     if (Arg.hasAttribute(Attribute::SwiftAsync))
+       MF.getInfo<AArch64FunctionInfo>()->setHasSwiftAsyncContext(true);
+  
+     splitToValueTypes(OrigArg, SplitArgs, DL, F.getCallingConv());
+     ++i;
+   }
+  
+   if (!MBB.empty())
+     MIRBuilder.setInstr(*MBB.begin());
+  
+   const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
+   CCAssignFn *AssignFn =
+       TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false);
+  
+   AArch64IncomingValueAssigner Assigner(AssignFn, AssignFn);
+   FormalArgHandler Handler(MIRBuilder, MRI);
+   if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
+                                      F.getCallingConv(), F.isVarArg()))
+     return false;
+  
+   AArch64FunctionInfo *FuncInfo = MF.getInfo<AArch64FunctionInfo>();
+   uint64_t StackOffset = Assigner.StackOffset;
+   if (F.isVarArg()) {
+     auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
+     if (!Subtarget.isTargetDarwin()) {
+       
+       return false;
+     }
+  
+
+     StackOffset =
+         alignTo(Assigner.StackOffset, Subtarget.isTargetILP32() ? 4 : 8);
+  
+     auto &MFI = MIRBuilder.getMF().getFrameInfo();
+     FuncInfo->setVarArgsStackIndex(MFI.CreateFixedObject(4, StackOffset, true));
+   }
+  
+   if (doesCalleeRestoreStack(F.getCallingConv(),
+                              MF.getTarget().Options.GuaranteedTailCallOpt)) {
+
+     StackOffset = alignTo(StackOffset, 16);
+
+     FuncInfo->setArgumentStackToRestore(StackOffset);
+   }
+  
+   FuncInfo->setBytesInStackArgArea(StackOffset);
+  
+   auto &Subtarget = MF.getSubtarget<AArch64Subtarget>();
+   if (Subtarget.hasCustomCallingConv())
+     Subtarget.getRegisterInfo()->UpdateCustomCalleeSavedRegs(MF);
+  
+   handleMustTailForwardedRegisters(MIRBuilder, AssignFn);
+  
+   MIRBuilder.setMBB(MBB);
+  
+   return true;
+   }
+
+Lowering return values:
+To lower outgoing return values into specified virtual registers.
+..  code-block:: none
+   bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
+                                      const Value *Val,
+                                      ArrayRef<Register> VRegs,
+                                      FunctionLoweringInfo &FLI,
+                                      Register SwiftErrorVReg) const {
+   auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
+   assert(((Val && !VRegs.empty()) || (!Val && VRegs.empty())) &&
+         "Return value without a vreg");
+
+   bool Success = true;
+   if (!VRegs.empty()) {
+      MachineFunction &MF = MIRBuilder.getMF();
+      const Function &F = MF.getFunction();
+      const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
+
+      MachineRegisterInfo &MRI = MF.getRegInfo();
+      const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>();
+      CCAssignFn *AssignFn = TLI.CCAssignFnForReturn(F.getCallingConv());
+      auto &DL = F.getParent()->getDataLayout();
+      LLVMContext &Ctx = Val->getType()->getContext();
+
+      SmallVector<EVT, 4> SplitEVTs;
+      ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
+      assert(VRegs.size() == SplitEVTs.size() &&
+            "For each split Type there should be exactly one VReg.");
+
+      SmallVector<ArgInfo, 8> SplitArgs;
+      CallingConv::ID CC = F.getCallingConv();
+
+      for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
+         if (TLI.getNumRegistersForCallingConv(Ctx, CC, SplitEVTs[i]) > 1) {
+         LLVM_DEBUG(dbgs() << "Can't handle extended arg types which need split");
+         return false;
+         }
+
+         Register CurVReg = VRegs[i];
+         ArgInfo CurArgInfo = ArgInfo{CurVReg, SplitEVTs[i].getTypeForEVT(Ctx)};
+         setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
+
+        
+         if (MRI.getType(CurVReg).getSizeInBits() == 1) {
+         CurVReg = MIRBuilder.buildZExt(LLT::scalar(8), CurVReg).getReg(0);
+         } else {
+       
+         MVT NewVT = TLI.getRegisterTypeForCallingConv(Ctx, CC, SplitEVTs[i]);
+         if (EVT(NewVT) != SplitEVTs[i]) {
+            unsigned ExtendOp = TargetOpcode::G_ANYEXT;
+            if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
+                                                Attribute::SExt))
+               ExtendOp = TargetOpcode::G_SEXT;
+            else if (F.getAttributes().hasAttribute(AttributeList::ReturnIndex,
+                                                   Attribute::ZExt))
+               ExtendOp = TargetOpcode::G_ZEXT;
+
+            LLT NewLLT(NewVT);
+            LLT OldLLT(MVT::getVT(CurArgInfo.Ty));
+            CurArgInfo.Ty = EVT(NewVT).getTypeForEVT(Ctx);
+           
+            if (NewVT.isVector()) {
+               if (OldLLT.isVector()) {
+               if (NewLLT.getNumElements() > OldLLT.getNumElements()) {
+                  
+                  if (NewLLT.getNumElements() != OldLLT.getNumElements() * 2) {
+                     LLVM_DEBUG(dbgs() << "Outgoing vector ret has too many elts");
+                     return false;
+                  }
+                  auto Undef = MIRBuilder.buildUndef({OldLLT});
+                  CurVReg =
+                     MIRBuilder.buildMerge({NewLLT}, {CurVReg, Undef}).getReg(0);
+               } else {
+                 
+                  CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
+                                 .getReg(0);
+               }
+               } else if (NewLLT.getNumElements() == 2) {
+             
+               auto Undef = MIRBuilder.buildUndef({OldLLT});
+               CurVReg =
+                     MIRBuilder
+                        .buildBuildVector({NewLLT}, {CurVReg, Undef.getReg(0)})
+                        .getReg(0);
+               } else {
+               LLVM_DEBUG(dbgs() << "Could not handle ret ty\n");
+               return false;
+               }
+            } else {
+               
+               if (NewLLT != MRI.getType(CurVReg)) {
+            
+               CurVReg = MIRBuilder.buildInstr(ExtendOp, {NewLLT}, {CurVReg})
+                              .getReg(0);
+               }
+            }
+         }
+         }
+         if (CurVReg != CurArgInfo.Regs[0]) {
+         CurArgInfo.Regs[0] = CurVReg;
+         // Reset the arg flags after modifying CurVReg.
+         setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
+         }
+         splitToValueTypes(CurArgInfo, SplitArgs, DL, CC);
+      }
+
+      AArch64OutgoingValueAssigner Assigner(AssignFn, AssignFn, Subtarget,
+                                             /*IsReturn*/ true);
+      OutgoingArgHandler Handler(MIRBuilder, MRI, MIB);
+      Success = determineAndHandleAssignments(Handler, Assigner, SplitArgs,
+                                             MIRBuilder, CC, F.isVarArg());
+   }
+
+   if (SwiftErrorVReg) {
+      MIB.addUse(AArch64::X21, RegState::Implicit);
+      MIRBuilder.buildCopy(AArch64::X21, SwiftErrorVReg);
+   }
+
+   MIRBuilder.insertInstr(MIB);
+   return Success;
+}
+
+
+
+Lowering function call: 
+
+
+