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Differential D105433

[AArch64][GlobalISel] Lower vector types for min/max
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Authored by Rin on Jul 5 2021, 7:10 AM.

Details

Reviewers
dmgreen
SjoerdMeijer
aemerson
paquette
Commits
rG5888a194c104: [AArch64][GlobalISel] Lower vector types for min/max
Summary

This patch allows vector types to be lowered for the min/max instruction in GlobalISel.

Diff Detail

Event Timeline

Rin created this revision.Jul 5 2021, 7:10 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls, rovka. · View Herald TranscriptJul 5 2021, 7:10 AM
Rin requested review of this revision.Jul 5 2021, 7:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 5 2021, 7:10 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
Rin edited the summary of this revision. (Show Details)Jul 5 2021, 7:11 AM
Rin added reviewers: dmgreen, SjoerdMeijer.
Rin added reviewers: aemerson, paquette.Jul 5 2021, 7:29 AM
Harbormaster completed remote builds in B112445: Diff 356500.Jul 5 2021, 7:43 AM
paquette added inline comments.Jul 6 2021, 10:35 AM
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
173

I think you can use the helper functions in LegalizerInfo.h here to make this a little cleaner:

.lowerIf(any(isScalar(0), isVector(0)))
aemerson added inline comments.Jul 6 2021, 11:33 PM
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
173

At this point, the rule just becomes equivalent to lower().

Rin added inline comments.Jul 7 2021, 1:07 AM
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
173

Good point, I'll just make it lower()

Rin updated this revision to Diff 356893.Jul 7 2021, 1:28 AM
Rin edited the summary of this revision. (Show Details)

Address review comments

Rin marked 2 inline comments as done.Jul 7 2021, 1:28 AM
aemerson accepted this revision.Jul 7 2021, 1:31 AM

LGTM.

This revision is now accepted and ready to land.Jul 7 2021, 1:31 AM
Harbormaster completed remote builds in B112747: Diff 356893.Jul 7 2021, 2:11 AM
Closed by commit rG5888a194c104: [AArch64][GlobalISel] Lower vector types for min/max (authored by Rin). · Explain WhyJul 7 2021, 7:34 AM
This revision was automatically updated to reflect the committed changes.
Rin added a commit: rG5888a194c104: [AArch64][GlobalISel] Lower vector types for min/max.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
GISel/
3 lines
test/
CodeGen/
AArch64/
GlobalISel/
506 lines

Diff 356500

llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp

Show First 20 Lines • Show All 163 Lines • ▼ Show 20 Lines getActionDefinitionsBuilder({G_SREM, G_UREM, G_SDIVREM, G_UDIVREM})
.lowerFor({s1, s8, s16, s32, s64}); .lowerFor({s1, s8, s16, s32, s64});
getActionDefinitionsBuilder({G_SMULO, G_UMULO}).lowerFor({{s64, s1}}); getActionDefinitionsBuilder({G_SMULO, G_UMULO}).lowerFor({{s64, s1}});
getActionDefinitionsBuilder({G_SMULH, G_UMULH}).legalFor({s32, s64}); getActionDefinitionsBuilder({G_SMULH, G_UMULH}).legalFor({s32, s64});
getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX}) getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
.legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32}) .legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
.lowerIf([=](const LegalityQuery &Q) { return Q.Types[0].isScalar(); }); .lowerIf([=](const LegalityQuery &Q) { return Q.Types[0].isScalar(); })
.lowerIf([=](const LegalityQuery &Q) { return Q.Types[0].isVector(); });
paquetteUnsubmitted
Done
ReplyInline Actions

I think you can use the helper functions in LegalizerInfo.h here to make this a little cleaner:

.lowerIf(any(isScalar(0), isVector(0)))
paquette: I think you can use the helper functions in LegalizerInfo.h here to make this a little cleaner…
aemersonUnsubmitted
Done
ReplyInline Actions

At this point, the rule just becomes equivalent to lower().

aemerson: At this point, the rule just becomes equivalent to `lower()`.
RinAuthorUnsubmitted
Done
ReplyInline Actions

Good point, I'll just make it lower()

Rin: Good point, I'll just make it lower()
getActionDefinitionsBuilder( getActionDefinitionsBuilder(
{G_SADDE, G_SSUBE, G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO}) {G_SADDE, G_SSUBE, G_UADDE, G_USUBE, G_SADDO, G_SSUBO, G_UADDO, G_USUBO})
.legalFor({{s32, s1}, {s64, s1}}) .legalFor({{s32, s1}, {s64, s1}})
.clampScalar(0, s32, s64) .clampScalar(0, s32, s64)
.widenScalarToNextPow2(0); .widenScalarToNextPow2(0);
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG}) getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG})
▲ Show 20 Lines • Show All 1,003 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir

Show First 20 Lines • Show All 121 Lines • ▼ Show 20 Lines bb.0:
; CHECK: RET_ReallyLR implicit $q0 ; CHECK: RET_ReallyLR implicit $q0
%vec:_(<4 x s32>) = G_IMPLICIT_DEF %vec:_(<4 x s32>) = G_IMPLICIT_DEF
%vec1:_(<4 x s32>) = G_IMPLICIT_DEF %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
%smin:_(<4 x s32>) = G_SMIN %vec, %vec1 %smin:_(<4 x s32>) = G_SMIN %vec, %vec1
$q0 = COPY %smin $q0 = COPY %smin
RET_ReallyLR implicit $q0 RET_ReallyLR implicit $q0
... ...
---
name: v2s64_smin
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v2s64_smin
; CHECK: liveins: $q0
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR]], [[BUILD_VECTOR1]]
; CHECK: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ASHR]]
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
; CHECK: %smin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: $q0 = COPY %smin(<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<2 x s64>) = G_IMPLICIT_DEF
%vec1:_(<2 x s64>) = G_IMPLICIT_DEF
%smin:_(<2 x s64>) = G_SMIN %vec, %vec1
$q0 = COPY %smin
RET_ReallyLR implicit $q0
...
---
name: v8s8_umin
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v8s8_umin
; CHECK: liveins: $x0
; CHECK: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
; CHECK: %umin:_(<8 x s8>) = G_UMIN %vec, %vec1
; CHECK: $x0 = COPY %umin(<8 x s8>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<8 x s8>) = G_IMPLICIT_DEF
%vec1:_(<8 x s8>) = G_IMPLICIT_DEF
%umin:_(<8 x s8>) = G_UMIN %vec, %vec1
$x0 = COPY %umin
RET_ReallyLR implicit $x0
...
---
name: v16s8_umin
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v16s8_umin
; CHECK: liveins: $q0
; CHECK: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK: %umin:_(<16 x s8>) = G_UMIN %vec, %vec1
; CHECK: $q0 = COPY %umin(<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<16 x s8>) = G_IMPLICIT_DEF
%vec1:_(<16 x s8>) = G_IMPLICIT_DEF
%umin:_(<16 x s8>) = G_UMIN %vec, %vec1
$q0 = COPY %umin
RET_ReallyLR implicit $q0
...
---
name: v4s16_umin
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v4s16_umin
; CHECK: liveins: $x0
; CHECK: %vec:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: %umin:_(<4 x s16>) = G_UMIN %vec, %vec1
; CHECK: $x0 = COPY %umin(<4 x s16>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<4 x s16>) = G_IMPLICIT_DEF
%vec1:_(<4 x s16>) = G_IMPLICIT_DEF
%umin:_(<4 x s16>) = G_UMIN %vec, %vec1
$x0 = COPY %umin
RET_ReallyLR implicit $x0
...
---
name: v8s16_umin
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_umin
; CHECK: liveins: $q0
; CHECK: %vec:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: %umin:_(<8 x s16>) = G_UMIN %vec, %vec1
; CHECK: $q0 = COPY %umin(<8 x s16>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<8 x s16>) = G_IMPLICIT_DEF
%vec1:_(<8 x s16>) = G_IMPLICIT_DEF
%umin:_(<8 x s16>) = G_UMIN %vec, %vec1
$q0 = COPY %umin
RET_ReallyLR implicit $q0
...
---
name: v2s32_umin
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v2s32_umin
; CHECK: liveins: $x0
; CHECK: %vec:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: %umin:_(<2 x s32>) = G_UMIN %vec, %vec1
; CHECK: $x0 = COPY %umin(<2 x s32>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<2 x s32>) = G_IMPLICIT_DEF
%vec1:_(<2 x s32>) = G_IMPLICIT_DEF
%umin:_(<2 x s32>) = G_UMIN %vec, %vec1
$x0 = COPY %umin
RET_ReallyLR implicit $x0
...
---
name: v4s32_umin
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v4s32_umin
; CHECK: liveins: $q0
; CHECK: %vec:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: %umin:_(<4 x s32>) = G_UMIN %vec, %vec1
; CHECK: $q0 = COPY %umin(<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<4 x s32>) = G_IMPLICIT_DEF
%vec1:_(<4 x s32>) = G_IMPLICIT_DEF
%umin:_(<4 x s32>) = G_UMIN %vec, %vec1
$q0 = COPY %umin
RET_ReallyLR implicit $q0
...
---
name: v2s64_umin
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v2s64_umin
; CHECK: liveins: $q0
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR]], [[BUILD_VECTOR1]]
; CHECK: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ASHR]]
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
; CHECK: %umin:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: $q0 = COPY %umin(<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<2 x s64>) = G_IMPLICIT_DEF
%vec1:_(<2 x s64>) = G_IMPLICIT_DEF
%umin:_(<2 x s64>) = G_UMIN %vec, %vec1
$q0 = COPY %umin
RET_ReallyLR implicit $q0
...
---
name: v8s8_smax
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v8s8_smax
; CHECK: liveins: $x0
; CHECK: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
; CHECK: %smax:_(<8 x s8>) = G_SMAX %vec, %vec1
; CHECK: $x0 = COPY %smax(<8 x s8>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<8 x s8>) = G_IMPLICIT_DEF
%vec1:_(<8 x s8>) = G_IMPLICIT_DEF
%smax:_(<8 x s8>) = G_SMAX %vec, %vec1
$x0 = COPY %smax
RET_ReallyLR implicit $x0
...
---
name: v16s8_smax
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v16s8_smax
; CHECK: liveins: $q0
; CHECK: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK: %smax:_(<16 x s8>) = G_SMAX %vec, %vec1
; CHECK: $q0 = COPY %smax(<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<16 x s8>) = G_IMPLICIT_DEF
%vec1:_(<16 x s8>) = G_IMPLICIT_DEF
%smax:_(<16 x s8>) = G_SMAX %vec, %vec1
$q0 = COPY %smax
RET_ReallyLR implicit $q0
...
---
name: v4s16_smax
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v4s16_smax
; CHECK: liveins: $x0
; CHECK: %vec:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: %smax:_(<4 x s16>) = G_SMAX %vec, %vec1
; CHECK: $x0 = COPY %smax(<4 x s16>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<4 x s16>) = G_IMPLICIT_DEF
%vec1:_(<4 x s16>) = G_IMPLICIT_DEF
%smax:_(<4 x s16>) = G_SMAX %vec, %vec1
$x0 = COPY %smax
RET_ReallyLR implicit $x0
...
---
name: v8s16_smax
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_smax
; CHECK: liveins: $q0
; CHECK: %vec:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: %smax:_(<8 x s16>) = G_SMAX %vec, %vec1
; CHECK: $q0 = COPY %smax(<8 x s16>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<8 x s16>) = G_IMPLICIT_DEF
%vec1:_(<8 x s16>) = G_IMPLICIT_DEF
%smax:_(<8 x s16>) = G_SMAX %vec, %vec1
$q0 = COPY %smax
RET_ReallyLR implicit $q0
...
---
name: v2s32_smax
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v2s32_smax
; CHECK: liveins: $x0
; CHECK: %vec:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: %smax:_(<2 x s32>) = G_SMAX %vec, %vec1
; CHECK: $x0 = COPY %smax(<2 x s32>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<2 x s32>) = G_IMPLICIT_DEF
%vec1:_(<2 x s32>) = G_IMPLICIT_DEF
%smax:_(<2 x s32>) = G_SMAX %vec, %vec1
$x0 = COPY %smax
RET_ReallyLR implicit $x0
...
---
name: v4s32_smax
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v4s32_smax
; CHECK: liveins: $q0
; CHECK: %vec:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: %smax:_(<4 x s32>) = G_SMAX %vec, %vec1
; CHECK: $q0 = COPY %smax(<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<4 x s32>) = G_IMPLICIT_DEF
%vec1:_(<4 x s32>) = G_IMPLICIT_DEF
%smax:_(<4 x s32>) = G_SMAX %vec, %vec1
$q0 = COPY %smax
RET_ReallyLR implicit $q0
...
---
name: v2s64_smax
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v2s64_smax
; CHECK: liveins: $q0
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR]], [[BUILD_VECTOR1]]
; CHECK: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ASHR]]
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
; CHECK: %smax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: $q0 = COPY %smax(<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<2 x s64>) = G_IMPLICIT_DEF
%vec1:_(<2 x s64>) = G_IMPLICIT_DEF
%smax:_(<2 x s64>) = G_SMAX %vec, %vec1
$q0 = COPY %smax
RET_ReallyLR implicit $q0
...
---
name: v8s8_umax
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v8s8_umax
; CHECK: liveins: $x0
; CHECK: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
; CHECK: %umax:_(<8 x s8>) = G_UMAX %vec, %vec1
; CHECK: $x0 = COPY %umax(<8 x s8>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<8 x s8>) = G_IMPLICIT_DEF
%vec1:_(<8 x s8>) = G_IMPLICIT_DEF
%umax:_(<8 x s8>) = G_UMAX %vec, %vec1
$x0 = COPY %umax
RET_ReallyLR implicit $x0
...
---
name: v16s8_umax
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v16s8_umax
; CHECK: liveins: $q0
; CHECK: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK: %umax:_(<16 x s8>) = G_UMAX %vec, %vec1
; CHECK: $q0 = COPY %umax(<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<16 x s8>) = G_IMPLICIT_DEF
%vec1:_(<16 x s8>) = G_IMPLICIT_DEF
%umax:_(<16 x s8>) = G_UMAX %vec, %vec1
$q0 = COPY %umax
RET_ReallyLR implicit $q0
...
---
name: v4s16_umax
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v4s16_umax
; CHECK: liveins: $x0
; CHECK: %vec:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: %umax:_(<4 x s16>) = G_UMAX %vec, %vec1
; CHECK: $x0 = COPY %umax(<4 x s16>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<4 x s16>) = G_IMPLICIT_DEF
%vec1:_(<4 x s16>) = G_IMPLICIT_DEF
%umax:_(<4 x s16>) = G_UMAX %vec, %vec1
$x0 = COPY %umax
RET_ReallyLR implicit $x0
...
---
name: v8s16_umax
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_umax
; CHECK: liveins: $q0
; CHECK: %vec:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: %umax:_(<8 x s16>) = G_UMAX %vec, %vec1
; CHECK: $q0 = COPY %umax(<8 x s16>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<8 x s16>) = G_IMPLICIT_DEF
%vec1:_(<8 x s16>) = G_IMPLICIT_DEF
%umax:_(<8 x s16>) = G_UMAX %vec, %vec1
$q0 = COPY %umax
RET_ReallyLR implicit $q0
...
---
name: v2s32_umax
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v2s32_umax
; CHECK: liveins: $x0
; CHECK: %vec:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: %umax:_(<2 x s32>) = G_UMAX %vec, %vec1
; CHECK: $x0 = COPY %umax(<2 x s32>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<2 x s32>) = G_IMPLICIT_DEF
%vec1:_(<2 x s32>) = G_IMPLICIT_DEF
%umax:_(<2 x s32>) = G_UMAX %vec, %vec1
$x0 = COPY %umax
RET_ReallyLR implicit $x0
...
---
name: v4s32_umax
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v4s32_umax
; CHECK: liveins: $q0
; CHECK: %vec:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: %umax:_(<4 x s32>) = G_UMAX %vec, %vec1
; CHECK: $q0 = COPY %umax(<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<4 x s32>) = G_IMPLICIT_DEF
%vec1:_(<4 x s32>) = G_IMPLICIT_DEF
%umax:_(<4 x s32>) = G_UMAX %vec, %vec1
$q0 = COPY %umax
RET_ReallyLR implicit $q0
...
---
name: v2s64_umax
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v2s64_umax
; CHECK: liveins: $q0
; CHECK: %vec:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec1
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY [[ICMP]](<2 x s64>)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64)
; CHECK: [[SHL:%[0-9]+]]:_(<2 x s64>) = G_SHL [[COPY]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[ASHR:%[0-9]+]]:_(<2 x s64>) = G_ASHR [[SHL]], [[BUILD_VECTOR]](<2 x s64>)
; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
; CHECK: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C1]](s64), [[C1]](s64)
; CHECK: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ASHR]], [[BUILD_VECTOR1]]
; CHECK: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ASHR]]
; CHECK: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]]
; CHECK: %umax:_(<2 x s64>) = G_OR [[AND]], [[AND1]]
; CHECK: $q0 = COPY %umax(<2 x s64>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<2 x s64>) = G_IMPLICIT_DEF
%vec1:_(<2 x s64>) = G_IMPLICIT_DEF
%umax:_(<2 x s64>) = G_UMAX %vec, %vec1
$q0 = COPY %umax
RET_ReallyLR implicit $q0
...