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[VP] Vector predicated vector splice intrinsic
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Authored by vkmr on Tue, Jun 8, 7:46 AM.

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Summary

This patch introduces the vector-predicated version of the experimental_vector_splice intrinsic [1] at the IR level. It considers the active vector length for both vectors and and uses a vector mask to disable certain lanes in the result.

[1] https://reviews.llvm.org/D94708

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Event Timeline

vkmr created this revision.Tue, Jun 8, 7:46 AM
vkmr requested review of this revision.Tue, Jun 8, 7:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptTue, Jun 8, 7:46 AM
vkmr retitled this revision from [VP] Length predicated vector splice intrinsic to [VP] Vector predicated vector splice intrinsic.Tue, Jun 8, 8:01 AM

As discussed on the call, maybe rename llvm.experimental.vp.vector.splice to llvm.experimental.vp.splice.. the "vector" is implied

Are evl1 and evl2 likely to be the same value? Do you have an example when they would be different?

vkmr added a comment.Thu, Jun 10, 6:51 AM

Are evl1 and evl2 likely to be the same value? Do you have an example when they would be different?

For a first order reduction, using a tail-folded loop with VP, if the EVL is computed using target-specific instructions, there is no guarantee that the EVL for the previous iteration would be the same as the EVL for current iteration or even that it would be equal to the runtime VF. For a more specific example, for RISC-V, the constraints on the vset{i}vl{i} instruction allow the EVL for the last non-tail iteration to be less than the runtime VF and unequal to the EVL for the tail iteration.

This patch needs to implement VPIntrinsic::getDeclarationForParams.