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Differential D103736

[RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions.
ClosedPublic

Authored by craig.topper on Jun 4 2021, 9:33 PM.

Details

Reviewers
rogfer01
HsiangKai
evandro
arcbbb
khchen
frasercrmck
Commits
rGc57bce9cc5fa: [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions.
Summary

In 0.9 these were defined to leave elements other than 0 in the
destination unmodified. They were changed to use the tail policy
in 0.10. I missed that update.

I assume no one has noticed because in order cores treat tail
agnostic the same as tail undisturbed. I believe Spike and QEMU do
the same.

Diff Detail

Event Timeline

craig.topper created this revision.Jun 4 2021, 9:33 PM
Herald added subscribers: StephenFan, vkmr, luismarques and 23 others. · View Herald TranscriptJun 4 2021, 9:33 PM
craig.topper requested review of this revision.Jun 4 2021, 9:33 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 4 2021, 9:33 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B107785: Diff 350018.Jun 4 2021, 10:06 PM
arcbbb accepted this revision.Jun 8 2021, 1:49 AM

LGTM

This revision is now accepted and ready to land.Jun 8 2021, 1:49 AM
frasercrmck accepted this revision.Jun 8 2021, 1:58 AM

LGTM, nice catch.

Closed by commit rGc57bce9cc5fa: [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions. (authored by craig.topper). · Explain WhyJun 8 2021, 9:23 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGc57bce9cc5fa: [RISCV] Remove ForceTailAgnostic flag from vmv.s.x, vfmv.s.f and reductions..

Revision Contents

Diff 350626

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

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multiclass VPseudoBinaryM_VX_VI { multiclass VPseudoBinaryM_VX_VI {
defm "" : VPseudoBinaryM_VX; defm "" : VPseudoBinaryM_VX;
defm "" : VPseudoBinaryM_VI; defm "" : VPseudoBinaryM_VI;
} }
multiclass VPseudoReductionV_VS { multiclass VPseudoReductionV_VS {
foreach m = MxList.m in { foreach m = MxList.m in {
let ForceTailAgnostic = true in
defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>; defm _VS : VPseudoTernary<V_M1.vrclass, m.vrclass, V_M1.vrclass, m>;
} }
} }
multiclass VPseudoConversion<VReg RetClass, multiclass VPseudoConversion<VReg RetClass,
VReg Op1Class, VReg Op1Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
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let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in { let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
foreach m = MxList.m in { foreach m = MxList.m in {
let VLMul = m.value in { let VLMul = m.value in {
let HasSEWOp = 1, BaseInstr = VMV_X_S in let HasSEWOp = 1, BaseInstr = VMV_X_S in
def PseudoVMV_X_S # "_" # m.MX: Pseudo<(outs GPR:$rd), def PseudoVMV_X_S # "_" # m.MX: Pseudo<(outs GPR:$rd),
(ins m.vrclass:$rs2, ixlenimm:$sew), (ins m.vrclass:$rs2, ixlenimm:$sew),
[]>, RISCVVPseudo; []>, RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X, let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
ForceTailAgnostic = true, Constraints = "$rd = $rs1" in Constraints = "$rd = $rs1" in
def PseudoVMV_S_X # "_" # m.MX: Pseudo<(outs m.vrclass:$rd), def PseudoVMV_S_X # "_" # m.MX: Pseudo<(outs m.vrclass:$rd),
(ins m.vrclass:$rs1, GPR:$rs2, (ins m.vrclass:$rs1, GPR:$rs2,
AVL:$vl, ixlenimm:$sew), AVL:$vl, ixlenimm:$sew),
[]>, RISCVVPseudo; []>, RISCVVPseudo;
} }
} }
} }
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]
Show All 9 Lines foreach f = FPList.fpinfo in {
let VLMul = m.value in { let VLMul = m.value in {
let HasSEWOp = 1, BaseInstr = VFMV_F_S in let HasSEWOp = 1, BaseInstr = VFMV_F_S in
def "PseudoVFMV_" # f.FX # "_S_" # m.MX : def "PseudoVFMV_" # f.FX # "_S_" # m.MX :
Pseudo<(outs f.fprclass:$rd), Pseudo<(outs f.fprclass:$rd),
(ins m.vrclass:$rs2, (ins m.vrclass:$rs2,
ixlenimm:$sew), ixlenimm:$sew),
[]>, RISCVVPseudo; []>, RISCVVPseudo;
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F, let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VFMV_S_F,
ForceTailAgnostic = true, Constraints = "$rd = $rs1" in Constraints = "$rd = $rs1" in
def "PseudoVFMV_S_" # f.FX # "_" # m.MX : def "PseudoVFMV_S_" # f.FX # "_" # m.MX :
Pseudo<(outs m.vrclass:$rd), Pseudo<(outs m.vrclass:$rd),
(ins m.vrclass:$rs1, f.fprclass:$rs2, (ins m.vrclass:$rs1, f.fprclass:$rs2,
AVL:$vl, ixlenimm:$sew), AVL:$vl, ixlenimm:$sew),
[]>, RISCVVPseudo; []>, RISCVVPseudo;
} }
} }
} }
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

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; LMULMAX2-RV64-NEXT: and a5, a5, t2 ; LMULMAX2-RV64-NEXT: and a5, a5, t2
; LMULMAX2-RV64-NEXT: or a4, a5, a4 ; LMULMAX2-RV64-NEXT: or a4, a5, a4
; LMULMAX2-RV64-NEXT: slli a5, a1, 40 ; LMULMAX2-RV64-NEXT: slli a5, a1, 40
; LMULMAX2-RV64-NEXT: and a3, a5, a3 ; LMULMAX2-RV64-NEXT: and a3, a5, a3
; LMULMAX2-RV64-NEXT: slli a1, a1, 56 ; LMULMAX2-RV64-NEXT: slli a1, a1, 56
; LMULMAX2-RV64-NEXT: or a1, a1, a3 ; LMULMAX2-RV64-NEXT: or a1, a1, a3
; LMULMAX2-RV64-NEXT: or a1, a1, a4 ; LMULMAX2-RV64-NEXT: or a1, a1, a4
; LMULMAX2-RV64-NEXT: or a1, a1, a2 ; LMULMAX2-RV64-NEXT: or a1, a1, a2
; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: bswap_v2i64: ; LMULMAX1-RV32-LABEL: bswap_v2i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu
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; LMULMAX1-RV64-NEXT: and a5, a5, t2 ; LMULMAX1-RV64-NEXT: and a5, a5, t2
; LMULMAX1-RV64-NEXT: or a4, a5, a4 ; LMULMAX1-RV64-NEXT: or a4, a5, a4
; LMULMAX1-RV64-NEXT: slli a5, a1, 40 ; LMULMAX1-RV64-NEXT: slli a5, a1, 40
; LMULMAX1-RV64-NEXT: and a3, a5, a3 ; LMULMAX1-RV64-NEXT: and a3, a5, a3
; LMULMAX1-RV64-NEXT: slli a1, a1, 56 ; LMULMAX1-RV64-NEXT: slli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a1, a3 ; LMULMAX1-RV64-NEXT: or a1, a1, a3
; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y %b = load <2 x i64>, <2 x i64>* %y
%c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a) %c = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %a)
store <2 x i64> %c, <2 x i64>* %x store <2 x i64> %c, <2 x i64>* %x
ret void ret void
} }
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; LMULMAX1-RV64-NEXT: and a5, a5, t3 ; LMULMAX1-RV64-NEXT: and a5, a5, t3
; LMULMAX1-RV64-NEXT: or a3, a5, a3 ; LMULMAX1-RV64-NEXT: or a3, a5, a3
; LMULMAX1-RV64-NEXT: slli a5, a1, 40 ; LMULMAX1-RV64-NEXT: slli a5, a1, 40
; LMULMAX1-RV64-NEXT: and a5, a5, a4 ; LMULMAX1-RV64-NEXT: and a5, a5, a4
; LMULMAX1-RV64-NEXT: slli a1, a1, 56 ; LMULMAX1-RV64-NEXT: slli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a1, a5 ; LMULMAX1-RV64-NEXT: or a1, a1, a5
; LMULMAX1-RV64-NEXT: or a1, a1, a3 ; LMULMAX1-RV64-NEXT: or a1, a1, a3
; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1 ; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 ; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: srli a2, a1, 40 ; LMULMAX1-RV64-NEXT: srli a2, a1, 40
; LMULMAX1-RV64-NEXT: and a2, a2, t0 ; LMULMAX1-RV64-NEXT: and a2, a2, t0
; LMULMAX1-RV64-NEXT: srli a3, a1, 56 ; LMULMAX1-RV64-NEXT: srli a3, a1, 56
; LMULMAX1-RV64-NEXT: or a2, a2, a3 ; LMULMAX1-RV64-NEXT: or a2, a2, a3
Show All 33 Lines
; LMULMAX1-RV64-NEXT: and a5, a5, t3 ; LMULMAX1-RV64-NEXT: and a5, a5, t3
; LMULMAX1-RV64-NEXT: or a3, a5, a3 ; LMULMAX1-RV64-NEXT: or a3, a5, a3
; LMULMAX1-RV64-NEXT: slli a5, a1, 40 ; LMULMAX1-RV64-NEXT: slli a5, a1, 40
; LMULMAX1-RV64-NEXT: and a4, a5, a4 ; LMULMAX1-RV64-NEXT: and a4, a5, a4
; LMULMAX1-RV64-NEXT: slli a1, a1, 56 ; LMULMAX1-RV64-NEXT: slli a1, a1, 56
; LMULMAX1-RV64-NEXT: or a1, a1, a4 ; LMULMAX1-RV64-NEXT: or a1, a1, a4
; LMULMAX1-RV64-NEXT: or a1, a1, a3 ; LMULMAX1-RV64-NEXT: or a1, a1, a3
; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v27, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v27, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v26, (a6) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a6)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a) %c = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %a)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>) declare <4 x i64> @llvm.bswap.v4i64(<4 x i64>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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; LMULMAX2-RV64-NEXT: srli a1, a1, 2 ; LMULMAX2-RV64-NEXT: srli a1, a1, 2
; LMULMAX2-RV64-NEXT: and a1, a1, a2 ; LMULMAX2-RV64-NEXT: and a1, a1, a2
; LMULMAX2-RV64-NEXT: add a1, a3, a1 ; LMULMAX2-RV64-NEXT: add a1, a3, a1
; LMULMAX2-RV64-NEXT: srli a2, a1, 4 ; LMULMAX2-RV64-NEXT: srli a2, a1, 4
; LMULMAX2-RV64-NEXT: add a1, a1, a2 ; LMULMAX2-RV64-NEXT: add a1, a1, a2
; LMULMAX2-RV64-NEXT: and a1, a1, a4 ; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: ctlz_v2i64: ; LMULMAX1-RV32-LABEL: ctlz_v2i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu
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; LMULMAX1-RV64-NEXT: srli a1, a1, 2 ; LMULMAX1-RV64-NEXT: srli a1, a1, 2
; LMULMAX1-RV64-NEXT: and a1, a1, a2 ; LMULMAX1-RV64-NEXT: and a1, a1, a2
; LMULMAX1-RV64-NEXT: add a1, a3, a1 ; LMULMAX1-RV64-NEXT: add a1, a3, a1
; LMULMAX1-RV64-NEXT: srli a2, a1, 4 ; LMULMAX1-RV64-NEXT: srli a2, a1, 4
; LMULMAX1-RV64-NEXT: add a1, a1, a2 ; LMULMAX1-RV64-NEXT: add a1, a1, a2
; LMULMAX1-RV64-NEXT: and a1, a1, a4 ; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y %b = load <2 x i64>, <2 x i64>* %y
%c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false) %c = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %a, i1 false)
store <2 x i64> %c, <2 x i64>* %x store <2 x i64> %c, <2 x i64>* %x
ret void ret void
} }
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; LMULMAX1-RV64-NEXT: srli a1, a1, 2 ; LMULMAX1-RV64-NEXT: srli a1, a1, 2
; LMULMAX1-RV64-NEXT: and a1, a1, a3 ; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: add a1, a2, a1 ; LMULMAX1-RV64-NEXT: add a1, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a1, 4 ; LMULMAX1-RV64-NEXT: srli a2, a1, 4
; LMULMAX1-RV64-NEXT: add a1, a1, a2 ; LMULMAX1-RV64-NEXT: add a1, a1, a2
; LMULMAX1-RV64-NEXT: and a1, a1, a4 ; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1 ; LMULMAX1-RV64-NEXT: vslidedown.vi v27, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27 ; LMULMAX1-RV64-NEXT: vmv.x.s a1, v27
; LMULMAX1-RV64-NEXT: srli a2, a1, 1 ; LMULMAX1-RV64-NEXT: srli a2, a1, 1
; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: or a1, a1, a2
; LMULMAX1-RV64-NEXT: srli a2, a1, 2 ; LMULMAX1-RV64-NEXT: srli a2, a1, 2
; LMULMAX1-RV64-NEXT: or a1, a1, a2 ; LMULMAX1-RV64-NEXT: or a1, a1, a2
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; LMULMAX1-RV64-NEXT: srli a1, a1, 2 ; LMULMAX1-RV64-NEXT: srli a1, a1, 2
; LMULMAX1-RV64-NEXT: and a1, a1, a3 ; LMULMAX1-RV64-NEXT: and a1, a1, a3
; LMULMAX1-RV64-NEXT: add a1, a2, a1 ; LMULMAX1-RV64-NEXT: add a1, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a1, 4 ; LMULMAX1-RV64-NEXT: srli a2, a1, 4
; LMULMAX1-RV64-NEXT: add a1, a1, a2 ; LMULMAX1-RV64-NEXT: add a1, a1, a2
; LMULMAX1-RV64-NEXT: and a1, a1, a4 ; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a1
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v27, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v27, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v26, (a6) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a6)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 false) %c = call <4 x i64> @llvm.ctlz.v4i64(<4 x i64> %a, i1 false)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1) declare <4 x i64> @llvm.ctlz.v4i64(<4 x i64>, i1)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll

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; LMULMAX2-RV64-NEXT: srli a1, a1, 2 ; LMULMAX2-RV64-NEXT: srli a1, a1, 2
; LMULMAX2-RV64-NEXT: and a1, a1, a2 ; LMULMAX2-RV64-NEXT: and a1, a1, a2
; LMULMAX2-RV64-NEXT: add a1, a3, a1 ; LMULMAX2-RV64-NEXT: add a1, a3, a1
; LMULMAX2-RV64-NEXT: srli a2, a1, 4 ; LMULMAX2-RV64-NEXT: srli a2, a1, 4
; LMULMAX2-RV64-NEXT: add a1, a1, a2 ; LMULMAX2-RV64-NEXT: add a1, a1, a2
; LMULMAX2-RV64-NEXT: and a1, a1, a4 ; LMULMAX2-RV64-NEXT: and a1, a1, a4
; LMULMAX2-RV64-NEXT: mul a1, a1, a5 ; LMULMAX2-RV64-NEXT: mul a1, a1, a5
; LMULMAX2-RV64-NEXT: srli a1, a1, 56 ; LMULMAX2-RV64-NEXT: srli a1, a1, 56
; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX2-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX2-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX2-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX2-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX2-RV64-NEXT: ret ; LMULMAX2-RV64-NEXT: ret
; ;
; LMULMAX1-RV32-LABEL: cttz_v2i64: ; LMULMAX1-RV32-LABEL: cttz_v2i64:
; LMULMAX1-RV32: # %bb.0: ; LMULMAX1-RV32: # %bb.0:
; LMULMAX1-RV32-NEXT: addi sp, sp, -32 ; LMULMAX1-RV32-NEXT: addi sp, sp, -32
; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32 ; LMULMAX1-RV32-NEXT: .cfi_def_cfa_offset 32
; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; LMULMAX1-RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu
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; LMULMAX1-RV64-NEXT: srli a1, a1, 2 ; LMULMAX1-RV64-NEXT: srli a1, a1, 2
; LMULMAX1-RV64-NEXT: and a1, a1, a2 ; LMULMAX1-RV64-NEXT: and a1, a1, a2
; LMULMAX1-RV64-NEXT: add a1, a3, a1 ; LMULMAX1-RV64-NEXT: add a1, a3, a1
; LMULMAX1-RV64-NEXT: srli a2, a1, 4 ; LMULMAX1-RV64-NEXT: srli a2, a1, 4
; LMULMAX1-RV64-NEXT: add a1, a1, a2 ; LMULMAX1-RV64-NEXT: add a1, a1, a2
; LMULMAX1-RV64-NEXT: and a1, a1, a4 ; LMULMAX1-RV64-NEXT: and a1, a1, a4
; LMULMAX1-RV64-NEXT: mul a1, a1, a5 ; LMULMAX1-RV64-NEXT: mul a1, a1, a5
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = load <2 x i64>, <2 x i64>* %y %b = load <2 x i64>, <2 x i64>* %y
%c = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false) %c = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %a, i1 false)
store <2 x i64> %c, <2 x i64>* %x store <2 x i64> %c, <2 x i64>* %x
ret void ret void
} }
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; LMULMAX1-RV64-NEXT: srli a2, a2, 2 ; LMULMAX1-RV64-NEXT: srli a2, a2, 2
; LMULMAX1-RV64-NEXT: and a2, a2, a3 ; LMULMAX1-RV64-NEXT: and a2, a2, a3
; LMULMAX1-RV64-NEXT: add a2, a4, a2 ; LMULMAX1-RV64-NEXT: add a2, a4, a2
; LMULMAX1-RV64-NEXT: srli a4, a2, 4 ; LMULMAX1-RV64-NEXT: srli a4, a2, 4
; LMULMAX1-RV64-NEXT: add a2, a2, a4 ; LMULMAX1-RV64-NEXT: add a2, a2, a4
; LMULMAX1-RV64-NEXT: and a2, a2, a5 ; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a2, a2, a1 ; LMULMAX1-RV64-NEXT: mul a2, a2, a1
; LMULMAX1-RV64-NEXT: srli a2, a2, 56 ; LMULMAX1-RV64-NEXT: srli a2, a2, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2 ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2
; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1 ; LMULMAX1-RV64-NEXT: vslidedown.vi v26, v25, 1
; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26 ; LMULMAX1-RV64-NEXT: vmv.x.s a2, v26
; LMULMAX1-RV64-NEXT: addi a4, a2, -1 ; LMULMAX1-RV64-NEXT: addi a4, a2, -1
; LMULMAX1-RV64-NEXT: not a2, a2 ; LMULMAX1-RV64-NEXT: not a2, a2
; LMULMAX1-RV64-NEXT: and a2, a2, a4 ; LMULMAX1-RV64-NEXT: and a2, a2, a4
; LMULMAX1-RV64-NEXT: srli a4, a2, 1 ; LMULMAX1-RV64-NEXT: srli a4, a2, 1
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; LMULMAX1-RV64-NEXT: srli a2, a2, 2 ; LMULMAX1-RV64-NEXT: srli a2, a2, 2
; LMULMAX1-RV64-NEXT: and a2, a2, a3 ; LMULMAX1-RV64-NEXT: and a2, a2, a3
; LMULMAX1-RV64-NEXT: add a2, a4, a2 ; LMULMAX1-RV64-NEXT: add a2, a4, a2
; LMULMAX1-RV64-NEXT: srli a3, a2, 4 ; LMULMAX1-RV64-NEXT: srli a3, a2, 4
; LMULMAX1-RV64-NEXT: add a2, a2, a3 ; LMULMAX1-RV64-NEXT: add a2, a2, a3
; LMULMAX1-RV64-NEXT: and a2, a2, a5 ; LMULMAX1-RV64-NEXT: and a2, a2, a5
; LMULMAX1-RV64-NEXT: mul a1, a2, a1 ; LMULMAX1-RV64-NEXT: mul a1, a2, a1
; LMULMAX1-RV64-NEXT: srli a1, a1, 56 ; LMULMAX1-RV64-NEXT: srli a1, a1, 56
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1 ; LMULMAX1-RV64-NEXT: vmv.s.x v26, a1
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v27, (a6) ; LMULMAX1-RV64-NEXT: vse64.v v27, (a6)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = load <4 x i64>, <4 x i64>* %y %b = load <4 x i64>, <4 x i64>* %y
%c = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 false) %c = call <4 x i64> @llvm.cttz.v4i64(<4 x i64> %a, i1 false)
store <4 x i64> %c, <4 x i64>* %x store <4 x i64> %c, <4 x i64>* %x
ret void ret void
} }
declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1) declare <4 x i64> @llvm.cttz.v4i64(<4 x i64>, i1)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: | FileCheck %s --check-prefixes=CHECK,RV64
define <1 x i1> @insertelt_v1i1(<1 x i1> %x, i1 %elt) nounwind { define <1 x i1> @insertelt_v1i1(<1 x i1> %x, i1 %elt) nounwind {
; CHECK-LABEL: insertelt_v1i1: ; CHECK-LABEL: insertelt_v1i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 1, e8,mf8,ta,mu ; CHECK-NEXT: vsetivli zero, 1, e8,mf8,ta,mu
; CHECK-NEXT: vmv.v.i v25, 0 ; CHECK-NEXT: vmv.v.i v25, 0
; CHECK-NEXT: vmerge.vim v25, v25, 1, v0 ; CHECK-NEXT: vmerge.vim v25, v25, 1, v0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu
; CHECK-NEXT: vmv.s.x v25, a0 ; CHECK-NEXT: vmv.s.x v25, a0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vand.vi v25, v25, 1
; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmsne.vi v0, v25, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%y = insertelement <1 x i1> %x, i1 %elt, i64 0 %y = insertelement <1 x i1> %x, i1 %elt, i64 0
ret <1 x i1> %y ret <1 x i1> %y
} }
define <1 x i1> @insertelt_idx_v1i1(<1 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind { define <1 x i1> @insertelt_idx_v1i1(<1 x i1> %x, i1 %elt, i32 zeroext %idx) nounwind {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll

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; RV32-NEXT: vsetivli zero, 8, e32,m2,ta,mu ; RV32-NEXT: vsetivli zero, 8, e32,m2,ta,mu
; RV32-NEXT: vmv.v.i v28, 0 ; RV32-NEXT: vmv.v.i v28, 0
; RV32-NEXT: vsetivli zero, 2, e64,m2,tu,mu ; RV32-NEXT: vsetivli zero, 2, e64,m2,tu,mu
; RV32-NEXT: vslideup.vi v28, v26, 0 ; RV32-NEXT: vslideup.vi v28, v26, 0
; RV32-NEXT: lw a3, 16(a0) ; RV32-NEXT: lw a3, 16(a0)
; RV32-NEXT: addi a4, a0, 20 ; RV32-NEXT: addi a4, a0, 20
; RV32-NEXT: vsetivli zero, 4, e32,m1,ta,mu ; RV32-NEXT: vsetivli zero, 4, e32,m1,ta,mu
; RV32-NEXT: vlse32.v v26, (a4), zero ; RV32-NEXT: vlse32.v v26, (a4), zero
; RV32-NEXT: vsetvli zero, zero, e32,m1,tu,mu
; RV32-NEXT: vmv.s.x v26, a3 ; RV32-NEXT: vmv.s.x v26, a3
; RV32-NEXT: vsetvli zero, zero, e64,m2,tu,mu ; RV32-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; RV32-NEXT: vslideup.vi v28, v26, 2 ; RV32-NEXT: vslideup.vi v28, v26, 2
; RV32-NEXT: vsetivli zero, 2, e32,m2,ta,mu ; RV32-NEXT: vsetivli zero, 2, e32,m2,ta,mu
; RV32-NEXT: vmv.v.i v26, 0 ; RV32-NEXT: vmv.v.i v26, 0
; RV32-NEXT: vslide1up.vx v30, v26, a2 ; RV32-NEXT: vslide1up.vx v30, v26, a2
; RV32-NEXT: vslide1up.vx v26, v30, a1 ; RV32-NEXT: vslide1up.vx v26, v30, a1
; RV32-NEXT: vsetivli zero, 3, e64,m2,tu,mu ; RV32-NEXT: vsetivli zero, 3, e64,m2,tu,mu
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} }
define void @insertelt_v8i64_0(<8 x i64>* %x) { define void @insertelt_v8i64_0(<8 x i64>* %x) {
; CHECK-LABEL: insertelt_v8i64_0: ; CHECK-LABEL: insertelt_v8i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64,m4,ta,mu ; CHECK-NEXT: vsetivli zero, 8, e64,m4,ta,mu
; CHECK-NEXT: vle64.v v28, (a0) ; CHECK-NEXT: vle64.v v28, (a0)
; CHECK-NEXT: addi a1, zero, -1 ; CHECK-NEXT: addi a1, zero, -1
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv.s.x v28, a1 ; CHECK-NEXT: vmv.s.x v28, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m4,ta,mu
; CHECK-NEXT: vse64.v v28, (a0) ; CHECK-NEXT: vse64.v v28, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 -1, i32 0 %b = insertelement <8 x i64> %a, i64 -1, i32 0
store <8 x i64> %b, <8 x i64>* %x store <8 x i64> %b, <8 x i64>* %x
ret void ret void
} }
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} }
define void @insertelt_c6_v8i64_0(<8 x i64>* %x) { define void @insertelt_c6_v8i64_0(<8 x i64>* %x) {
; CHECK-LABEL: insertelt_c6_v8i64_0: ; CHECK-LABEL: insertelt_c6_v8i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64,m4,ta,mu ; CHECK-NEXT: vsetivli zero, 8, e64,m4,ta,mu
; CHECK-NEXT: vle64.v v28, (a0) ; CHECK-NEXT: vle64.v v28, (a0)
; CHECK-NEXT: addi a1, zero, 6 ; CHECK-NEXT: addi a1, zero, 6
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv.s.x v28, a1 ; CHECK-NEXT: vmv.s.x v28, a1
; CHECK-NEXT: vsetvli zero, zero, e64,m4,ta,mu
; CHECK-NEXT: vse64.v v28, (a0) ; CHECK-NEXT: vse64.v v28, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 6, i32 0 %b = insertelement <8 x i64> %a, i64 6, i32 0
store <8 x i64> %b, <8 x i64>* %x store <8 x i64> %b, <8 x i64>* %x
ret void ret void
} }
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; Test that using a insertelement at element 0 by a later operation doesn't ; Test that using a insertelement at element 0 by a later operation doesn't
; crash the compiler. ; crash the compiler.
define void @insertelt_c6_v8i64_0_add(<8 x i64>* %x, <8 x i64>* %y) { define void @insertelt_c6_v8i64_0_add(<8 x i64>* %x, <8 x i64>* %y) {
; CHECK-LABEL: insertelt_c6_v8i64_0_add: ; CHECK-LABEL: insertelt_c6_v8i64_0_add:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e64,m4,ta,mu ; CHECK-NEXT: vsetivli zero, 8, e64,m4,ta,mu
; CHECK-NEXT: vle64.v v28, (a0) ; CHECK-NEXT: vle64.v v28, (a0)
; CHECK-NEXT: addi a2, zero, 6
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv.s.x v28, a2
; CHECK-NEXT: vsetvli zero, zero, e64,m4,ta,mu
; CHECK-NEXT: vle64.v v8, (a1) ; CHECK-NEXT: vle64.v v8, (a1)
; CHECK-NEXT: addi a1, zero, 6
; CHECK-NEXT: vmv.s.x v28, a1
; CHECK-NEXT: vadd.vv v28, v28, v8 ; CHECK-NEXT: vadd.vv v28, v28, v8
; CHECK-NEXT: vse64.v v28, (a0) ; CHECK-NEXT: vse64.v v28, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x i64>, <8 x i64>* %x %a = load <8 x i64>, <8 x i64>* %x
%b = insertelement <8 x i64> %a, i64 6, i32 0 %b = insertelement <8 x i64> %a, i64 6, i32 0
%c = load <8 x i64>, <8 x i64>* %y %c = load <8 x i64>, <8 x i64>* %y
%d = add <8 x i64> %b, %c %d = add <8 x i64> %b, %c
store <8 x i64> %d, <8 x i64>* %x store <8 x i64> %d, <8 x i64>* %x
ret void ret void
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll

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ret void ret void
} }
define void @buildvec_dominant2_v2i8(<2 x i8>* %x) { define void @buildvec_dominant2_v2i8(<2 x i8>* %x) {
; CHECK-LABEL: buildvec_dominant2_v2i8: ; CHECK-LABEL: buildvec_dominant2_v2i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8,mf8,ta,mu ; CHECK-NEXT: vsetivli zero, 2, e8,mf8,ta,mu
; CHECK-NEXT: vmv.v.i v25, -1 ; CHECK-NEXT: vmv.v.i v25, -1
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu
; CHECK-NEXT: vmv.s.x v25, zero ; CHECK-NEXT: vmv.s.x v25, zero
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
; CHECK-NEXT: vse8.v v25, (a0) ; CHECK-NEXT: vse8.v v25, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
store <2 x i8> <i8 0, i8 -1>, <2 x i8>* %x store <2 x i8> <i8 0, i8 -1>, <2 x i8>* %x
ret void ret void
} }
define void @buildvec_dominant0_v2i32(<2 x i64>* %x) { define void @buildvec_dominant0_v2i32(<2 x i64>* %x) {
; RV32-LABEL: buildvec_dominant0_v2i32: ; RV32-LABEL: buildvec_dominant0_v2i32:
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; RV64-NEXT: lui a1, 3641 ; RV64-NEXT: lui a1, 3641
; RV64-NEXT: addiw a1, a1, -455 ; RV64-NEXT: addiw a1, a1, -455
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -455 ; RV64-NEXT: addi a1, a1, -455
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -455 ; RV64-NEXT: addi a1, a1, -455
; RV64-NEXT: slli a1, a1, 13 ; RV64-NEXT: slli a1, a1, 13
; RV64-NEXT: addi a1, a1, -910 ; RV64-NEXT: addi a1, a1, -910
; RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; RV64-NEXT: vmv.s.x v25, a1 ; RV64-NEXT: vmv.s.x v25, a1
; RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; RV64-NEXT: vse64.v v25, (a0) ; RV64-NEXT: vse64.v v25, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
store <2 x i64> <i64 2049638230412172402, i64 -1>, <2 x i64>* %x store <2 x i64> <i64 2049638230412172402, i64 -1>, <2 x i64>* %x
ret void ret void
} }
define void @buildvec_dominant1_optsize_v2i32(<2 x i64>* %x) optsize { define void @buildvec_dominant1_optsize_v2i32(<2 x i64>* %x) optsize {
; RV32-LABEL: buildvec_dominant1_optsize_v2i32: ; RV32-LABEL: buildvec_dominant1_optsize_v2i32:
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

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; CHECK-NEXT: vsetivli zero, 8, e16,m1,ta,mu ; CHECK-NEXT: vsetivli zero, 8, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.i v27, 3 ; CHECK-NEXT: vmv.v.i v27, 3
; CHECK-NEXT: vmerge.vim v27, v27, 2, v0 ; CHECK-NEXT: vmerge.vim v27, v27, 2, v0
; CHECK-NEXT: vsetivli zero, 7, e16,m1,tu,mu ; CHECK-NEXT: vsetivli zero, 7, e16,m1,tu,mu
; CHECK-NEXT: vslideup.vi v27, v26, 6 ; CHECK-NEXT: vslideup.vi v27, v26, 6
; CHECK-NEXT: vsetivli zero, 8, e16,m1,ta,mu ; CHECK-NEXT: vsetivli zero, 8, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.i v28, 0 ; CHECK-NEXT: vmv.v.i v28, 0
; CHECK-NEXT: lui a1, 1048568 ; CHECK-NEXT: lui a1, 1048568
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu
; CHECK-NEXT: vmv1r.v v29, v28 ; CHECK-NEXT: vmv1r.v v29, v28
; CHECK-NEXT: vmv.s.x v29, a1 ; CHECK-NEXT: vmv.s.x v29, a1
; CHECK-NEXT: vsetivli zero, 7, e16,m1,tu,mu ; CHECK-NEXT: vsetivli zero, 7, e16,m1,tu,mu
; CHECK-NEXT: vslideup.vi v28, v26, 6 ; CHECK-NEXT: vslideup.vi v28, v26, 6
; CHECK-NEXT: vsetivli zero, 8, e16,m1,ta,mu ; CHECK-NEXT: vsetivli zero, 8, e16,m1,ta,mu
; CHECK-NEXT: lui a1, %hi(.LCPI53_0) ; CHECK-NEXT: lui a1, %hi(.LCPI53_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI53_0)
; CHECK-NEXT: vle16.v v26, (a1) ; CHECK-NEXT: vle16.v v26, (a1)
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; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mulhu_v2i64: ; RV64-LABEL: mulhu_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vle64.v v25, (a0)
; RV64-NEXT: vmv.v.i v26, 2 ; RV64-NEXT: vmv.v.i v26, 2
; RV64-NEXT: addi a1, zero, 1 ; RV64-NEXT: addi a1, zero, 1
; RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; RV64-NEXT: vmv.s.x v26, a1 ; RV64-NEXT: vmv.s.x v26, a1
; RV64-NEXT: lui a1, 1035469 ; RV64-NEXT: lui a1, 1035469
; RV64-NEXT: addiw a1, a1, -819 ; RV64-NEXT: addiw a1, a1, -819
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -819 ; RV64-NEXT: addi a1, a1, -819
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -819 ; RV64-NEXT: addi a1, a1, -819
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -819 ; RV64-NEXT: addi a1, a1, -819
; RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; RV64-NEXT: vmv.v.x v27, a1 ; RV64-NEXT: vmv.v.x v27, a1
; RV64-NEXT: lui a1, 1026731 ; RV64-NEXT: lui a1, 1026731
; RV64-NEXT: addiw a1, a1, -1365 ; RV64-NEXT: addiw a1, a1, -1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -1365 ; RV64-NEXT: addi a1, a1, -1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -1365 ; RV64-NEXT: addi a1, a1, -1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, -1365 ; RV64-NEXT: addi a1, a1, -1365
; RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; RV64-NEXT: vmv.s.x v27, a1 ; RV64-NEXT: vmv.s.x v27, a1
; RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; RV64-NEXT: vmulhu.vv v25, v25, v27 ; RV64-NEXT: vmulhu.vv v25, v25, v27
; RV64-NEXT: vsrl.vv v25, v25, v26 ; RV64-NEXT: vsrl.vv v25, v25, v26
; RV64-NEXT: vse64.v v25, (a0) ; RV64-NEXT: vse64.v v25, (a0)
; RV64-NEXT: ret ; RV64-NEXT: ret
%a = load <2 x i64>, <2 x i64>* %x %a = load <2 x i64>, <2 x i64>* %x
%b = udiv <2 x i64> %a, <i64 3, i64 5> %b = udiv <2 x i64> %a, <i64 3, i64 5>
store <2 x i64> %b, <2 x i64>* %x store <2 x i64> %b, <2 x i64>* %x
ret void ret void
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; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; RV32-NEXT: vle64.v v25, (a0) ; RV32-NEXT: vle64.v v25, (a0)
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a2, a1, 1365 ; RV32-NEXT: addi a2, a1, 1365
; RV32-NEXT: vsetivli zero, 4, e32,m1,ta,mu ; RV32-NEXT: vsetivli zero, 4, e32,m1,ta,mu
; RV32-NEXT: vmv.v.x v26, a2 ; RV32-NEXT: vmv.v.x v26, a2
; RV32-NEXT: addi a1, a1, 1366 ; RV32-NEXT: addi a1, a1, 1366
; RV32-NEXT: vsetvli zero, zero, e32,m1,tu,mu
; RV32-NEXT: vmv.s.x v26, a1 ; RV32-NEXT: vmv.s.x v26, a1
; RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; RV32-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; RV32-NEXT: vmulh.vv v26, v25, v26 ; RV32-NEXT: vmulh.vv v26, v25, v26
; RV32-NEXT: addi a1, zero, 3 ; RV32-NEXT: addi a1, zero, 3
; RV32-NEXT: vsetivli zero, 1, e8,mf8,ta,mu ; RV32-NEXT: vsetivli zero, 1, e8,mf8,ta,mu
; RV32-NEXT: vmv.s.x v0, a1 ; RV32-NEXT: vmv.s.x v0, a1
; RV32-NEXT: vsetivli zero, 4, e32,m1,ta,mu ; RV32-NEXT: vsetivli zero, 4, e32,m1,ta,mu
; RV32-NEXT: vmv.v.i v27, -1 ; RV32-NEXT: vmv.v.i v27, -1
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; RV32-NEXT: vse64.v v25, (a0) ; RV32-NEXT: vse64.v v25, (a0)
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: mulhs_v2i64: ; RV64-LABEL: mulhs_v2i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; RV64-NEXT: vle64.v v25, (a0) ; RV64-NEXT: vle64.v v25, (a0)
; RV64-NEXT: vmv.v.i v26, -1 ; RV64-NEXT: vmv.v.i v26, -1
; RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; RV64-NEXT: vmv.s.x v26, zero ; RV64-NEXT: vmv.s.x v26, zero
; RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; RV64-NEXT: vmul.vv v26, v25, v26 ; RV64-NEXT: vmul.vv v26, v25, v26
; RV64-NEXT: lui a1, 21845 ; RV64-NEXT: lui a1, 21845
; RV64-NEXT: addiw a1, a1, 1365 ; RV64-NEXT: addiw a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, 1365 ; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a1, a1, 1365 ; RV64-NEXT: addi a1, a1, 1365
; RV64-NEXT: slli a1, a1, 12 ; RV64-NEXT: slli a1, a1, 12
; RV64-NEXT: addi a2, a1, 1365 ; RV64-NEXT: addi a2, a1, 1365
; RV64-NEXT: vmv.v.x v27, a2 ; RV64-NEXT: vmv.v.x v27, a2
; RV64-NEXT: addi a1, a1, 1366 ; RV64-NEXT: addi a1, a1, 1366
; RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; RV64-NEXT: vmv.s.x v27, a1 ; RV64-NEXT: vmv.s.x v27, a1
; RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; RV64-NEXT: vmulh.vv v25, v25, v27 ; RV64-NEXT: vmulh.vv v25, v25, v27
; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vadd.vv v25, v25, v26
; RV64-NEXT: addi a1, zero, 63 ; RV64-NEXT: addi a1, zero, 63
; RV64-NEXT: vsrl.vx v26, v25, a1 ; RV64-NEXT: vsrl.vx v26, v25, a1
; RV64-NEXT: vid.v v27 ; RV64-NEXT: vid.v v27
; RV64-NEXT: vsra.vv v25, v25, v27 ; RV64-NEXT: vsra.vv v25, v25, v27
; RV64-NEXT: vadd.vv v25, v25, v26 ; RV64-NEXT: vadd.vv v25, v25, v26
; RV64-NEXT: vse64.v v25, (a0) ; RV64-NEXT: vse64.v v25, (a0)
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; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v26, (a1) ; LMULMAX1-RV64-NEXT: vle64.v v26, (a1)
; LMULMAX1-RV64-NEXT: vmv.v.i v27, 0 ; LMULMAX1-RV64-NEXT: vmv.v.i v27, 0
; LMULMAX1-RV64-NEXT: addi a2, zero, -1 ; LMULMAX1-RV64-NEXT: addi a2, zero, -1
; LMULMAX1-RV64-NEXT: slli a2, a2, 63 ; LMULMAX1-RV64-NEXT: slli a2, a2, 63
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2 ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2
; LMULMAX1-RV64-NEXT: lui a2, 1044935 ; LMULMAX1-RV64-NEXT: lui a2, 1044935
; LMULMAX1-RV64-NEXT: addiw a2, a2, 455 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 455
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, 455 ; LMULMAX1-RV64-NEXT: addi a2, a2, 455
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, 455 ; LMULMAX1-RV64-NEXT: addi a2, a2, 455
; LMULMAX1-RV64-NEXT: slli a2, a2, 13 ; LMULMAX1-RV64-NEXT: slli a2, a2, 13
; LMULMAX1-RV64-NEXT: addi a2, a2, 911 ; LMULMAX1-RV64-NEXT: addi a2, a2, 911
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.v.x v28, a2 ; LMULMAX1-RV64-NEXT: vmv.v.x v28, a2
; LMULMAX1-RV64-NEXT: lui a2, 4681 ; LMULMAX1-RV64-NEXT: lui a2, 4681
; LMULMAX1-RV64-NEXT: addiw a2, a2, 585 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 585
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, 585 ; LMULMAX1-RV64-NEXT: addi a2, a2, 585
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, 585 ; LMULMAX1-RV64-NEXT: addi a2, a2, 585
; LMULMAX1-RV64-NEXT: slli a2, a2, 13 ; LMULMAX1-RV64-NEXT: slli a2, a2, 13
; LMULMAX1-RV64-NEXT: addi a2, a2, 1171 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1171
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v28, a2 ; LMULMAX1-RV64-NEXT: vmv.s.x v28, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmulhu.vv v28, v26, v28 ; LMULMAX1-RV64-NEXT: vmulhu.vv v28, v26, v28
; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v28 ; LMULMAX1-RV64-NEXT: vsub.vv v26, v26, v28
; LMULMAX1-RV64-NEXT: vmulhu.vv v26, v26, v27 ; LMULMAX1-RV64-NEXT: vmulhu.vv v26, v26, v27
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v28 ; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v28
; LMULMAX1-RV64-NEXT: vmv.v.i v27, 3 ; LMULMAX1-RV64-NEXT: vmv.v.i v27, 3
; LMULMAX1-RV64-NEXT: addi a2, zero, 2 ; LMULMAX1-RV64-NEXT: addi a2, zero, 2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2 ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vsrl.vv v26, v26, v27 ; LMULMAX1-RV64-NEXT: vsrl.vv v26, v26, v27
; LMULMAX1-RV64-NEXT: vmv.v.i v27, 2 ; LMULMAX1-RV64-NEXT: vmv.v.i v27, 2
; LMULMAX1-RV64-NEXT: addi a2, zero, 1 ; LMULMAX1-RV64-NEXT: addi a2, zero, 1
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2 ; LMULMAX1-RV64-NEXT: vmv.s.x v27, a2
; LMULMAX1-RV64-NEXT: lui a2, 1035469 ; LMULMAX1-RV64-NEXT: lui a2, 1035469
; LMULMAX1-RV64-NEXT: addiw a2, a2, -819 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -819
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -819 ; LMULMAX1-RV64-NEXT: addi a2, a2, -819
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -819 ; LMULMAX1-RV64-NEXT: addi a2, a2, -819
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -819 ; LMULMAX1-RV64-NEXT: addi a2, a2, -819
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmv.v.x v28, a2 ; LMULMAX1-RV64-NEXT: vmv.v.x v28, a2
; LMULMAX1-RV64-NEXT: lui a2, 1026731 ; LMULMAX1-RV64-NEXT: lui a2, 1026731
; LMULMAX1-RV64-NEXT: addiw a2, a2, -1365 ; LMULMAX1-RV64-NEXT: addiw a2, a2, -1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -1365 ; LMULMAX1-RV64-NEXT: addi a2, a2, -1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -1365 ; LMULMAX1-RV64-NEXT: addi a2, a2, -1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, -1365 ; LMULMAX1-RV64-NEXT: addi a2, a2, -1365
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v28, a2 ; LMULMAX1-RV64-NEXT: vmv.s.x v28, a2
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmulhu.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vmulhu.vv v25, v25, v28
; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v27 ; LMULMAX1-RV64-NEXT: vsrl.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v26, (a1) ; LMULMAX1-RV64-NEXT: vse64.v v26, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9> %b = udiv <4 x i64> %a, <i64 3, i64 5, i64 7, i64 9>
store <4 x i64> %b, <4 x i64>* %x store <4 x i64> %b, <4 x i64>* %x
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; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v27 ; LMULMAX1-RV32-NEXT: vdiv.vv v25, v25, v27
; LMULMAX1-RV32-NEXT: vse64.v v25, (a0) ; LMULMAX1-RV32-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV32-NEXT: vse64.v v26, (a1) ; LMULMAX1-RV32-NEXT: vse64.v v26, (a1)
; LMULMAX1-RV32-NEXT: ret ; LMULMAX1-RV32-NEXT: ret
; ;
; LMULMAX1-RV64-LABEL: mulhs_v4i64: ; LMULMAX1-RV64-LABEL: mulhs_v4i64:
; LMULMAX1-RV64: # %bb.0: ; LMULMAX1-RV64: # %bb.0:
; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; LMULMAX1-RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vle64.v v25, (a0)
; LMULMAX1-RV64-NEXT: addi a1, a0, 16 ; LMULMAX1-RV64-NEXT: addi a1, a0, 16
; LMULMAX1-RV64-NEXT: vle64.v v25, (a1) ; LMULMAX1-RV64-NEXT: vle64.v v26, (a1)
; LMULMAX1-RV64-NEXT: vle64.v v26, (a0)
; LMULMAX1-RV64-NEXT: vmv.v.i v27, -1 ; LMULMAX1-RV64-NEXT: vmv.v.i v27, -1
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v27, zero ; LMULMAX1-RV64-NEXT: vmv.s.x v27, zero
; LMULMAX1-RV64-NEXT: vmul.vv v28, v25, v27 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vmul.vv v28, v26, v27
; LMULMAX1-RV64-NEXT: lui a2, 21845 ; LMULMAX1-RV64-NEXT: lui a2, 21845
; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365 ; LMULMAX1-RV64-NEXT: addiw a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, 1365 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a2, a2, 1365 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1365
; LMULMAX1-RV64-NEXT: slli a2, a2, 12 ; LMULMAX1-RV64-NEXT: slli a2, a2, 12
; LMULMAX1-RV64-NEXT: addi a3, a2, 1365 ; LMULMAX1-RV64-NEXT: addi a3, a2, 1365
; LMULMAX1-RV64-NEXT: vmv.v.x v29, a3 ; LMULMAX1-RV64-NEXT: vmv.v.x v29, a3
; LMULMAX1-RV64-NEXT: addi a2, a2, 1366 ; LMULMAX1-RV64-NEXT: addi a2, a2, 1366
; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-RV64-NEXT: vmv.s.x v29, a2 ; LMULMAX1-RV64-NEXT: vmv.s.x v29, a2
; LMULMAX1-RV64-NEXT: vmulh.vv v25, v25, v29 ; LMULMAX1-RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28 ; LMULMAX1-RV64-NEXT: vmulh.vv v26, v26, v29
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v28
; LMULMAX1-RV64-NEXT: addi a2, zero, 63 ; LMULMAX1-RV64-NEXT: addi a2, zero, 63
; LMULMAX1-RV64-NEXT: vsrl.vx v28, v25, a2 ; LMULMAX1-RV64-NEXT: vsrl.vx v28, v26, a2
; LMULMAX1-RV64-NEXT: vid.v v30 ; LMULMAX1-RV64-NEXT: vid.v v30
; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v30
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v28
; LMULMAX1-RV64-NEXT: vmul.vv v27, v26, v27
; LMULMAX1-RV64-NEXT: vmulh.vv v26, v26, v29
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27
; LMULMAX1-RV64-NEXT: vsrl.vx v27, v26, a2
; LMULMAX1-RV64-NEXT: vsra.vv v26, v26, v30 ; LMULMAX1-RV64-NEXT: vsra.vv v26, v26, v30
; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v27 ; LMULMAX1-RV64-NEXT: vadd.vv v26, v26, v28
; LMULMAX1-RV64-NEXT: vse64.v v26, (a0) ; LMULMAX1-RV64-NEXT: vmul.vv v27, v25, v27
; LMULMAX1-RV64-NEXT: vse64.v v25, (a1) ; LMULMAX1-RV64-NEXT: vmulh.vv v25, v25, v29
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vsrl.vx v27, v25, a2
; LMULMAX1-RV64-NEXT: vsra.vv v25, v25, v30
; LMULMAX1-RV64-NEXT: vadd.vv v25, v25, v27
; LMULMAX1-RV64-NEXT: vse64.v v25, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v26, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, <4 x i64>* %x %a = load <4 x i64>, <4 x i64>* %x
%b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3> %b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3>
store <4 x i64> %b, <4 x i64>* %x store <4 x i64> %b, <4 x i64>* %x
ret void ret void
} }
define void @smin_v32i8(<32 x i8>* %x, <32 x i8>* %y) { define void @smin_v32i8(<32 x i8>* %x, <32 x i8>* %y) {
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll

Show All 31 Lines; CHECK-NEXT: ret
ret <1 x i1> %1 ret <1 x i1> %1
} }
define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) { define <2 x i1> @buildvec_mask_nonconst_v2i1(i1 %x, i1 %y) {
; CHECK-LABEL: buildvec_mask_nonconst_v2i1: ; CHECK-LABEL: buildvec_mask_nonconst_v2i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e8,mf8,ta,mu ; CHECK-NEXT: vsetivli zero, 2, e8,mf8,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1 ; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,tu,mu
; CHECK-NEXT: vmv.s.x v25, a0 ; CHECK-NEXT: vmv.s.x v25, a0
; CHECK-NEXT: vsetvli zero, zero, e8,mf8,ta,mu
; CHECK-NEXT: vand.vi v25, v25, 1 ; CHECK-NEXT: vand.vi v25, v25, 1
; CHECK-NEXT: vmsne.vi v0, v25, 0 ; CHECK-NEXT: vmsne.vi v0, v25, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%1 = insertelement <2 x i1> undef, i1 %x, i32 0 %1 = insertelement <2 x i1> undef, i1 %x, i32 0
%2 = insertelement <2 x i1> %1, i1 %y, i32 1 %2 = insertelement <2 x i1> %1, i1 %y, i32 1
ret <2 x i1> %2 ret <2 x i1> %2
} }
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll

Show All 17 Lines
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: vsetivli zero, 1, e16,mf4,ta,mu ; CHECK-NEXT: vsetivli zero, 1, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 1 ; CHECK-NEXT: vslidedown.vi v25, v8, 1
; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: vfmv.f.s ft1, v25 ; CHECK-NEXT: vfmv.f.s ft1, v25
; CHECK-NEXT: vsetivli zero, 2, e16,mf4,ta,mu ; CHECK-NEXT: vsetivli zero, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.v.f v8, ft1 ; CHECK-NEXT: vfmv.v.f v8, ft1
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = select i1 %c, <2 x half> %a, <2 x half> %b %v = select i1 %c, <2 x half> %a, <2 x half> %b
ret <2 x half> %v ret <2 x half> %v
} }
define <2 x half> @selectcc_v2f16(half %a, half %b, <2 x half> %c, <2 x half> %d) { define <2 x half> @selectcc_v2f16(half %a, half %b, <2 x half> %c, <2 x half> %d) {
; CHECK-LABEL: selectcc_v2f16: ; CHECK-LABEL: selectcc_v2f16:
Show All 13 Lines
; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vfmv.v.f v25, ft0
; CHECK-NEXT: bnez a0, .LBB1_5 ; CHECK-NEXT: bnez a0, .LBB1_5
; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: # %bb.4:
; CHECK-NEXT: vfmv.f.s ft0, v9 ; CHECK-NEXT: vfmv.f.s ft0, v9
; CHECK-NEXT: j .LBB1_6 ; CHECK-NEXT: j .LBB1_6
; CHECK-NEXT: .LBB1_5: ; CHECK-NEXT: .LBB1_5:
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: .LBB1_6: ; CHECK-NEXT: .LBB1_6:
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu
; CHECK-NEXT: vfmv.s.f v25, ft0 ; CHECK-NEXT: vfmv.s.f v25, ft0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cmp = fcmp oeq half %a, %b %cmp = fcmp oeq half %a, %b
%v = select i1 %cmp, <2 x half> %c, <2 x half> %d %v = select i1 %cmp, <2 x half> %c, <2 x half> %d
ret <2 x half> %v ret <2 x half> %v
} }
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; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: vsetivli zero, 1, e32,mf2,ta,mu ; CHECK-NEXT: vsetivli zero, 1, e32,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 1 ; CHECK-NEXT: vslidedown.vi v25, v8, 1
; CHECK-NEXT: .LBB8_3: ; CHECK-NEXT: .LBB8_3:
; CHECK-NEXT: vfmv.f.s ft1, v25 ; CHECK-NEXT: vfmv.f.s ft1, v25
; CHECK-NEXT: vsetivli zero, 2, e32,mf2,ta,mu ; CHECK-NEXT: vsetivli zero, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfmv.v.f v8, ft1 ; CHECK-NEXT: vfmv.v.f v8, ft1
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = select i1 %c, <2 x float> %a, <2 x float> %b %v = select i1 %c, <2 x float> %a, <2 x float> %b
ret <2 x float> %v ret <2 x float> %v
} }
define <2 x float> @selectcc_v2f32(float %a, float %b, <2 x float> %c, <2 x float> %d) { define <2 x float> @selectcc_v2f32(float %a, float %b, <2 x float> %c, <2 x float> %d) {
; CHECK-LABEL: selectcc_v2f32: ; CHECK-LABEL: selectcc_v2f32:
Show All 13 Lines
; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vfmv.v.f v25, ft0
; CHECK-NEXT: bnez a0, .LBB9_5 ; CHECK-NEXT: bnez a0, .LBB9_5
; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: # %bb.4:
; CHECK-NEXT: vfmv.f.s ft0, v9 ; CHECK-NEXT: vfmv.f.s ft0, v9
; CHECK-NEXT: j .LBB9_6 ; CHECK-NEXT: j .LBB9_6
; CHECK-NEXT: .LBB9_5: ; CHECK-NEXT: .LBB9_5:
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: .LBB9_6: ; CHECK-NEXT: .LBB9_6:
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v25, ft0 ; CHECK-NEXT: vfmv.s.f v25, ft0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cmp = fcmp oeq float %a, %b %cmp = fcmp oeq float %a, %b
%v = select i1 %cmp, <2 x float> %c, <2 x float> %d %v = select i1 %cmp, <2 x float> %c, <2 x float> %d
ret <2 x float> %v ret <2 x float> %v
} }
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; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: vsetivli zero, 1, e64,m1,ta,mu ; CHECK-NEXT: vsetivli zero, 1, e64,m1,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v8, 1 ; CHECK-NEXT: vslidedown.vi v25, v8, 1
; CHECK-NEXT: .LBB16_3: ; CHECK-NEXT: .LBB16_3:
; CHECK-NEXT: vfmv.f.s ft1, v25 ; CHECK-NEXT: vfmv.f.s ft1, v25
; CHECK-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; CHECK-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v8, ft1 ; CHECK-NEXT: vfmv.v.f v8, ft1
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, ft0 ; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v = select i1 %c, <2 x double> %a, <2 x double> %b %v = select i1 %c, <2 x double> %a, <2 x double> %b
ret <2 x double> %v ret <2 x double> %v
} }
define <2 x double> @selectcc_v2f64(double %a, double %b, <2 x double> %c, <2 x double> %d) { define <2 x double> @selectcc_v2f64(double %a, double %b, <2 x double> %c, <2 x double> %d) {
; CHECK-LABEL: selectcc_v2f64: ; CHECK-LABEL: selectcc_v2f64:
Show All 13 Lines
; CHECK-NEXT: vfmv.v.f v25, ft0 ; CHECK-NEXT: vfmv.v.f v25, ft0
; CHECK-NEXT: bnez a0, .LBB17_5 ; CHECK-NEXT: bnez a0, .LBB17_5
; CHECK-NEXT: # %bb.4: ; CHECK-NEXT: # %bb.4:
; CHECK-NEXT: vfmv.f.s ft0, v9 ; CHECK-NEXT: vfmv.f.s ft0, v9
; CHECK-NEXT: j .LBB17_6 ; CHECK-NEXT: j .LBB17_6
; CHECK-NEXT: .LBB17_5: ; CHECK-NEXT: .LBB17_5:
; CHECK-NEXT: vfmv.f.s ft0, v8 ; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: .LBB17_6: ; CHECK-NEXT: .LBB17_6:
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v25, ft0 ; CHECK-NEXT: vfmv.s.f v25, ft0
; CHECK-NEXT: vmv1r.v v8, v25 ; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%cmp = fcmp oeq double %a, %b %cmp = fcmp oeq double %a, %b
%v = select i1 %cmp, <2 x double> %c, <2 x double> %d %v = select i1 %cmp, <2 x double> %c, <2 x double> %d
ret <2 x double> %v ret <2 x double> %v
} }
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll

Show First 20 Lines • Show All 196 Lines • ▼ Show 20 Lines
declare <4 x i64> @llvm.experimental.stepvector.v4i64() declare <4 x i64> @llvm.experimental.stepvector.v4i64()
define <4 x i64> @stepvector_v4i64() { define <4 x i64> @stepvector_v4i64() {
; LMULMAX1-LABEL: stepvector_v4i64: ; LMULMAX1-LABEL: stepvector_v4i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; LMULMAX1-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v9, 3 ; LMULMAX1-NEXT: vmv.v.i v9, 3
; LMULMAX1-NEXT: addi a0, zero, 2 ; LMULMAX1-NEXT: addi a0, zero, 2
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v9, a0 ; LMULMAX1-NEXT: vmv.s.x v9, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vid.v v8 ; LMULMAX1-NEXT: vid.v v8
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX2-LABEL: stepvector_v4i64: ; LMULMAX2-LABEL: stepvector_v4i64:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: vsetivli zero, 4, e64,m2,ta,mu ; LMULMAX2-NEXT: vsetivli zero, 4, e64,m2,ta,mu
; LMULMAX2-NEXT: vid.v v8 ; LMULMAX2-NEXT: vid.v v8
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
%v = call <4 x i64> @llvm.experimental.stepvector.v4i64() %v = call <4 x i64> @llvm.experimental.stepvector.v4i64()
ret <4 x i64> %v ret <4 x i64> %v
} }
declare <8 x i64> @llvm.experimental.stepvector.v8i64() declare <8 x i64> @llvm.experimental.stepvector.v8i64()
define <8 x i64> @stepvector_v8i64() { define <8 x i64> @stepvector_v8i64() {
; LMULMAX1-LABEL: stepvector_v8i64: ; LMULMAX1-LABEL: stepvector_v8i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; LMULMAX1-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v9, 3 ; LMULMAX1-NEXT: vmv.v.i v9, 3
; LMULMAX1-NEXT: addi a0, zero, 2 ; LMULMAX1-NEXT: addi a0, zero, 2
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v9, a0 ; LMULMAX1-NEXT: vmv.s.x v9, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v10, 5 ; LMULMAX1-NEXT: vmv.v.i v10, 5
; LMULMAX1-NEXT: addi a0, zero, 4 ; LMULMAX1-NEXT: addi a0, zero, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v10, a0 ; LMULMAX1-NEXT: vmv.s.x v10, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v11, 7 ; LMULMAX1-NEXT: vmv.v.i v11, 7
; LMULMAX1-NEXT: addi a0, zero, 6 ; LMULMAX1-NEXT: addi a0, zero, 6
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v11, a0 ; LMULMAX1-NEXT: vmv.s.x v11, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vid.v v8 ; LMULMAX1-NEXT: vid.v v8
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX2-LABEL: stepvector_v8i64: ; LMULMAX2-LABEL: stepvector_v8i64:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: lui a0, %hi(.LCPI14_0) ; LMULMAX2-NEXT: lui a0, %hi(.LCPI14_0)
; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI14_0) ; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI14_0)
; LMULMAX2-NEXT: vsetivli zero, 4, e64,m2,ta,mu ; LMULMAX2-NEXT: vsetivli zero, 4, e64,m2,ta,mu
; LMULMAX2-NEXT: vle64.v v10, (a0) ; LMULMAX2-NEXT: vle64.v v10, (a0)
; LMULMAX2-NEXT: vid.v v8 ; LMULMAX2-NEXT: vid.v v8
; LMULMAX2-NEXT: ret ; LMULMAX2-NEXT: ret
%v = call <8 x i64> @llvm.experimental.stepvector.v8i64() %v = call <8 x i64> @llvm.experimental.stepvector.v8i64()
ret <8 x i64> %v ret <8 x i64> %v
} }
declare <16 x i64> @llvm.experimental.stepvector.v16i64() declare <16 x i64> @llvm.experimental.stepvector.v16i64()
define <16 x i64> @stepvector_v16i64() { define <16 x i64> @stepvector_v16i64() {
; LMULMAX1-LABEL: stepvector_v16i64: ; LMULMAX1-LABEL: stepvector_v16i64:
; LMULMAX1: # %bb.0: ; LMULMAX1: # %bb.0:
; LMULMAX1-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; LMULMAX1-NEXT: vsetivli zero, 2, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v9, 3 ; LMULMAX1-NEXT: vmv.v.i v9, 3
; LMULMAX1-NEXT: addi a0, zero, 2 ; LMULMAX1-NEXT: addi a0, zero, 2
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v9, a0 ; LMULMAX1-NEXT: vmv.s.x v9, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v10, 5 ; LMULMAX1-NEXT: vmv.v.i v10, 5
; LMULMAX1-NEXT: addi a0, zero, 4 ; LMULMAX1-NEXT: addi a0, zero, 4
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v10, a0 ; LMULMAX1-NEXT: vmv.s.x v10, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v11, 7 ; LMULMAX1-NEXT: vmv.v.i v11, 7
; LMULMAX1-NEXT: addi a0, zero, 6 ; LMULMAX1-NEXT: addi a0, zero, 6
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v11, a0 ; LMULMAX1-NEXT: vmv.s.x v11, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v12, 9 ; LMULMAX1-NEXT: vmv.v.i v12, 9
; LMULMAX1-NEXT: addi a0, zero, 8 ; LMULMAX1-NEXT: addi a0, zero, 8
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v12, a0 ; LMULMAX1-NEXT: vmv.s.x v12, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v13, 11 ; LMULMAX1-NEXT: vmv.v.i v13, 11
; LMULMAX1-NEXT: addi a0, zero, 10 ; LMULMAX1-NEXT: addi a0, zero, 10
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v13, a0 ; LMULMAX1-NEXT: vmv.s.x v13, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v14, 13 ; LMULMAX1-NEXT: vmv.v.i v14, 13
; LMULMAX1-NEXT: addi a0, zero, 12 ; LMULMAX1-NEXT: addi a0, zero, 12
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v14, a0 ; LMULMAX1-NEXT: vmv.s.x v14, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vmv.v.i v15, 15 ; LMULMAX1-NEXT: vmv.v.i v15, 15
; LMULMAX1-NEXT: addi a0, zero, 14 ; LMULMAX1-NEXT: addi a0, zero, 14
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; LMULMAX1-NEXT: vmv.s.x v15, a0 ; LMULMAX1-NEXT: vmv.s.x v15, a0
; LMULMAX1-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; LMULMAX1-NEXT: vid.v v8 ; LMULMAX1-NEXT: vid.v v8
; LMULMAX1-NEXT: ret ; LMULMAX1-NEXT: ret
; ;
; LMULMAX2-LABEL: stepvector_v16i64: ; LMULMAX2-LABEL: stepvector_v16i64:
; LMULMAX2: # %bb.0: ; LMULMAX2: # %bb.0:
; LMULMAX2-NEXT: lui a0, %hi(.LCPI15_0) ; LMULMAX2-NEXT: lui a0, %hi(.LCPI15_0)
; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI15_0) ; LMULMAX2-NEXT: addi a0, a0, %lo(.LCPI15_0)
; LMULMAX2-NEXT: vsetivli zero, 4, e64,m2,ta,mu ; LMULMAX2-NEXT: vsetivli zero, 4, e64,m2,ta,mu
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll

Show First 20 Lines • Show All 350 Lines • ▼ Show 20 Lines
; RV32-NEXT: beqz a1, .LBB4_2 ; RV32-NEXT: beqz a1, .LBB4_2
; RV32-NEXT: # %bb.1: # %cond.load ; RV32-NEXT: # %bb.1: # %cond.load
; RV32-NEXT: vsetvli zero, zero, e32,mf2,ta,mu ; RV32-NEXT: vsetvli zero, zero, e32,mf2,ta,mu
; RV32-NEXT: vmv.x.s a1, v8 ; RV32-NEXT: vmv.x.s a1, v8
; RV32-NEXT: lb a2, 1(a1) ; RV32-NEXT: lb a2, 1(a1)
; RV32-NEXT: lbu a1, 0(a1) ; RV32-NEXT: lbu a1, 0(a1)
; RV32-NEXT: slli a2, a2, 8 ; RV32-NEXT: slli a2, a2, 8
; RV32-NEXT: or a1, a2, a1 ; RV32-NEXT: or a1, a2, a1
; RV32-NEXT: vsetivli zero, 2, e16,mf4,ta,mu ; RV32-NEXT: vsetivli zero, 2, e16,mf4,tu,mu
; RV32-NEXT: vmv.s.x v9, a1 ; RV32-NEXT: vmv.s.x v9, a1
; RV32-NEXT: .LBB4_2: # %else ; RV32-NEXT: .LBB4_2: # %else
; RV32-NEXT: andi a0, a0, 2 ; RV32-NEXT: andi a0, a0, 2
; RV32-NEXT: beqz a0, .LBB4_4 ; RV32-NEXT: beqz a0, .LBB4_4
; RV32-NEXT: # %bb.3: # %cond.load1 ; RV32-NEXT: # %bb.3: # %cond.load1
; RV32-NEXT: vsetivli zero, 1, e32,mf2,ta,mu ; RV32-NEXT: vsetivli zero, 1, e32,mf2,ta,mu
; RV32-NEXT: vslidedown.vi v25, v8, 1 ; RV32-NEXT: vslidedown.vi v25, v8, 1
; RV32-NEXT: vmv.x.s a0, v25 ; RV32-NEXT: vmv.x.s a0, v25
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; RV64-NEXT: beqz a1, .LBB4_2 ; RV64-NEXT: beqz a1, .LBB4_2
; RV64-NEXT: # %bb.1: # %cond.load ; RV64-NEXT: # %bb.1: # %cond.load
; RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; RV64-NEXT: vmv.x.s a1, v8 ; RV64-NEXT: vmv.x.s a1, v8
; RV64-NEXT: lb a2, 1(a1) ; RV64-NEXT: lb a2, 1(a1)
; RV64-NEXT: lbu a1, 0(a1) ; RV64-NEXT: lbu a1, 0(a1)
; RV64-NEXT: slli a2, a2, 8 ; RV64-NEXT: slli a2, a2, 8
; RV64-NEXT: or a1, a2, a1 ; RV64-NEXT: or a1, a2, a1
; RV64-NEXT: vsetivli zero, 2, e16,mf4,ta,mu ; RV64-NEXT: vsetivli zero, 2, e16,mf4,tu,mu
; RV64-NEXT: vmv.s.x v9, a1 ; RV64-NEXT: vmv.s.x v9, a1
; RV64-NEXT: .LBB4_2: # %else ; RV64-NEXT: .LBB4_2: # %else
; RV64-NEXT: andi a0, a0, 2 ; RV64-NEXT: andi a0, a0, 2
; RV64-NEXT: beqz a0, .LBB4_4 ; RV64-NEXT: beqz a0, .LBB4_4
; RV64-NEXT: # %bb.3: # %cond.load1 ; RV64-NEXT: # %bb.3: # %cond.load1
; RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu ; RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu
; RV64-NEXT: vslidedown.vi v25, v8, 1 ; RV64-NEXT: vslidedown.vi v25, v8, 1
; RV64-NEXT: vmv.x.s a0, v25 ; RV64-NEXT: vmv.x.s a0, v25
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; RV64-NEXT: beqz a1, .LBB5_2 ; RV64-NEXT: beqz a1, .LBB5_2
; RV64-NEXT: # %bb.1: # %cond.load ; RV64-NEXT: # %bb.1: # %cond.load
; RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu ; RV64-NEXT: vsetvli zero, zero, e64,m1,ta,mu
; RV64-NEXT: vmv.x.s a1, v8 ; RV64-NEXT: vmv.x.s a1, v8
; RV64-NEXT: lwu a2, 4(a1) ; RV64-NEXT: lwu a2, 4(a1)
; RV64-NEXT: lwu a1, 0(a1) ; RV64-NEXT: lwu a1, 0(a1)
; RV64-NEXT: slli a2, a2, 32 ; RV64-NEXT: slli a2, a2, 32
; RV64-NEXT: or a1, a2, a1 ; RV64-NEXT: or a1, a2, a1
; RV64-NEXT: vsetivli zero, 2, e64,m1,ta,mu ; RV64-NEXT: vsetivli zero, 2, e64,m1,tu,mu
; RV64-NEXT: vmv.s.x v9, a1 ; RV64-NEXT: vmv.s.x v9, a1
; RV64-NEXT: .LBB5_2: # %else ; RV64-NEXT: .LBB5_2: # %else
; RV64-NEXT: andi a0, a0, 2 ; RV64-NEXT: andi a0, a0, 2
; RV64-NEXT: beqz a0, .LBB5_4 ; RV64-NEXT: beqz a0, .LBB5_4
; RV64-NEXT: # %bb.3: # %cond.load1 ; RV64-NEXT: # %bb.3: # %cond.load1
; RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu ; RV64-NEXT: vsetivli zero, 1, e64,m1,ta,mu
; RV64-NEXT: vslidedown.vi v25, v8, 1 ; RV64-NEXT: vslidedown.vi v25, v8, 1
; RV64-NEXT: vmv.x.s a0, v25 ; RV64-NEXT: vmv.x.s a0, v25
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llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_0: ; CHECK-LABEL: insertelt_nxv1f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 1 x half> %v, half %elt, i32 0
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_imm: ; CHECK-LABEL: insertelt_nxv1f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_0: ; CHECK-LABEL: insertelt_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 0
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_imm: ; CHECK-LABEL: insertelt_nxv2f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_0: ; CHECK-LABEL: insertelt_nxv4f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 0
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_imm: ; CHECK-LABEL: insertelt_nxv4f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_0: ; CHECK-LABEL: insertelt_nxv8f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 0
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_imm: ; CHECK-LABEL: insertelt_nxv8f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_0: ; CHECK-LABEL: insertelt_nxv16f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 0
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_imm: ; CHECK-LABEL: insertelt_nxv16f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_0: ; CHECK-LABEL: insertelt_nxv32f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 0
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_imm: ; CHECK-LABEL: insertelt_nxv32f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) { define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv1f32_0: ; CHECK-LABEL: insertelt_nxv1f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 1 x float> %v, float %elt, i32 0
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) { define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv1f32_imm: ; CHECK-LABEL: insertelt_nxv1f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) { define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv2f32_0: ; CHECK-LABEL: insertelt_nxv2f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 2 x float> %v, float %elt, i32 0
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) { define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv2f32_imm: ; CHECK-LABEL: insertelt_nxv2f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) { define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv4f32_0: ; CHECK-LABEL: insertelt_nxv4f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 4 x float> %v, float %elt, i32 0
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) { define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv4f32_imm: ; CHECK-LABEL: insertelt_nxv4f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) { define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv8f32_0: ; CHECK-LABEL: insertelt_nxv8f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 8 x float> %v, float %elt, i32 0
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) { define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv8f32_imm: ; CHECK-LABEL: insertelt_nxv8f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) { define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv16f32_0: ; CHECK-LABEL: insertelt_nxv16f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 16 x float> %v, float %elt, i32 0
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) { define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv16f32_imm: ; CHECK-LABEL: insertelt_nxv16f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) { define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv1f64_0: ; CHECK-LABEL: insertelt_nxv1f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 1 x double> %v, double %elt, i32 0
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) { define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv1f64_imm: ; CHECK-LABEL: insertelt_nxv1f64_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) { define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv2f64_0: ; CHECK-LABEL: insertelt_nxv2f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 2 x double> %v, double %elt, i32 0
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) { define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv2f64_imm: ; CHECK-LABEL: insertelt_nxv2f64_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) { define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv4f64_0: ; CHECK-LABEL: insertelt_nxv4f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 4 x double> %v, double %elt, i32 0
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) { define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv4f64_imm: ; CHECK-LABEL: insertelt_nxv4f64_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) { define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv8f64_0: ; CHECK-LABEL: insertelt_nxv8f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 8 x double> %v, double %elt, i32 0
ret <vscale x 8 x double> %r ret <vscale x 8 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) { define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv8f64_imm: ; CHECK-LABEL: insertelt_nxv8f64_imm:
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llvm/test/CodeGen/RISCV/rvv/insertelt-fp-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_0(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_0: ; CHECK-LABEL: insertelt_nxv1f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 1 x half> %v, half %elt, i32 0
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) { define <vscale x 1 x half> @insertelt_nxv1f16_imm(<vscale x 1 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv1f16_imm: ; CHECK-LABEL: insertelt_nxv1f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 1 x half> %v, half %elt, i32 %idx
ret <vscale x 1 x half> %r ret <vscale x 1 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_0(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_0: ; CHECK-LABEL: insertelt_nxv2f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 2 x half> %v, half %elt, i32 0
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) { define <vscale x 2 x half> @insertelt_nxv2f16_imm(<vscale x 2 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv2f16_imm: ; CHECK-LABEL: insertelt_nxv2f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 2 x half> %v, half %elt, i32 %idx
ret <vscale x 2 x half> %r ret <vscale x 2 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_0(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_0: ; CHECK-LABEL: insertelt_nxv4f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 4 x half> %v, half %elt, i32 0
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) { define <vscale x 4 x half> @insertelt_nxv4f16_imm(<vscale x 4 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv4f16_imm: ; CHECK-LABEL: insertelt_nxv4f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 4 x half> %v, half %elt, i32 %idx
ret <vscale x 4 x half> %r ret <vscale x 4 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_0(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_0: ; CHECK-LABEL: insertelt_nxv8f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 8 x half> %v, half %elt, i32 0
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) { define <vscale x 8 x half> @insertelt_nxv8f16_imm(<vscale x 8 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv8f16_imm: ; CHECK-LABEL: insertelt_nxv8f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 8 x half> %v, half %elt, i32 %idx
ret <vscale x 8 x half> %r ret <vscale x 8 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_0(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_0: ; CHECK-LABEL: insertelt_nxv16f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 16 x half> %v, half %elt, i32 0
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) { define <vscale x 16 x half> @insertelt_nxv16f16_imm(<vscale x 16 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv16f16_imm: ; CHECK-LABEL: insertelt_nxv16f16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 16 x half> %v, half %elt, i32 %idx
ret <vscale x 16 x half> %r ret <vscale x 16 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_0(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_0: ; CHECK-LABEL: insertelt_nxv32f16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e16,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 0 %r = insertelement <vscale x 32 x half> %v, half %elt, i32 0
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) { define <vscale x 32 x half> @insertelt_nxv32f16_imm(<vscale x 32 x half> %v, half %elt) {
; CHECK-LABEL: insertelt_nxv32f16_imm: ; CHECK-LABEL: insertelt_nxv32f16_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx %r = insertelement <vscale x 32 x half> %v, half %elt, i32 %idx
ret <vscale x 32 x half> %r ret <vscale x 32 x half> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) { define <vscale x 1 x float> @insertelt_nxv1f32_0(<vscale x 1 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv1f32_0: ; CHECK-LABEL: insertelt_nxv1f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 1 x float> %v, float %elt, i32 0
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) { define <vscale x 1 x float> @insertelt_nxv1f32_imm(<vscale x 1 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv1f32_imm: ; CHECK-LABEL: insertelt_nxv1f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 1 x float> %v, float %elt, i32 %idx
ret <vscale x 1 x float> %r ret <vscale x 1 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) { define <vscale x 2 x float> @insertelt_nxv2f32_0(<vscale x 2 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv2f32_0: ; CHECK-LABEL: insertelt_nxv2f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 2 x float> %v, float %elt, i32 0
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) { define <vscale x 2 x float> @insertelt_nxv2f32_imm(<vscale x 2 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv2f32_imm: ; CHECK-LABEL: insertelt_nxv2f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 2 x float> %v, float %elt, i32 %idx
ret <vscale x 2 x float> %r ret <vscale x 2 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) { define <vscale x 4 x float> @insertelt_nxv4f32_0(<vscale x 4 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv4f32_0: ; CHECK-LABEL: insertelt_nxv4f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 4 x float> %v, float %elt, i32 0
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) { define <vscale x 4 x float> @insertelt_nxv4f32_imm(<vscale x 4 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv4f32_imm: ; CHECK-LABEL: insertelt_nxv4f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 4 x float> %v, float %elt, i32 %idx
ret <vscale x 4 x float> %r ret <vscale x 4 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) { define <vscale x 8 x float> @insertelt_nxv8f32_0(<vscale x 8 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv8f32_0: ; CHECK-LABEL: insertelt_nxv8f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 8 x float> %v, float %elt, i32 0
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) { define <vscale x 8 x float> @insertelt_nxv8f32_imm(<vscale x 8 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv8f32_imm: ; CHECK-LABEL: insertelt_nxv8f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 8 x float> %v, float %elt, i32 %idx
ret <vscale x 8 x float> %r ret <vscale x 8 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) { define <vscale x 16 x float> @insertelt_nxv16f32_0(<vscale x 16 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv16f32_0: ; CHECK-LABEL: insertelt_nxv16f32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e32,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 0 %r = insertelement <vscale x 16 x float> %v, float %elt, i32 0
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) { define <vscale x 16 x float> @insertelt_nxv16f32_imm(<vscale x 16 x float> %v, float %elt) {
; CHECK-LABEL: insertelt_nxv16f32_imm: ; CHECK-LABEL: insertelt_nxv16f32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx %r = insertelement <vscale x 16 x float> %v, float %elt, i32 %idx
ret <vscale x 16 x float> %r ret <vscale x 16 x float> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) { define <vscale x 1 x double> @insertelt_nxv1f64_0(<vscale x 1 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv1f64_0: ; CHECK-LABEL: insertelt_nxv1f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 1 x double> %v, double %elt, i32 0
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) { define <vscale x 1 x double> @insertelt_nxv1f64_imm(<vscale x 1 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv1f64_imm: ; CHECK-LABEL: insertelt_nxv1f64_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 1 x double> %v, double %elt, i32 %idx
ret <vscale x 1 x double> %r ret <vscale x 1 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) { define <vscale x 2 x double> @insertelt_nxv2f64_0(<vscale x 2 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv2f64_0: ; CHECK-LABEL: insertelt_nxv2f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 2 x double> %v, double %elt, i32 0
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) { define <vscale x 2 x double> @insertelt_nxv2f64_imm(<vscale x 2 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv2f64_imm: ; CHECK-LABEL: insertelt_nxv2f64_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 2 x double> %v, double %elt, i32 %idx
ret <vscale x 2 x double> %r ret <vscale x 2 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) { define <vscale x 4 x double> @insertelt_nxv4f64_0(<vscale x 4 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv4f64_0: ; CHECK-LABEL: insertelt_nxv4f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 4 x double> %v, double %elt, i32 0
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) { define <vscale x 4 x double> @insertelt_nxv4f64_imm(<vscale x 4 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv4f64_imm: ; CHECK-LABEL: insertelt_nxv4f64_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx %r = insertelement <vscale x 4 x double> %v, double %elt, i32 %idx
ret <vscale x 4 x double> %r ret <vscale x 4 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) { define <vscale x 8 x double> @insertelt_nxv8f64_0(<vscale x 8 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv8f64_0: ; CHECK-LABEL: insertelt_nxv8f64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a0, zero, e64,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x double> %v, double %elt, i32 0 %r = insertelement <vscale x 8 x double> %v, double %elt, i32 0
ret <vscale x 8 x double> %r ret <vscale x 8 x double> %r
} }
define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) { define <vscale x 8 x double> @insertelt_nxv8f64_imm(<vscale x 8 x double> %v, double %elt) {
; CHECK-LABEL: insertelt_nxv8f64_imm: ; CHECK-LABEL: insertelt_nxv8f64_imm:
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llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) { define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i8_0: ; CHECK-LABEL: insertelt_nxv1i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 0
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) { define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i8_imm: ; CHECK-LABEL: insertelt_nxv1i8_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_0: ; CHECK-LABEL: insertelt_nxv2i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_imm: ; CHECK-LABEL: insertelt_nxv2i8_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_0: ; CHECK-LABEL: insertelt_nxv4i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_imm: ; CHECK-LABEL: insertelt_nxv4i8_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_0: ; CHECK-LABEL: insertelt_nxv8i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_imm: ; CHECK-LABEL: insertelt_nxv8i8_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_0: ; CHECK-LABEL: insertelt_nxv16i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_imm: ; CHECK-LABEL: insertelt_nxv16i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) { define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i8_0: ; CHECK-LABEL: insertelt_nxv32i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) { define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i8_imm: ; CHECK-LABEL: insertelt_nxv32i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) { define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv64i8_0: ; CHECK-LABEL: insertelt_nxv64i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) { define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv64i8_imm: ; CHECK-LABEL: insertelt_nxv64i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) { define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i16_0: ; CHECK-LABEL: insertelt_nxv1i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) { define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i16_imm: ; CHECK-LABEL: insertelt_nxv1i16_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_0: ; CHECK-LABEL: insertelt_nxv2i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_imm: ; CHECK-LABEL: insertelt_nxv2i16_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_0: ; CHECK-LABEL: insertelt_nxv4i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_imm: ; CHECK-LABEL: insertelt_nxv4i16_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_0: ; CHECK-LABEL: insertelt_nxv8i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_imm: ; CHECK-LABEL: insertelt_nxv8i16_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) { define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i16_0: ; CHECK-LABEL: insertelt_nxv16i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) { define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i16_imm: ; CHECK-LABEL: insertelt_nxv16i16_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) { define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i16_0: ; CHECK-LABEL: insertelt_nxv32i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) { define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i16_imm: ; CHECK-LABEL: insertelt_nxv32i16_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 %elt) { define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv1i32_0: ; CHECK-LABEL: insertelt_nxv1i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 %elt) { define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv1i32_imm: ; CHECK-LABEL: insertelt_nxv1i32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv2i32_0: ; CHECK-LABEL: insertelt_nxv2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv2i32_imm: ; CHECK-LABEL: insertelt_nxv2i32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv4i32_0: ; CHECK-LABEL: insertelt_nxv4i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv4i32_imm: ; CHECK-LABEL: insertelt_nxv4i32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 %elt) { define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv8i32_0: ; CHECK-LABEL: insertelt_nxv8i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 %elt) { define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv8i32_imm: ; CHECK-LABEL: insertelt_nxv8i32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 %elt) { define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv16i32_0: ; CHECK-LABEL: insertelt_nxv16i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0
ret <vscale x 16 x i32> %r ret <vscale x 16 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 %elt) { define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 %elt) {
; CHECK-LABEL: insertelt_nxv16i32_imm: ; CHECK-LABEL: insertelt_nxv16i32_imm:
▲ Show 20 Lines • Show All 192 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <vscale x 8 x i64> %r ret <vscale x 8 x i64> %r
} }
; Extra tests to check lowering of constant values ; Extra tests to check lowering of constant values
define <vscale x 2 x i64> @insertelt_nxv2i64_0_c10(<vscale x 2 x i64> %v) { define <vscale x 2 x i64> @insertelt_nxv2i64_0_c10(<vscale x 2 x i64> %v) {
; CHECK-LABEL: insertelt_nxv2i64_0_c10: ; CHECK-LABEL: insertelt_nxv2i64_0_c10:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, 10 ; CHECK-NEXT: addi a0, zero, 10
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 10, i32 0 %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 0
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_imm_c10(<vscale x 2 x i64> %v) { define <vscale x 2 x i64> @insertelt_nxv2i64_imm_c10(<vscale x 2 x i64> %v) {
; CHECK-LABEL: insertelt_nxv2i64_imm_c10: ; CHECK-LABEL: insertelt_nxv2i64_imm_c10:
Show All 21 Lines; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 10, i32 %idx %r = insertelement <vscale x 2 x i64> %v, i64 10, i32 %idx
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_0_cn1(<vscale x 2 x i64> %v) { define <vscale x 2 x i64> @insertelt_nxv2i64_0_cn1(<vscale x 2 x i64> %v) {
; CHECK-LABEL: insertelt_nxv2i64_0_cn1: ; CHECK-LABEL: insertelt_nxv2i64_0_cn1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi a0, zero, -1 ; CHECK-NEXT: addi a0, zero, -1
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 0 %r = insertelement <vscale x 2 x i64> %v, i64 -1, i32 0
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_imm_cn1(<vscale x 2 x i64> %v) { define <vscale x 2 x i64> @insertelt_nxv2i64_imm_cn1(<vscale x 2 x i64> %v) {
; CHECK-LABEL: insertelt_nxv2i64_imm_cn1: ; CHECK-LABEL: insertelt_nxv2i64_imm_cn1:
Show All 24 Lines

llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-zfh,+experimental-v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) { define <vscale x 1 x i8> @insertelt_nxv1i8_0(<vscale x 1 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i8_0: ; CHECK-LABEL: insertelt_nxv1i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,mf8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 0
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) { define <vscale x 1 x i8> @insertelt_nxv1i8_imm(<vscale x 1 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i8_imm: ; CHECK-LABEL: insertelt_nxv1i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 1 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 1 x i8> %r ret <vscale x 1 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_0(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_0: ; CHECK-LABEL: insertelt_nxv2i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,mf4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 0
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) { define <vscale x 2 x i8> @insertelt_nxv2i8_imm(<vscale x 2 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i8_imm: ; CHECK-LABEL: insertelt_nxv2i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 2 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 2 x i8> %r ret <vscale x 2 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_0(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_0: ; CHECK-LABEL: insertelt_nxv4i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 0
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) { define <vscale x 4 x i8> @insertelt_nxv4i8_imm(<vscale x 4 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i8_imm: ; CHECK-LABEL: insertelt_nxv4i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 4 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 4 x i8> %r ret <vscale x 4 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_0(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_0: ; CHECK-LABEL: insertelt_nxv8i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 0
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) { define <vscale x 8 x i8> @insertelt_nxv8i8_imm(<vscale x 8 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i8_imm: ; CHECK-LABEL: insertelt_nxv8i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 8 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 8 x i8> %r ret <vscale x 8 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_0(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_0: ; CHECK-LABEL: insertelt_nxv16i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 0
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) { define <vscale x 16 x i8> @insertelt_nxv16i8_imm(<vscale x 16 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i8_imm: ; CHECK-LABEL: insertelt_nxv16i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 16 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 16 x i8> %r ret <vscale x 16 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) { define <vscale x 32 x i8> @insertelt_nxv32i8_0(<vscale x 32 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i8_0: ; CHECK-LABEL: insertelt_nxv32i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 0
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) { define <vscale x 32 x i8> @insertelt_nxv32i8_imm(<vscale x 32 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i8_imm: ; CHECK-LABEL: insertelt_nxv32i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 32 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 32 x i8> %r ret <vscale x 32 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) { define <vscale x 64 x i8> @insertelt_nxv64i8_0(<vscale x 64 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv64i8_0: ; CHECK-LABEL: insertelt_nxv64i8_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e8,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0 %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 0
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) { define <vscale x 64 x i8> @insertelt_nxv64i8_imm(<vscale x 64 x i8> %v, i8 signext %elt) {
; CHECK-LABEL: insertelt_nxv64i8_imm: ; CHECK-LABEL: insertelt_nxv64i8_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx %r = insertelement <vscale x 64 x i8> %v, i8 %elt, i32 %idx
ret <vscale x 64 x i8> %r ret <vscale x 64 x i8> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) { define <vscale x 1 x i16> @insertelt_nxv1i16_0(<vscale x 1 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i16_0: ; CHECK-LABEL: insertelt_nxv1i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 0
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) { define <vscale x 1 x i16> @insertelt_nxv1i16_imm(<vscale x 1 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i16_imm: ; CHECK-LABEL: insertelt_nxv1i16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 1 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 1 x i16> %r ret <vscale x 1 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_0(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_0: ; CHECK-LABEL: insertelt_nxv2i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 0
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) { define <vscale x 2 x i16> @insertelt_nxv2i16_imm(<vscale x 2 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i16_imm: ; CHECK-LABEL: insertelt_nxv2i16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 2 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 2 x i16> %r ret <vscale x 2 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_0(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_0: ; CHECK-LABEL: insertelt_nxv4i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 0
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) { define <vscale x 4 x i16> @insertelt_nxv4i16_imm(<vscale x 4 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i16_imm: ; CHECK-LABEL: insertelt_nxv4i16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 4 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 4 x i16> %r ret <vscale x 4 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_0(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_0: ; CHECK-LABEL: insertelt_nxv8i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 0
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) { define <vscale x 8 x i16> @insertelt_nxv8i16_imm(<vscale x 8 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i16_imm: ; CHECK-LABEL: insertelt_nxv8i16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 8 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 8 x i16> %r ret <vscale x 8 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) { define <vscale x 16 x i16> @insertelt_nxv16i16_0(<vscale x 16 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i16_0: ; CHECK-LABEL: insertelt_nxv16i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 0
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) { define <vscale x 16 x i16> @insertelt_nxv16i16_imm(<vscale x 16 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i16_imm: ; CHECK-LABEL: insertelt_nxv16i16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 16 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 16 x i16> %r ret <vscale x 16 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) { define <vscale x 32 x i16> @insertelt_nxv32i16_0(<vscale x 32 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i16_0: ; CHECK-LABEL: insertelt_nxv32i16_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e16,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0 %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 0
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) { define <vscale x 32 x i16> @insertelt_nxv32i16_imm(<vscale x 32 x i16> %v, i16 signext %elt) {
; CHECK-LABEL: insertelt_nxv32i16_imm: ; CHECK-LABEL: insertelt_nxv32i16_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx %r = insertelement <vscale x 32 x i16> %v, i16 %elt, i32 %idx
ret <vscale x 32 x i16> %r ret <vscale x 32 x i16> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 signext %elt) { define <vscale x 1 x i32> @insertelt_nxv1i32_0(<vscale x 1 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i32_0: ; CHECK-LABEL: insertelt_nxv1i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 0
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 signext %elt) { define <vscale x 1 x i32> @insertelt_nxv1i32_imm(<vscale x 1 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv1i32_imm: ; CHECK-LABEL: insertelt_nxv1i32_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 1 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 1 x i32> %r ret <vscale x 1 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 signext %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_0(<vscale x 2 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i32_0: ; CHECK-LABEL: insertelt_nxv2i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 0
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 signext %elt) { define <vscale x 2 x i32> @insertelt_nxv2i32_imm(<vscale x 2 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv2i32_imm: ; CHECK-LABEL: insertelt_nxv2i32_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 2 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 2 x i32> %r ret <vscale x 2 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 signext %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_0(<vscale x 4 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i32_0: ; CHECK-LABEL: insertelt_nxv4i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 0
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 signext %elt) { define <vscale x 4 x i32> @insertelt_nxv4i32_imm(<vscale x 4 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv4i32_imm: ; CHECK-LABEL: insertelt_nxv4i32_imm:
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 4 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 4 x i32> %r ret <vscale x 4 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 signext %elt) { define <vscale x 8 x i32> @insertelt_nxv8i32_0(<vscale x 8 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i32_0: ; CHECK-LABEL: insertelt_nxv8i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 0
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 signext %elt) { define <vscale x 8 x i32> @insertelt_nxv8i32_imm(<vscale x 8 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv8i32_imm: ; CHECK-LABEL: insertelt_nxv8i32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 8 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 8 x i32> %r ret <vscale x 8 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 signext %elt) { define <vscale x 16 x i32> @insertelt_nxv16i32_0(<vscale x 16 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i32_0: ; CHECK-LABEL: insertelt_nxv16i32_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e32,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e32,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0 %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 0
ret <vscale x 16 x i32> %r ret <vscale x 16 x i32> %r
} }
define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 signext %elt) { define <vscale x 16 x i32> @insertelt_nxv16i32_imm(<vscale x 16 x i32> %v, i32 signext %elt) {
; CHECK-LABEL: insertelt_nxv16i32_imm: ; CHECK-LABEL: insertelt_nxv16i32_imm:
Show All 18 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx %r = insertelement <vscale x 16 x i32> %v, i32 %elt, i32 %idx
ret <vscale x 16 x i32> %r ret <vscale x 16 x i32> %r
} }
define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) { define <vscale x 1 x i64> @insertelt_nxv1i64_0(<vscale x 1 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv1i64_0: ; CHECK-LABEL: insertelt_nxv1i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m1,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 0
ret <vscale x 1 x i64> %r ret <vscale x 1 x i64> %r
} }
define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) { define <vscale x 1 x i64> @insertelt_nxv1i64_imm(<vscale x 1 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv1i64_imm: ; CHECK-LABEL: insertelt_nxv1i64_imm:
Show All 19 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 1 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 1 x i64> %r ret <vscale x 1 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) { define <vscale x 2 x i64> @insertelt_nxv2i64_0(<vscale x 2 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv2i64_0: ; CHECK-LABEL: insertelt_nxv2i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m2,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 0
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) { define <vscale x 2 x i64> @insertelt_nxv2i64_imm(<vscale x 2 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv2i64_imm: ; CHECK-LABEL: insertelt_nxv2i64_imm:
Show All 19 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 2 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 2 x i64> %r ret <vscale x 2 x i64> %r
} }
define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) { define <vscale x 4 x i64> @insertelt_nxv4i64_0(<vscale x 4 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv4i64_0: ; CHECK-LABEL: insertelt_nxv4i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m4,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 0
ret <vscale x 4 x i64> %r ret <vscale x 4 x i64> %r
} }
define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) { define <vscale x 4 x i64> @insertelt_nxv4i64_imm(<vscale x 4 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv4i64_imm: ; CHECK-LABEL: insertelt_nxv4i64_imm:
Show All 19 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx %r = insertelement <vscale x 4 x i64> %v, i64 %elt, i32 %idx
ret <vscale x 4 x i64> %r ret <vscale x 4 x i64> %r
} }
define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) { define <vscale x 8 x i64> @insertelt_nxv8i64_0(<vscale x 8 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv8i64_0: ; CHECK-LABEL: insertelt_nxv8i64_0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64,m8,ta,mu ; CHECK-NEXT: vsetvli a1, zero, e64,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0 %r = insertelement <vscale x 8 x i64> %v, i64 %elt, i32 0
ret <vscale x 8 x i64> %r ret <vscale x 8 x i64> %r
} }
define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) { define <vscale x 8 x i64> @insertelt_nxv8i64_imm(<vscale x 8 x i64> %v, i64 %elt) {
; CHECK-LABEL: insertelt_nxv8i64_imm: ; CHECK-LABEL: insertelt_nxv8i64_imm:
Show All 24 Lines

llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-v,+experimental-zfh -target-abi ilp32d -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv32 -mattr=+d,+experimental-v,+experimental-zfh -target-abi ilp32d -verify-machineinstrs < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half>, half, i32) declare <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half>, half, i32)
define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(<vscale x 1 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> %0, half %1, i32 %2) %a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> %0, half %1, i32 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half>, half, i32) declare <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half>, half, i32)
define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_nxv2f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind { define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_nxv2f16(<vscale x 2 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half> %0, half %1, i32 %2) %a = call <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half> %0, half %1, i32 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half>, half, i32) declare <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half>, half, i32)
define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_nxv4f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind { define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_nxv4f16(<vscale x 4 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half> %0, half %1, i32 %2) %a = call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half> %0, half %1, i32 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half>, half, i32) declare <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half>, half, i32)
define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind { define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half> %0, half %1, i32 %2) %a = call <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half> %0, half %1, i32 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half>, half, i32) declare <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half>, half, i32)
define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind { define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half> %0, half %1, i32 %2) %a = call <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half> %0, half %1, i32 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half>, half, i32) declare <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half>, half, i32)
define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind { define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half> %0, half %1, i32 %2) %a = call <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half> %0, half %1, i32 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float>, float, i32) declare <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float>, float, i32)
define <vscale x 1 x float> @intrinsic_vfmv.s.f_f_nxv1f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfmv.s.f_f_nxv1f32(<vscale x 1 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float> %0, float %1, i32 %2) %a = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float> %0, float %1, i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float>, float, i32) declare <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float>, float, i32)
define <vscale x 2 x float> @intrinsic_vfmv.s.f_f_nxv2f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vfmv.s.f_f_nxv2f32(<vscale x 2 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float> %0, float %1, i32 %2) %a = call <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float> %0, float %1, i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float>, float, i32) declare <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float>, float, i32)
define <vscale x 4 x float> @intrinsic_vfmv.s.f_f_nxv4f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vfmv.s.f_f_nxv4f32(<vscale x 4 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float> %0, float %1, i32 %2) %a = call <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float> %0, float %1, i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float>, float, i32) declare <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float>, float, i32)
define <vscale x 8 x float> @intrinsic_vfmv.s.f_f_nxv8f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vfmv.s.f_f_nxv8f32(<vscale x 8 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float> %0, float %1, i32 %2) %a = call <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float> %0, float %1, i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float>, float, i32) declare <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float>, float, i32)
define <vscale x 16 x float> @intrinsic_vfmv.s.f_f_nxv16f32(<vscale x 16 x float> %0, float %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vfmv.s.f_f_nxv16f32(<vscale x 16 x float> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float> %0, float %1, i32 %2) %a = call <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float> %0, float %1, i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double>, double, i32) declare <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double>, double, i32)
define <vscale x 1 x double> @intrinsic_vfmv.s.f_f_nxv1f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vfmv.s.f_f_nxv1f64(<vscale x 1 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f64: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double> %0, double %1, i32 %2) %a = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double> %0, double %1, i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double>, double, i32) declare <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double>, double, i32)
define <vscale x 2 x double> @intrinsic_vfmv.s.f_f_nxv2f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vfmv.s.f_f_nxv2f64(<vscale x 2 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f64: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double> %0, double %1, i32 %2) %a = call <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double> %0, double %1, i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double>, double, i32) declare <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double>, double, i32)
define <vscale x 4 x double> @intrinsic_vfmv.s.f_f_nxv4f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vfmv.s.f_f_nxv4f64(<vscale x 4 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f64: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double> %0, double %1, i32 %2) %a = call <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double> %0, double %1, i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double>, double, i32) declare <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double>, double, i32)
define <vscale x 8 x double> @intrinsic_vfmv.s.f_f_nxv8f64(<vscale x 8 x double> %0, double %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vfmv.s.f_f_nxv8f64(<vscale x 8 x double> %0, double %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f64: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> %0, double %1, i32 %2) %a = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> %0, double %1, i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfmv.s.f-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-v,+experimental-zfh -target-abi lp64d -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+d,+experimental-v,+experimental-zfh -target-abi lp64d -verify-machineinstrs < %s | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half>, half, i64) declare <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half>, half, i64)
define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind { define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_nxv1f16(<vscale x 1 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> %0, half %1, i64 %2) %a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> %0, half %1, i64 %2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half>, half, i64) declare <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half>, half, i64)
define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_nxv2f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind { define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_nxv2f16(<vscale x 2 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half> %0, half %1, i64 %2) %a = call <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half> %0, half %1, i64 %2)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half>, half, i64) declare <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half>, half, i64)
define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_nxv4f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind { define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_nxv4f16(<vscale x 4 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half> %0, half %1, i64 %2) %a = call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half> %0, half %1, i64 %2)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half>, half, i64) declare <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half>, half, i64)
define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind { define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_nxv8f16(<vscale x 8 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half> %0, half %1, i64 %2) %a = call <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half> %0, half %1, i64 %2)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half>, half, i64) declare <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half>, half, i64)
define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind { define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_nxv16f16(<vscale x 16 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half> %0, half %1, i64 %2) %a = call <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half> %0, half %1, i64 %2)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half>, half, i64) declare <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half>, half, i64)
define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind { define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_nxv32f16(<vscale x 32 x half> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv32f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half> %0, half %1, i64 %2) %a = call <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half> %0, half %1, i64 %2)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float>, float, i64) declare <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float>, float, i64)
define <vscale x 1 x float> @intrinsic_vfmv.s.f_f_nxv1f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfmv.s.f_f_nxv1f32(<vscale x 1 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float> %0, float %1, i64 %2) %a = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float> %0, float %1, i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float>, float, i64) declare <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float>, float, i64)
define <vscale x 2 x float> @intrinsic_vfmv.s.f_f_nxv2f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vfmv.s.f_f_nxv2f32(<vscale x 2 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float> %0, float %1, i64 %2) %a = call <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float> %0, float %1, i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float>, float, i64) declare <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float>, float, i64)
define <vscale x 4 x float> @intrinsic_vfmv.s.f_f_nxv4f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vfmv.s.f_f_nxv4f32(<vscale x 4 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float> %0, float %1, i64 %2) %a = call <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float> %0, float %1, i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float>, float, i64) declare <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float>, float, i64)
define <vscale x 8 x float> @intrinsic_vfmv.s.f_f_nxv8f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vfmv.s.f_f_nxv8f32(<vscale x 8 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float> %0, float %1, i64 %2) %a = call <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float> %0, float %1, i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float>, float, i64) declare <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float>, float, i64)
define <vscale x 16 x float> @intrinsic_vfmv.s.f_f_nxv16f32(<vscale x 16 x float> %0, float %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vfmv.s.f_f_nxv16f32(<vscale x 16 x float> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f32: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv16f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float> %0, float %1, i64 %2) %a = call <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float> %0, float %1, i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double>, double, i64) declare <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double>, double, i64)
define <vscale x 1 x double> @intrinsic_vfmv.s.f_f_nxv1f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vfmv.s.f_f_nxv1f64(<vscale x 1 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f64: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double> %0, double %1, i64 %2) %a = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double> %0, double %1, i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double>, double, i64) declare <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double>, double, i64)
define <vscale x 2 x double> @intrinsic_vfmv.s.f_f_nxv2f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vfmv.s.f_f_nxv2f64(<vscale x 2 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f64: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double> %0, double %1, i64 %2) %a = call <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double> %0, double %1, i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double>, double, i64) declare <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double>, double, i64)
define <vscale x 4 x double> @intrinsic_vfmv.s.f_f_nxv4f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vfmv.s.f_f_nxv4f64(<vscale x 4 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f64: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double> %0, double %1, i64 %2) %a = call <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double> %0, double %1, i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double>, double, i64) declare <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double>, double, i64)
define <vscale x 8 x double> @intrinsic_vfmv.s.f_f_nxv8f64(<vscale x 8 x double> %0, double %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vfmv.s.f_f_nxv8f64(<vscale x 8 x double> %0, double %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f64: ; CHECK-LABEL: intrinsic_vfmv.s.f_f_nxv8f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfmv.s.f v8, fa0 ; CHECK-NEXT: vfmv.s.f v8, fa0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> %0, double %1, i64 %2) %a = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> %0, double %1, i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16.nxv1i1( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16.nxv1i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16.nxv2i1( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16.nxv2i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16.nxv4i1( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16.nxv4i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9 ; CHECK-NEXT: vfredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16.nxv8i1( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16.nxv8i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9 ; CHECK-NEXT: vfredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16.nxv16i1( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16.nxv16i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9 ; CHECK-NEXT: vfredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.nxv32i1( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.nxv32i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.nxv1i1( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.nxv1i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.nxv2i1( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.nxv2i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9 ; CHECK-NEXT: vfredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.nxv4i1( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.nxv4i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9 ; CHECK-NEXT: vfredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.nxv8i1( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.nxv8i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9 ; CHECK-NEXT: vfredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.nxv16i1( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.nxv16i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.nxv16i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32.nxv16i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64.nxv1i1( declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64.nxv1i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9 ; CHECK-NEXT: vfredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64.nxv2i1( declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64.nxv2i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9 ; CHECK-NEXT: vfredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64.nxv4i1( declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64.nxv4i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9 ; CHECK-NEXT: vfredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.nxv8i1( declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.nxv8i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9 ; CHECK-NEXT: vfredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9 ; CHECK-NEXT: vfredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9 ; CHECK-NEXT: vfredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmax.mask.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9 ; CHECK-NEXT: vfredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9 ; CHECK-NEXT: vfredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9 ; CHECK-NEXT: vfredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmax.mask.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10 ; CHECK-NEXT: vfredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9 ; CHECK-NEXT: vfredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9 ; CHECK-NEXT: vfredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9 ; CHECK-NEXT: vfredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmax_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmax.mask.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16.nxv1i1( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16.nxv1i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16.nxv2i1( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16.nxv2i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16.nxv4i1( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16.nxv4i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9 ; CHECK-NEXT: vfredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16.nxv8i1( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16.nxv8i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9 ; CHECK-NEXT: vfredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16.nxv16i1( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16.nxv16i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9 ; CHECK-NEXT: vfredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.nxv32i1( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.nxv32i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.nxv1i1( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.nxv1i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32.nxv2i1( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32.nxv2i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9 ; CHECK-NEXT: vfredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32.nxv4i1( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32.nxv4i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9 ; CHECK-NEXT: vfredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32.nxv8i1( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32.nxv8i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9 ; CHECK-NEXT: vfredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32.nxv16i1( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32.nxv16i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32.nxv16i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32.nxv16i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64.nxv1i1( declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64.nxv1i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9 ; CHECK-NEXT: vfredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64.nxv2i1( declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64.nxv2i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9 ; CHECK-NEXT: vfredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64.nxv4i1( declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64.nxv4i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9 ; CHECK-NEXT: vfredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64.nxv8i1( declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64.nxv8i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9 ; CHECK-NEXT: vfredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9 ; CHECK-NEXT: vfredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9 ; CHECK-NEXT: vfredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredmin.mask.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9 ; CHECK-NEXT: vfredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9 ; CHECK-NEXT: vfredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9 ; CHECK-NEXT: vfredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredmin.mask.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10 ; CHECK-NEXT: vfredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9 ; CHECK-NEXT: vfredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9 ; CHECK-NEXT: vfredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9 ; CHECK-NEXT: vfredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredmin_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredmin.mask.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9 ; CHECK-NEXT: vfredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9 ; CHECK-NEXT: vfredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9 ; CHECK-NEXT: vfredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9 ; CHECK-NEXT: vfredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9 ; CHECK-NEXT: vfredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9 ; CHECK-NEXT: vfredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1( declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9 ; CHECK-NEXT: vfredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1( declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9 ; CHECK-NEXT: vfredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1( declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9 ; CHECK-NEXT: vfredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1( declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9 ; CHECK-NEXT: vfredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9 ; CHECK-NEXT: vfredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9 ; CHECK-NEXT: vfredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9 ; CHECK-NEXT: vfredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9 ; CHECK-NEXT: vfredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9 ; CHECK-NEXT: vfredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10 ; CHECK-NEXT: vfredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9 ; CHECK-NEXT: vfredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9 ; CHECK-NEXT: vfredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9 ; CHECK-NEXT: vfredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16.nxv1i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16.nxv2i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16.nxv4i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9 ; CHECK-NEXT: vfredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16.nxv8i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9 ; CHECK-NEXT: vfredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16.nxv16i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9 ; CHECK-NEXT: vfredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i32 %3) i32 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16.nxv32i1(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32.nxv1i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32.nxv2i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9 ; CHECK-NEXT: vfredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32.nxv4i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9 ; CHECK-NEXT: vfredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32.nxv8i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9 ; CHECK-NEXT: vfredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32.nxv16i1(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.nxv1i1( declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.nxv1i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64.nxv1i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9 ; CHECK-NEXT: vfredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.nxv2i1( declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.nxv2i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64.nxv2i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9 ; CHECK-NEXT: vfredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.nxv4i1( declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.nxv4i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64.nxv4i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9 ; CHECK-NEXT: vfredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.nxv8i1( declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.nxv8i1( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64.nxv8i1(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 1 x half> %1, <vscale x 4 x half> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv1f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv1f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 2 x half> %1, <vscale x 4 x half> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv2f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv2f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9 ; CHECK-NEXT: vfredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 8 x half> %1, <vscale x 4 x half> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv8f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv8f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9 ; CHECK-NEXT: vfredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 16 x half> %1, <vscale x 4 x half> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv16f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv16f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9 ; CHECK-NEXT: vfredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
i64 %3) i64 %3)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16( declare <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x half> @intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 32 x half> %1, <vscale x 4 x half> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv4f16_nxv32f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16( %a = call <vscale x 4 x half> @llvm.riscv.vfredsum.mask.nxv4f16.nxv32f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x float> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv1f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv1f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9 ; CHECK-NEXT: vfredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x float> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv4f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv4f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9 ; CHECK-NEXT: vfredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x float> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv8f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv8f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9 ; CHECK-NEXT: vfredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32( declare <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x float> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv2f32_nxv16f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32( %a = call <vscale x 2 x float> @llvm.riscv.vfredsum.mask.nxv2f32.nxv16f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10 ; CHECK-NEXT: vfredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9 ; CHECK-NEXT: vfredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x double> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv2f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv2f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9 ; CHECK-NEXT: vfredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x double> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv4f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv4f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9 ; CHECK-NEXT: vfredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64( declare <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x double>, <vscale x 8 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x double> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfredsum_mask_vs_nxv1f64_nxv8f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64( %a = call <vscale x 1 x double> @llvm.riscv.vfredsum.mask.nxv1f64.nxv8f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x double> %1, <vscale x 8 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v10, v9 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v12, v9 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v16, v9 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v10, v9 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v12, v9 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v16, v9 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfwredosum-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv1f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv2f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv4f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v10, v9 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv8f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v12, v9 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv16f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v16, v9 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.nxv2f32.nxv32f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( declare <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv1f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv2f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v10, v9 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv4f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v12, v9 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv8f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v16, v9 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.nxv1f64.nxv16f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32( declare <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv1f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv1f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv2f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv4f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv4f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv8f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v10, v9 ; CHECK-NEXT: vfwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv8f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv16f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v12, v9 ; CHECK-NEXT: vfwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv16f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v16, v9 ; CHECK-NEXT: vfwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i32 %3) i32 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v10, v9 ; CHECK-NEXT: vfwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v12, v9 ; CHECK-NEXT: vfwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v16, v9 ; CHECK-NEXT: vfwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i32 %3) i32 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfwredsum-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v,+d,+experimental-zfh -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv1f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv1f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv1f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 1 x half> %1, <vscale x 2 x float> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv1f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv1f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv2f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv2f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv2f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x half> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv2f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv2f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv4f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv4f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv4f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 4 x half> %1, <vscale x 2 x float> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv4f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv4f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv8f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v10, v9 ; CHECK-NEXT: vfwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv8f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv8f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 8 x half> %1, <vscale x 2 x float> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv8f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv8f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv16f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v12, v9 ; CHECK-NEXT: vfwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv16f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv16f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 16 x half> %1, <vscale x 2 x float> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv16f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv16f16.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v16, v9 ; CHECK-NEXT: vfwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.nxv2f32.nxv32f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
i64 %3) i64 %3)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( declare <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x half>, <vscale x 32 x half>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 2 x float> @intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32(<vscale x 2 x float> %0, <vscale x 32 x half> %1, <vscale x 2 x float> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv2f32_nxv32f16_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwredsum.mask.nxv2f32.nxv32f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 32 x half> %1, <vscale x 32 x half> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv1f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x float> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv1f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv1f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10 ; CHECK-NEXT: vfwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv2f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 2 x float> %1, <vscale x 1 x double> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv2f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv2f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v10, v9 ; CHECK-NEXT: vfwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv4f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 4 x float> %1, <vscale x 1 x double> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv4f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv4f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v12, v9 ; CHECK-NEXT: vfwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv8f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 8 x float> %1, <vscale x 1 x double> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv8f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv8f32.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v16, v9 ; CHECK-NEXT: vfwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.nxv1f64.nxv16f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
i64 %3) i64 %3)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32( declare <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x float>, <vscale x 16 x float>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 1 x double> @intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64(<vscale x 1 x double> %0, <vscale x 16 x float> %1, <vscale x 1 x double> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK-LABEL: intrinsic_vfwredsum_mask_vs_nxv1f64_nxv16f32_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vfwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwredsum.mask.nxv1f64.nxv16f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 16 x float> %1, <vscale x 16 x float> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8>, i8, i32) declare <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8>, i8, i32)
define <vscale x 1 x i8> @intrinsic_vmv.s.x_x_nxv1i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vmv.s.x_x_nxv1i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8> %0, i8 %1, i32 %2) %a = call <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8> %0, i8 %1, i32 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8(<vscale x 2 x i8>, i8, i32) declare <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8(<vscale x 2 x i8>, i8, i32)
define <vscale x 2 x i8> @intrinsic_vmv.s.x_x_nxv2i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vmv.s.x_x_nxv2i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8(<vscale x 2 x i8> %0, i8 %1, i32 %2) %a = call <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8(<vscale x 2 x i8> %0, i8 %1, i32 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8(<vscale x 4 x i8>, i8, i32) declare <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8(<vscale x 4 x i8>, i8, i32)
define <vscale x 4 x i8> @intrinsic_vmv.s.x_x_nxv4i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vmv.s.x_x_nxv4i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8(<vscale x 4 x i8> %0, i8 %1, i32 %2) %a = call <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8(<vscale x 4 x i8> %0, i8 %1, i32 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8(<vscale x 8 x i8>, i8, i32) declare <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8(<vscale x 8 x i8>, i8, i32)
define <vscale x 8 x i8> @intrinsic_vmv.s.x_x_nxv8i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vmv.s.x_x_nxv8i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8(<vscale x 8 x i8> %0, i8 %1, i32 %2) %a = call <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8(<vscale x 8 x i8> %0, i8 %1, i32 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8>, i8, i32) declare <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8>, i8, i32)
define <vscale x 16 x i8> @intrinsic_vmv.s.x_x_nxv16i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vmv.s.x_x_nxv16i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8> %0, i8 %1, i32 %2) %a = call <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8> %0, i8 %1, i32 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8>, i8, i32) declare <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8>, i8, i32)
define <vscale x 32 x i8> @intrinsic_vmv.s.x_x_nxv32i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vmv.s.x_x_nxv32i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8> %0, i8 %1, i32 %2) %a = call <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8> %0, i8 %1, i32 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8>, i8, i32) declare <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8>, i8, i32)
define <vscale x 64 x i8> @intrinsic_vmv.s.x_x_nxv64i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vmv.s.x_x_nxv64i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv64i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8> %0, i8 %1, i32 %2) %a = call <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8> %0, i8 %1, i32 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16(<vscale x 1 x i16>, i16, i32) declare <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16(<vscale x 1 x i16>, i16, i32)
define <vscale x 1 x i16> @intrinsic_vmv.s.x_x_nxv1i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vmv.s.x_x_nxv1i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16(<vscale x 1 x i16> %0, i16 %1, i32 %2) %a = call <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16(<vscale x 1 x i16> %0, i16 %1, i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16(<vscale x 2 x i16>, i16, i32) declare <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16(<vscale x 2 x i16>, i16, i32)
define <vscale x 2 x i16> @intrinsic_vmv.s.x_x_nxv2i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vmv.s.x_x_nxv2i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16(<vscale x 2 x i16> %0, i16 %1, i32 %2) %a = call <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16(<vscale x 2 x i16> %0, i16 %1, i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16(<vscale x 4 x i16>, i16, i32) declare <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16(<vscale x 4 x i16>, i16, i32)
define <vscale x 4 x i16> @intrinsic_vmv.s.x_x_nxv4i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vmv.s.x_x_nxv4i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16(<vscale x 4 x i16> %0, i16 %1, i32 %2) %a = call <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16(<vscale x 4 x i16> %0, i16 %1, i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16>, i16, i32) declare <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16>, i16, i32)
define <vscale x 8 x i16> @intrinsic_vmv.s.x_x_nxv8i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vmv.s.x_x_nxv8i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16> %0, i16 %1, i32 %2) %a = call <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16> %0, i16 %1, i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16>, i16, i32) declare <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16>, i16, i32)
define <vscale x 16 x i16> @intrinsic_vmv.s.x_x_nxv16i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vmv.s.x_x_nxv16i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16> %0, i16 %1, i32 %2) %a = call <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16> %0, i16 %1, i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16>, i16, i32) declare <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16>, i16, i32)
define <vscale x 32 x i16> @intrinsic_vmv.s.x_x_nxv32i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vmv.s.x_x_nxv32i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16> %0, i16 %1, i32 %2) %a = call <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16> %0, i16 %1, i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32(<vscale x 1 x i32>, i32, i32) declare <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32(<vscale x 1 x i32>, i32, i32)
define <vscale x 1 x i32> @intrinsic_vmv.s.x_x_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vmv.s.x_x_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2) %a = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32(<vscale x 1 x i32> %0, i32 %1, i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32(<vscale x 2 x i32>, i32, i32) declare <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32(<vscale x 2 x i32>, i32, i32)
define <vscale x 2 x i32> @intrinsic_vmv.s.x_x_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vmv.s.x_x_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2) %a = call <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32(<vscale x 2 x i32> %0, i32 %1, i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32>, i32, i32) declare <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32>, i32, i32)
define <vscale x 4 x i32> @intrinsic_vmv.s.x_x_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vmv.s.x_x_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2) %a = call <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32> %0, i32 %1, i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32>, i32, i32) declare <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32>, i32, i32)
define <vscale x 8 x i32> @intrinsic_vmv.s.x_x_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vmv.s.x_x_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2) %a = call <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32> %0, i32 %1, i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32>, i32, i32) declare <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32>, i32, i32)
define <vscale x 16 x i32> @intrinsic_vmv.s.x_x_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vmv.s.x_x_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2) %a = call <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32> %0, i32 %1, i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, i32); declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, i32);
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llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
declare <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8>, i8, i64); declare <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8>, i8, i64);
define <vscale x 1 x i8> @intrinsic_vmv.s.x_x_nxv1i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i8> @intrinsic_vmv.s.x_x_nxv1i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8> %0, i8 %1, i64 %2) %a = call <vscale x 1 x i8> @llvm.riscv.vmv.s.x.nxv1i8(<vscale x 1 x i8> %0, i8 %1, i64 %2)
ret <vscale x 1 x i8> %a ret <vscale x 1 x i8> %a
} }
declare <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8(<vscale x 2 x i8>, i8, i64); declare <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8(<vscale x 2 x i8>, i8, i64);
define <vscale x 2 x i8> @intrinsic_vmv.s.x_x_nxv2i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i8> @intrinsic_vmv.s.x_x_nxv2i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8(<vscale x 2 x i8> %0, i8 %1, i64 %2) %a = call <vscale x 2 x i8> @llvm.riscv.vmv.s.x.nxv2i8(<vscale x 2 x i8> %0, i8 %1, i64 %2)
ret <vscale x 2 x i8> %a ret <vscale x 2 x i8> %a
} }
declare <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8(<vscale x 4 x i8>, i8, i64); declare <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8(<vscale x 4 x i8>, i8, i64);
define <vscale x 4 x i8> @intrinsic_vmv.s.x_x_nxv4i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i8> @intrinsic_vmv.s.x_x_nxv4i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8(<vscale x 4 x i8> %0, i8 %1, i64 %2) %a = call <vscale x 4 x i8> @llvm.riscv.vmv.s.x.nxv4i8(<vscale x 4 x i8> %0, i8 %1, i64 %2)
ret <vscale x 4 x i8> %a ret <vscale x 4 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8(<vscale x 8 x i8>, i8, i64); declare <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8(<vscale x 8 x i8>, i8, i64);
define <vscale x 8 x i8> @intrinsic_vmv.s.x_x_nxv8i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i8> @intrinsic_vmv.s.x_x_nxv8i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8(<vscale x 8 x i8> %0, i8 %1, i64 %2) %a = call <vscale x 8 x i8> @llvm.riscv.vmv.s.x.nxv8i8(<vscale x 8 x i8> %0, i8 %1, i64 %2)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8>, i8, i64); declare <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8>, i8, i64);
define <vscale x 16 x i8> @intrinsic_vmv.s.x_x_nxv16i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i8> @intrinsic_vmv.s.x_x_nxv16i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8> %0, i8 %1, i64 %2) %a = call <vscale x 16 x i8> @llvm.riscv.vmv.s.x.nxv16i8(<vscale x 16 x i8> %0, i8 %1, i64 %2)
ret <vscale x 16 x i8> %a ret <vscale x 16 x i8> %a
} }
declare <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8>, i8, i64); declare <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8>, i8, i64);
define <vscale x 32 x i8> @intrinsic_vmv.s.x_x_nxv32i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i8> @intrinsic_vmv.s.x_x_nxv32i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8> %0, i8 %1, i64 %2) %a = call <vscale x 32 x i8> @llvm.riscv.vmv.s.x.nxv32i8(<vscale x 32 x i8> %0, i8 %1, i64 %2)
ret <vscale x 32 x i8> %a ret <vscale x 32 x i8> %a
} }
declare <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8>, i8, i64); declare <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8>, i8, i64);
define <vscale x 64 x i8> @intrinsic_vmv.s.x_x_nxv64i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind { define <vscale x 64 x i8> @intrinsic_vmv.s.x_x_nxv64i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv64i8: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv64i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e8,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8> %0, i8 %1, i64 %2) %a = call <vscale x 64 x i8> @llvm.riscv.vmv.s.x.nxv64i8(<vscale x 64 x i8> %0, i8 %1, i64 %2)
ret <vscale x 64 x i8> %a ret <vscale x 64 x i8> %a
} }
declare <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16(<vscale x 1 x i16>, i16, i64); declare <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16(<vscale x 1 x i16>, i16, i64);
define <vscale x 1 x i16> @intrinsic_vmv.s.x_x_nxv1i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vmv.s.x_x_nxv1i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16(<vscale x 1 x i16> %0, i16 %1, i64 %2) %a = call <vscale x 1 x i16> @llvm.riscv.vmv.s.x.nxv1i16(<vscale x 1 x i16> %0, i16 %1, i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
} }
declare <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16(<vscale x 2 x i16>, i16, i64); declare <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16(<vscale x 2 x i16>, i16, i64);
define <vscale x 2 x i16> @intrinsic_vmv.s.x_x_nxv2i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vmv.s.x_x_nxv2i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16(<vscale x 2 x i16> %0, i16 %1, i64 %2) %a = call <vscale x 2 x i16> @llvm.riscv.vmv.s.x.nxv2i16(<vscale x 2 x i16> %0, i16 %1, i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16(<vscale x 4 x i16>, i16, i64); declare <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16(<vscale x 4 x i16>, i16, i64);
define <vscale x 4 x i16> @intrinsic_vmv.s.x_x_nxv4i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vmv.s.x_x_nxv4i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16(<vscale x 4 x i16> %0, i16 %1, i64 %2) %a = call <vscale x 4 x i16> @llvm.riscv.vmv.s.x.nxv4i16(<vscale x 4 x i16> %0, i16 %1, i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16>, i16, i64); declare <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16>, i16, i64);
define <vscale x 8 x i16> @intrinsic_vmv.s.x_x_nxv8i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vmv.s.x_x_nxv8i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16> %0, i16 %1, i64 %2) %a = call <vscale x 8 x i16> @llvm.riscv.vmv.s.x.nxv8i16(<vscale x 8 x i16> %0, i16 %1, i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
} }
declare <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16>, i16, i64); declare <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16>, i16, i64);
define <vscale x 16 x i16> @intrinsic_vmv.s.x_x_nxv16i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vmv.s.x_x_nxv16i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16> %0, i16 %1, i64 %2) %a = call <vscale x 16 x i16> @llvm.riscv.vmv.s.x.nxv16i16(<vscale x 16 x i16> %0, i16 %1, i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
} }
declare <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16>, i16, i64); declare <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16>, i16, i64);
define <vscale x 32 x i16> @intrinsic_vmv.s.x_x_nxv32i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vmv.s.x_x_nxv32i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i16: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv32i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e16,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16> %0, i16 %1, i64 %2) %a = call <vscale x 32 x i16> @llvm.riscv.vmv.s.x.nxv32i16(<vscale x 32 x i16> %0, i16 %1, i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
} }
declare <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32(<vscale x 1 x i32>, i32, i64); declare <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32(<vscale x 1 x i32>, i32, i64);
define <vscale x 1 x i32> @intrinsic_vmv.s.x_x_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vmv.s.x_x_nxv1i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32(<vscale x 1 x i32> %0, i32 %1, i64 %2) %a = call <vscale x 1 x i32> @llvm.riscv.vmv.s.x.nxv1i32(<vscale x 1 x i32> %0, i32 %1, i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32(<vscale x 2 x i32>, i32, i64); declare <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32(<vscale x 2 x i32>, i32, i64);
define <vscale x 2 x i32> @intrinsic_vmv.s.x_x_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vmv.s.x_x_nxv2i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32(<vscale x 2 x i32> %0, i32 %1, i64 %2) %a = call <vscale x 2 x i32> @llvm.riscv.vmv.s.x.nxv2i32(<vscale x 2 x i32> %0, i32 %1, i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32>, i32, i64); declare <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32>, i32, i64);
define <vscale x 4 x i32> @intrinsic_vmv.s.x_x_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vmv.s.x_x_nxv4i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32> %0, i32 %1, i64 %2) %a = call <vscale x 4 x i32> @llvm.riscv.vmv.s.x.nxv4i32(<vscale x 4 x i32> %0, i32 %1, i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
} }
declare <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32>, i32, i64); declare <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32>, i32, i64);
define <vscale x 8 x i32> @intrinsic_vmv.s.x_x_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vmv.s.x_x_nxv8i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32> %0, i32 %1, i64 %2) %a = call <vscale x 8 x i32> @llvm.riscv.vmv.s.x.nxv8i32(<vscale x 8 x i32> %0, i32 %1, i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
} }
declare <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32>, i32, i64); declare <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32>, i32, i64);
define <vscale x 16 x i32> @intrinsic_vmv.s.x_x_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vmv.s.x_x_nxv16i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv16i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e32,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32> %0, i32 %1, i64 %2) %a = call <vscale x 16 x i32> @llvm.riscv.vmv.s.x.nxv16i32(<vscale x 16 x i32> %0, i32 %1, i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, i64); declare <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64>, i64, i64);
define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vmv.s.x_x_nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2) %a = call <vscale x 1 x i64> @llvm.riscv.vmv.s.x.nxv1i64(<vscale x 1 x i64> %0, i64 %1, i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64>, i64, i64); declare <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64>, i64, i64);
define <vscale x 2 x i64> @intrinsic_vmv.s.x_x_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vmv.s.x_x_nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i64: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv2i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2) %a = call <vscale x 2 x i64> @llvm.riscv.vmv.s.x.nxv2i64(<vscale x 2 x i64> %0, i64 %1, i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
} }
declare <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64>, i64, i64); declare <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64>, i64, i64);
define <vscale x 4 x i64> @intrinsic_vmv.s.x_x_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vmv.s.x_x_nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i64: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv4i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2) %a = call <vscale x 4 x i64> @llvm.riscv.vmv.s.x.nxv4i64(<vscale x 4 x i64> %0, i64 %1, i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
} }
declare <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64>, i64, i64); declare <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64>, i64, i64);
define <vscale x 8 x i64> @intrinsic_vmv.s.x_x_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vmv.s.x_x_nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i64: ; CHECK-LABEL: intrinsic_vmv.s.x_x_nxv8i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a1, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a1, e64,m8,tu,mu
; CHECK-NEXT: vmv.s.x v8, a0 ; CHECK-NEXT: vmv.s.x v8, a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2) %a = call <vscale x 8 x i64> @llvm.riscv.vmv.s.x.nxv8i64(<vscale x 8 x i64> %0, i64 %1, i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9 ; CHECK-NEXT: vredand.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9 ; CHECK-NEXT: vredand.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9 ; CHECK-NEXT: vredand.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9 ; CHECK-NEXT: vredand.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9 ; CHECK-NEXT: vredand.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9 ; CHECK-NEXT: vredand.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9 ; CHECK-NEXT: vredand.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9 ; CHECK-NEXT: vredand.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9 ; CHECK-NEXT: vredand.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9 ; CHECK-NEXT: vredand.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9 ; CHECK-NEXT: vredand.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9 ; CHECK-NEXT: vredand.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9 ; CHECK-NEXT: vredand.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredand.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9 ; CHECK-NEXT: vredand.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9 ; CHECK-NEXT: vredand.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9 ; CHECK-NEXT: vredand.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredand.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9 ; CHECK-NEXT: vredand.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9 ; CHECK-NEXT: vredand.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9 ; CHECK-NEXT: vredand.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredand.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10 ; CHECK-NEXT: vredand.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredand.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9 ; CHECK-NEXT: vredand.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9 ; CHECK-NEXT: vredand.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9 ; CHECK-NEXT: vredand.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredand_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredand.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredand.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: vredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: vredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: vredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: vredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9 ; CHECK-NEXT: vredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: vredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: vredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9 ; CHECK-NEXT: vredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: vredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: vredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9 ; CHECK-NEXT: vredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: vredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: vredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmax.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: vredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: vredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9 ; CHECK-NEXT: vredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmax.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: vredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: vredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9 ; CHECK-NEXT: vredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmax.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10 ; CHECK-NEXT: vredmax.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmax.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9 ; CHECK-NEXT: vredmax.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9 ; CHECK-NEXT: vredmax.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9 ; CHECK-NEXT: vredmax.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmax_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmax.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmax.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9 ; CHECK-NEXT: vredmaxu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9 ; CHECK-NEXT: vredmaxu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9 ; CHECK-NEXT: vredmaxu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9 ; CHECK-NEXT: vredmaxu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9 ; CHECK-NEXT: vredmaxu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9 ; CHECK-NEXT: vredmaxu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9 ; CHECK-NEXT: vredmaxu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9 ; CHECK-NEXT: vredmaxu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9 ; CHECK-NEXT: vredmaxu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9 ; CHECK-NEXT: vredmaxu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9 ; CHECK-NEXT: vredmaxu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9 ; CHECK-NEXT: vredmaxu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9 ; CHECK-NEXT: vredmaxu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmaxu.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9 ; CHECK-NEXT: vredmaxu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9 ; CHECK-NEXT: vredmaxu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9 ; CHECK-NEXT: vredmaxu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmaxu.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9 ; CHECK-NEXT: vredmaxu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9 ; CHECK-NEXT: vredmaxu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9 ; CHECK-NEXT: vredmaxu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmaxu.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10 ; CHECK-NEXT: vredmaxu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9 ; CHECK-NEXT: vredmaxu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9 ; CHECK-NEXT: vredmaxu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9 ; CHECK-NEXT: vredmaxu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmaxu_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmaxu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmaxu.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9 ; CHECK-NEXT: vredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9 ; CHECK-NEXT: vredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9 ; CHECK-NEXT: vredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9 ; CHECK-NEXT: vredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9 ; CHECK-NEXT: vredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9 ; CHECK-NEXT: vredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9 ; CHECK-NEXT: vredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9 ; CHECK-NEXT: vredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9 ; CHECK-NEXT: vredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9 ; CHECK-NEXT: vredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9 ; CHECK-NEXT: vredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9 ; CHECK-NEXT: vredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9 ; CHECK-NEXT: vredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredmin.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9 ; CHECK-NEXT: vredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9 ; CHECK-NEXT: vredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9 ; CHECK-NEXT: vredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredmin.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9 ; CHECK-NEXT: vredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9 ; CHECK-NEXT: vredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9 ; CHECK-NEXT: vredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredmin.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10 ; CHECK-NEXT: vredmin.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredmin.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9 ; CHECK-NEXT: vredmin.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9 ; CHECK-NEXT: vredmin.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9 ; CHECK-NEXT: vredmin.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredmin_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredmin.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredmin.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9 ; CHECK-NEXT: vredminu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9 ; CHECK-NEXT: vredminu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9 ; CHECK-NEXT: vredminu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9 ; CHECK-NEXT: vredminu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9 ; CHECK-NEXT: vredminu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9 ; CHECK-NEXT: vredminu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9 ; CHECK-NEXT: vredminu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9 ; CHECK-NEXT: vredminu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9 ; CHECK-NEXT: vredminu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9 ; CHECK-NEXT: vredminu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9 ; CHECK-NEXT: vredminu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9 ; CHECK-NEXT: vredminu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9 ; CHECK-NEXT: vredminu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredminu.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9 ; CHECK-NEXT: vredminu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9 ; CHECK-NEXT: vredminu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9 ; CHECK-NEXT: vredminu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredminu.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9 ; CHECK-NEXT: vredminu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9 ; CHECK-NEXT: vredminu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9 ; CHECK-NEXT: vredminu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredminu.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10 ; CHECK-NEXT: vredminu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredminu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9 ; CHECK-NEXT: vredminu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9 ; CHECK-NEXT: vredminu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9 ; CHECK-NEXT: vredminu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredminu_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredminu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredminu.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9 ; CHECK-NEXT: vredor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9 ; CHECK-NEXT: vredor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9 ; CHECK-NEXT: vredor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9 ; CHECK-NEXT: vredor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9 ; CHECK-NEXT: vredor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9 ; CHECK-NEXT: vredor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9 ; CHECK-NEXT: vredor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9 ; CHECK-NEXT: vredor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9 ; CHECK-NEXT: vredor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9 ; CHECK-NEXT: vredor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9 ; CHECK-NEXT: vredor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9 ; CHECK-NEXT: vredor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9 ; CHECK-NEXT: vredor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredor.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9 ; CHECK-NEXT: vredor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9 ; CHECK-NEXT: vredor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9 ; CHECK-NEXT: vredor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredor.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9 ; CHECK-NEXT: vredor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9 ; CHECK-NEXT: vredor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9 ; CHECK-NEXT: vredor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredor.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10 ; CHECK-NEXT: vredor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9 ; CHECK-NEXT: vredor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9 ; CHECK-NEXT: vredor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9 ; CHECK-NEXT: vredor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredor_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredor.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9 ; CHECK-NEXT: vredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9 ; CHECK-NEXT: vredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9 ; CHECK-NEXT: vredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9 ; CHECK-NEXT: vredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9 ; CHECK-NEXT: vredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9 ; CHECK-NEXT: vredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9 ; CHECK-NEXT: vredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9 ; CHECK-NEXT: vredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9 ; CHECK-NEXT: vredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9 ; CHECK-NEXT: vredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9 ; CHECK-NEXT: vredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9 ; CHECK-NEXT: vredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9 ; CHECK-NEXT: vredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredsum.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9 ; CHECK-NEXT: vredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9 ; CHECK-NEXT: vredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9 ; CHECK-NEXT: vredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredsum.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9 ; CHECK-NEXT: vredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9 ; CHECK-NEXT: vredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9 ; CHECK-NEXT: vredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredsum.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10 ; CHECK-NEXT: vredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9 ; CHECK-NEXT: vredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9 ; CHECK-NEXT: vredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9 ; CHECK-NEXT: vredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredsum_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredsum.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9 ; CHECK-NEXT: vredxor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9 ; CHECK-NEXT: vredxor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i32 %3) i32 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9 ; CHECK-NEXT: vredxor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9 ; CHECK-NEXT: vredxor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9 ; CHECK-NEXT: vredxor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9 ; CHECK-NEXT: vredxor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9 ; CHECK-NEXT: vredxor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9 ; CHECK-NEXT: vredxor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9 ; CHECK-NEXT: vredxor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9 ; CHECK-NEXT: vredxor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9 ; CHECK-NEXT: vredxor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 1 x i8> %1, <vscale x 8 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv1i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv1i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 2 x i8> %1, <vscale x 8 x i8> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv2i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv2i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 4 x i8> %1, <vscale x 8 x i8> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv4i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv4i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv8i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv8i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9 ; CHECK-NEXT: vredxor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 16 x i8> %1, <vscale x 8 x i8> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv16i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv16i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9 ; CHECK-NEXT: vredxor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
i64 %3) i64 %3)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8( declare <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 8 x i8> @intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 32 x i8> %1, <vscale x 8 x i8> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv8i8_nxv32i8_nxv8i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8( %a = call <vscale x 8 x i8> @llvm.riscv.vredxor.mask.nxv8i8.nxv32i8(
<vscale x 8 x i8> %0, <vscale x 8 x i8> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 8 x i8> %a ret <vscale x 8 x i8> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i16> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv1i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv1i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i16> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv2i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv2i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i16> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv4i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9 ; CHECK-NEXT: vredxor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i16> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv8i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv8i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9 ; CHECK-NEXT: vredxor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i16> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv16i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv16i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9 ; CHECK-NEXT: vredxor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16( declare <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i16> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv4i16_nxv32i16_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16( %a = call <vscale x 4 x i16> @llvm.riscv.vredxor.mask.nxv4i16.nxv32i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i32> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv1i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv1i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i32> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv2i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9 ; CHECK-NEXT: vredxor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i32> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv4i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv4i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9 ; CHECK-NEXT: vredxor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i32> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv8i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv8i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9 ; CHECK-NEXT: vredxor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32( declare <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i32> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv2i32_nxv16i32_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32( %a = call <vscale x 2 x i32> @llvm.riscv.vredxor.mask.nxv2i32.nxv16i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10 ; CHECK-NEXT: vredxor.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m1,tu,mu
; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t ; CHECK-NEXT: vredxor.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i64> %1, <vscale x 1 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9 ; CHECK-NEXT: vredxor.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i64>, <vscale x 2 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i64> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv2i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m2,tu,mu
; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv2i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i64> %1, <vscale x 2 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9 ; CHECK-NEXT: vredxor.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i64>, <vscale x 4 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i64> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv4i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m4,tu,mu
; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv4i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i64> %1, <vscale x 4 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9 ; CHECK-NEXT: vredxor.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64( declare <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i64>, <vscale x 8 x i64>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i64> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64: ; CHECK-LABEL: intrinsic_vredxor_mask_vs_nxv1i64_nxv8i64_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e64,m8,tu,mu
; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t ; CHECK-NEXT: vredxor.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64( %a = call <vscale x 1 x i64> @llvm.riscv.vredxor.mask.nxv1i64.nxv8i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i64> %1, <vscale x 8 x i64> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwredsum-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9 ; CHECK-NEXT: vwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9 ; CHECK-NEXT: vwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9 ; CHECK-NEXT: vwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9 ; CHECK-NEXT: vwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9 ; CHECK-NEXT: vwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9 ; CHECK-NEXT: vwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9 ; CHECK-NEXT: vwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9 ; CHECK-NEXT: vwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9 ; CHECK-NEXT: vwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwredsum-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv1i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv1i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv1i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv1i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv2i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv2i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv2i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv2i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv8i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv8i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv8i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv8i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv16i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9 ; CHECK-NEXT: vwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv16i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv16i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv16i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv32i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9 ; CHECK-NEXT: vwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv32i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv32i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv32i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv4i16_nxv64i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9 ; CHECK-NEXT: vwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.nxv4i16.nxv64i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv4i16_nxv64i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsum.mask.nxv4i16.nxv64i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv1i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv1i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv1i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv1i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv4i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv4i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv4i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv4i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv8i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9 ; CHECK-NEXT: vwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv8i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv8i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv8i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv16i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9 ; CHECK-NEXT: vwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv16i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv16i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv16i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv2i32_nxv32i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9 ; CHECK-NEXT: vwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.nxv2i32.nxv32i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv2i32_nxv32i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsum.mask.nxv2i32.nxv32i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv2i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10 ; CHECK-NEXT: vwredsum.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv2i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv2i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsum.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv2i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv4i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9 ; CHECK-NEXT: vwredsum.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv4i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv4i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv4i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv8i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9 ; CHECK-NEXT: vwredsum.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv8i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv8i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv8i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_vs_nxv1i64_nxv16i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9 ; CHECK-NEXT: vwredsum.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.nxv1i64.nxv16i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsum_mask_vs_nxv1i64_nxv16i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsum.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsum.mask.nxv1i64.nxv16i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9 ; CHECK-NEXT: vwredsumu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9 ; CHECK-NEXT: vwredsumu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9 ; CHECK-NEXT: vwredsumu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i32 %3) i32 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, <vscale x 64 x i1> %3, i32 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, <vscale x 64 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv4i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv4i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv4i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv4i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv8i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv8i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9 ; CHECK-NEXT: vwredsumu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv8i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv8i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv16i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv16i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9 ; CHECK-NEXT: vwredsumu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv16i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv16i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv32i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv32i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9 ; CHECK-NEXT: vwredsumu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv32i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv32i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i32 %3) i32 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, <vscale x 32 x i1> %3, i32 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, <vscale x 32 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv2i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv2i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv2i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv2i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv4i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv4i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9 ; CHECK-NEXT: vwredsumu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv4i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv4i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv8i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv8i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9 ; CHECK-NEXT: vwredsumu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv8i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv8i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv16i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv16i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, i32 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9 ; CHECK-NEXT: vwredsumu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv16i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv16i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i32 %3) i32 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, <vscale x 16 x i1> %3, i32 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, <vscale x 16 x i1> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i32 %4) i32 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/rvv/vwredsumu-rv64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN: < %s | FileCheck %s ; RUN: < %s | FileCheck %s
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv1i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv1i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i8>, <vscale x 1 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 1 x i8> %1, <vscale x 4 x i16> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv1i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv1i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 1 x i8> %1, <vscale x 1 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv2i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv2i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i8>, <vscale x 2 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 2 x i8> %1, <vscale x 4 x i16> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv2i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv2i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 2 x i8> %1, <vscale x 2 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv4i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i8>, <vscale x 4 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i8> %1, <vscale x 4 x i16> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv4i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv4i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 4 x i8> %1, <vscale x 4 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv8i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv8i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i8>, <vscale x 8 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 8 x i8> %1, <vscale x 4 x i16> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv8i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv8i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 8 x i8> %1, <vscale x 8 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv16i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9 ; CHECK-NEXT: vwredsumu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv16i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i8>, <vscale x 16 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 16 x i8> %1, <vscale x 4 x i16> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv16i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv16i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 16 x i8> %1, <vscale x 16 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv32i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9 ; CHECK-NEXT: vwredsumu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv32i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i8>, <vscale x 32 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 32 x i8> %1, <vscale x 4 x i16> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv32i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv32i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 32 x i8> %1, <vscale x 32 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv4i16_nxv64i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9 ; CHECK-NEXT: vwredsumu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.nxv4i16.nxv64i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
i64 %3) i64 %3)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16( declare <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16(
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i8>, <vscale x 64 x i8>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 64 x i1>, <vscale x 64 x i1>,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, <vscale x 64 x i1> %3, i64 %4) nounwind { define <vscale x 4 x i16> @intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16(<vscale x 4 x i16> %0, <vscale x 64 x i8> %1, <vscale x 4 x i16> %2, <vscale x 64 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv4i16_nxv64i8_nxv4i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e8,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16( %a = call <vscale x 4 x i16> @llvm.riscv.vwredsumu.mask.nxv4i16.nxv64i8.nxv4i16(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
<vscale x 64 x i8> %1, <vscale x 64 x i8> %1,
<vscale x 4 x i16> %2, <vscale x 4 x i16> %2,
<vscale x 64 x i1> %3, <vscale x 64 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv1i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv1i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i16>, <vscale x 1 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 1 x i16> %1, <vscale x 2 x i32> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv1i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv1i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 1 x i16> %1, <vscale x 1 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv2i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i16>, <vscale x 2 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i16> %1, <vscale x 2 x i32> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv2i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv2i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 2 x i16> %1, <vscale x 2 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv4i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv4i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv4i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv4i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv4i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i16>, <vscale x 4 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 4 x i16> %1, <vscale x 2 x i32> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv4i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv4i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 4 x i16> %1, <vscale x 4 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv8i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv8i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv8i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9 ; CHECK-NEXT: vwredsumu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv8i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv8i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i16>, <vscale x 8 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 8 x i16> %1, <vscale x 2 x i32> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv8i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv8i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 8 x i16> %1, <vscale x 8 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv16i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv16i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv16i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9 ; CHECK-NEXT: vwredsumu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv16i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv16i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i16>, <vscale x 16 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 16 x i16> %1, <vscale x 2 x i32> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv16i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv16i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 16 x i16> %1, <vscale x 16 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv32i16( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv32i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv2i32_nxv32i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9 ; CHECK-NEXT: vwredsumu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv32i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.nxv2i32.nxv32i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
i64 %3) i64 %3)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32( declare <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32(
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i16>, <vscale x 32 x i16>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 32 x i1>, <vscale x 32 x i1>,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, <vscale x 32 x i1> %3, i64 %4) nounwind { define <vscale x 2 x i32> @intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32(<vscale x 2 x i32> %0, <vscale x 32 x i16> %1, <vscale x 2 x i32> %2, <vscale x 32 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv2i32_nxv32i16_nxv2i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e16,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32( %a = call <vscale x 2 x i32> @llvm.riscv.vwredsumu.mask.nxv2i32.nxv32i16.nxv2i32(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
<vscale x 32 x i16> %1, <vscale x 32 x i16> %1,
<vscale x 2 x i32> %2, <vscale x 2 x i32> %2,
<vscale x 32 x i1> %3, <vscale x 32 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i32>, <vscale x 1 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i32> %1, <vscale x 1 x i64> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv1i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,mf2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv1i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 1 x i32> %1, <vscale x 1 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv2i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv2i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv2i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10 ; CHECK-NEXT: vwredsumu.vs v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv2i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv2i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i32>, <vscale x 2 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 2 x i32> %1, <vscale x 1 x i64> %2, <vscale x 2 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv2i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m1,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv2i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 2 x i32> %1, <vscale x 2 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv4i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv4i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv4i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9 ; CHECK-NEXT: vwredsumu.vs v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv4i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv4i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i32>, <vscale x 4 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 4 x i32> %1, <vscale x 1 x i64> %2, <vscale x 4 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv4i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m2,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v10, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv4i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 4 x i32> %1, <vscale x 4 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv8i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv8i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv8i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9 ; CHECK-NEXT: vwredsumu.vs v8, v12, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv8i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv8i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i32>, <vscale x 8 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 8 x i32> %1, <vscale x 1 x i64> %2, <vscale x 8 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv8i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m4,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v12, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv8i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 8 x i32> %1, <vscale x 8 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv16i32( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv16i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_vs_nxv1i64_nxv16i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9 ; CHECK-NEXT: vwredsumu.vs v8, v16, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv16i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.nxv1i64.nxv16i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
i64 %3) i64 %3)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }
declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.nxv1i64( declare <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.nxv1i64(
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i32>, <vscale x 16 x i32>,
<vscale x 1 x i64>, <vscale x 1 x i64>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, <vscale x 16 x i1> %3, i64 %4) nounwind { define <vscale x 1 x i64> @intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64(<vscale x 1 x i64> %0, <vscale x 16 x i32> %1, <vscale x 1 x i64> %2, <vscale x 16 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64: ; CHECK-LABEL: intrinsic_vwredsumu_mask_vs_nxv1i64_nxv16i32_nxv1i64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m8,ta,mu ; CHECK-NEXT: vsetvli zero, a0, e32,m8,tu,mu
; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t ; CHECK-NEXT: vwredsumu.vs v8, v16, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.nxv1i64( %a = call <vscale x 1 x i64> @llvm.riscv.vwredsumu.mask.nxv1i64.nxv16i32.nxv1i64(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
<vscale x 16 x i32> %1, <vscale x 16 x i32> %1,
<vscale x 1 x i64> %2, <vscale x 1 x i64> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
i64 %4) i64 %4)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
} }

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

Show First 20 Lines • Show All 572 Lines • ▼ Show 20 Lines
; RV32MV-NEXT: addi a1, a1, %lo(.LCPI4_0) ; RV32MV-NEXT: addi a1, a1, %lo(.LCPI4_0)
; RV32MV-NEXT: vle16.v v26, (a1) ; RV32MV-NEXT: vle16.v v26, (a1)
; RV32MV-NEXT: vid.v v27 ; RV32MV-NEXT: vid.v v27
; RV32MV-NEXT: vsub.vv v25, v25, v27 ; RV32MV-NEXT: vsub.vv v25, v25, v27
; RV32MV-NEXT: vmul.vv v25, v25, v26 ; RV32MV-NEXT: vmul.vv v25, v25, v26
; RV32MV-NEXT: vsll.vi v26, v25, 1 ; RV32MV-NEXT: vsll.vi v26, v25, 1
; RV32MV-NEXT: addi a1, zero, 9 ; RV32MV-NEXT: addi a1, zero, 9
; RV32MV-NEXT: vmv.v.i v27, 10 ; RV32MV-NEXT: vmv.v.i v27, 10
; RV32MV-NEXT: vsetvli zero, zero, e16,mf2,tu,mu
; RV32MV-NEXT: vmv.s.x v27, a1 ; RV32MV-NEXT: vmv.s.x v27, a1
; RV32MV-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; RV32MV-NEXT: vsll.vv v26, v26, v27 ; RV32MV-NEXT: vsll.vv v26, v26, v27
; RV32MV-NEXT: addi a1, zero, 2047 ; RV32MV-NEXT: addi a1, zero, 2047
; RV32MV-NEXT: vand.vx v25, v25, a1 ; RV32MV-NEXT: vand.vx v25, v25, a1
; RV32MV-NEXT: vmv.v.i v27, 0 ; RV32MV-NEXT: vmv.v.i v27, 0
; RV32MV-NEXT: addi a2, zero, 1 ; RV32MV-NEXT: addi a2, zero, 1
; RV32MV-NEXT: vsetvli zero, zero, e16,mf2,tu,mu
; RV32MV-NEXT: vmv1r.v v28, v27 ; RV32MV-NEXT: vmv1r.v v28, v27
; RV32MV-NEXT: vmv.s.x v28, a2 ; RV32MV-NEXT: vmv.s.x v28, a2
; RV32MV-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; RV32MV-NEXT: lui a2, %hi(.LCPI4_1) ; RV32MV-NEXT: lui a2, %hi(.LCPI4_1)
; RV32MV-NEXT: addi a2, a2, %lo(.LCPI4_1) ; RV32MV-NEXT: addi a2, a2, %lo(.LCPI4_1)
; RV32MV-NEXT: vle16.v v29, (a2) ; RV32MV-NEXT: vle16.v v29, (a2)
; RV32MV-NEXT: vsrl.vv v25, v25, v28 ; RV32MV-NEXT: vsrl.vv v25, v25, v28
; RV32MV-NEXT: vor.vv v25, v25, v26 ; RV32MV-NEXT: vor.vv v25, v25, v26
; RV32MV-NEXT: vand.vx v25, v25, a1 ; RV32MV-NEXT: vand.vx v25, v25, a1
; RV32MV-NEXT: vmsltu.vv v0, v29, v25 ; RV32MV-NEXT: vmsltu.vv v0, v29, v25
; RV32MV-NEXT: vmerge.vim v25, v27, -1, v0 ; RV32MV-NEXT: vmerge.vim v25, v27, -1, v0
Show All 37 Lines
; RV64MV-NEXT: addi a1, a1, %lo(.LCPI4_0) ; RV64MV-NEXT: addi a1, a1, %lo(.LCPI4_0)
; RV64MV-NEXT: vle16.v v26, (a1) ; RV64MV-NEXT: vle16.v v26, (a1)
; RV64MV-NEXT: vid.v v27 ; RV64MV-NEXT: vid.v v27
; RV64MV-NEXT: vsub.vv v25, v25, v27 ; RV64MV-NEXT: vsub.vv v25, v25, v27
; RV64MV-NEXT: vmul.vv v25, v25, v26 ; RV64MV-NEXT: vmul.vv v25, v25, v26
; RV64MV-NEXT: vsll.vi v26, v25, 1 ; RV64MV-NEXT: vsll.vi v26, v25, 1
; RV64MV-NEXT: addi a1, zero, 9 ; RV64MV-NEXT: addi a1, zero, 9
; RV64MV-NEXT: vmv.v.i v27, 10 ; RV64MV-NEXT: vmv.v.i v27, 10
; RV64MV-NEXT: vsetvli zero, zero, e16,mf2,tu,mu
; RV64MV-NEXT: vmv.s.x v27, a1 ; RV64MV-NEXT: vmv.s.x v27, a1
; RV64MV-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; RV64MV-NEXT: vsll.vv v26, v26, v27 ; RV64MV-NEXT: vsll.vv v26, v26, v27
; RV64MV-NEXT: addi a1, zero, 2047 ; RV64MV-NEXT: addi a1, zero, 2047
; RV64MV-NEXT: vand.vx v25, v25, a1 ; RV64MV-NEXT: vand.vx v25, v25, a1
; RV64MV-NEXT: vmv.v.i v27, 0 ; RV64MV-NEXT: vmv.v.i v27, 0
; RV64MV-NEXT: addi a2, zero, 1 ; RV64MV-NEXT: addi a2, zero, 1
; RV64MV-NEXT: vsetvli zero, zero, e16,mf2,tu,mu
; RV64MV-NEXT: vmv1r.v v28, v27 ; RV64MV-NEXT: vmv1r.v v28, v27
; RV64MV-NEXT: vmv.s.x v28, a2 ; RV64MV-NEXT: vmv.s.x v28, a2
; RV64MV-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; RV64MV-NEXT: lui a2, %hi(.LCPI4_1) ; RV64MV-NEXT: lui a2, %hi(.LCPI4_1)
; RV64MV-NEXT: addi a2, a2, %lo(.LCPI4_1) ; RV64MV-NEXT: addi a2, a2, %lo(.LCPI4_1)
; RV64MV-NEXT: vle16.v v29, (a2) ; RV64MV-NEXT: vle16.v v29, (a2)
; RV64MV-NEXT: vsrl.vv v25, v25, v28 ; RV64MV-NEXT: vsrl.vv v25, v25, v28
; RV64MV-NEXT: vor.vv v25, v25, v26 ; RV64MV-NEXT: vor.vv v25, v25, v26
; RV64MV-NEXT: vand.vx v25, v25, a1 ; RV64MV-NEXT: vand.vx v25, v25, a1
; RV64MV-NEXT: vmsltu.vv v0, v29, v25 ; RV64MV-NEXT: vmsltu.vv v0, v29, v25
; RV64MV-NEXT: vmerge.vim v25, v27, -1, v0 ; RV64MV-NEXT: vmerge.vim v25, v27, -1, v0
Show All 27 Lines