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[RISCV] Improve register allocation for masked vwadd(u).wv, vwsub(u).wv, vfwadd.wv, and vfwsub.wv.
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Authored by craig.topper on May 26 2021, 3:18 PM.

Details

Summary

The first source has the same EEW as the destination, but we're
using earlyclobber which prevents them from ever being the same
register.

To workaround this, add a special TIED pseudo to use whenever the
first source and merge operand are the same value. This allows
us to use a single operand for the merge operand and first source
which we can then tie to the destination. A tied source disables
earlyclobber for that operand.

Diff Detail

Event Timeline

craig.topper created this revision.May 26 2021, 3:18 PM
craig.topper requested review of this revision.May 26 2021, 3:18 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 26 2021, 3:18 PM
Herald added a subscriber: MaskRay. · View Herald Transcript

Rebase after pre-commiting tests.

Fix accidental test name changes

arcbbb accepted this revision.Jun 1 2021, 6:15 PM

LGTM

This revision is now accepted and ready to land.Jun 1 2021, 6:15 PM
This revision was landed with ongoing or failed builds.Jun 1 2021, 7:04 PM
This revision was automatically updated to reflect the committed changes.