[PowerPC] Added multiple PowerPC builtins

[quinnp]

Summary

This is the first in a series of patches to provide builtins for
compatibility with the XL compiler. Most of the builtins already had
intrinsics and only needed to be implemented in the front end.
Intrinsics were created for the three iospace builtins, eieio, and icbt.
Pseudo instructions were created for eieio and iospace_eieio to
ensure that nops were inserted before the eieio instruction.

[quinnp]

Fixed some formatting.

[quinnp]

[PowerPC] Fixing previous update.

[quinnp]

Removing redundant tests.

[quinnp]

Re-added some changes that were lost in the previous updates.

[quinnp]

Removed some unused checks in a test.

[qiucf]

Is there any motivation to add these builtins? I don't see them implemented in GCC. Besides, in Clang I think a prefix __builtin is preferred for them.

clang/include/clang/Basic/BuiltinsPPC.def

28

On PPC we have __builtin_popcount, but I only saw popcntw and popcntd generated. (I didn't verify it carefully)

[nemanjai]

In terms of the motivation for this, the description of the patch should include something along the lines of:

"This is the first in a series of patches to provide builtins for compatibility with the XL compiler."

Since these builtins don't really conform to the typical naming in clang (i.e. using the __builtin prefix), perhaps @rjmccall or @rsmith have a suggestion as to how we should proceed here.
If the names with two underscores are acceptable, great (there won't be any name clashes with existing builtins).
However if those names are not acceptable, we might be able to implement some sort of compatibility layer in Clang where the names are intercepted if compiling for a PPC target and handled in CGBuiltin.cpp.

clang/include/clang/Basic/BuiltinsPPC.def

28

There isn't really a good candidate builtin for this since this does a popcount in each byte separately. Of course, it could be used for a popcount of i8, but that is just a subset of what the builtin/instruction do.

[rjmccall]

If these builtins are generally supposed to be accessed through a compiler-provided header, you could make that header define these functions using underlying builtins that have a __builtin prefix. That's not completely necessary, though; we do support some other non-library builtins that lack the __builtin prefix. And it sounds like maybe there isn't such a header anyway.

[quinnp]

Adding a comment in BuiltinsPPC.def for motivation.

[rjmccall]

The Clang part of this looks fine to me; I can't review the backend changes, but you have partial approval.

[quinnp]

This update is motivated by comments made by @nemanjai. All of the builtin names have been changed to follow the convention of __builtin_<arch>_<func>. To fulfill the original goal of compatibility with the XL compiler, macros have been added to map __<func> to __builtin_ppc_<func>.

[rjmccall]

Alright, that's fine with me, too.

[nemanjai]

LGTM. Thanks for implementing this. The redundant pseudo can be removed when committing.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

2572

These two are identical. Please only define one.

[quinnp]

Addressing the last comments made by @nemanjai.

[stefanp]

Rebased revision to top of trunk.

[stefanp]

Updated author to Quinn.

clang/include/clang/Basic/BuiltinsPPC.def

 // MMA builtins that are using their own format documented below.
 
 #if defined(BUILTIN) && !defined(CUSTOM_BUILTIN)
 #   define CUSTOM_BUILTIN(ID, TYPES, ACCUMULATE) BUILTIN(__builtin_##ID, "i.", "t")
 #elif defined(CUSTOM_BUILTIN) && !defined(BUILTIN)
 #   define BUILTIN(ID, TYPES, ATTRS)
 #endif
 
+BUILTIN(__popcntb, "ULiULi", "")
+BUILTIN(__eieio, "v", "")
+BUILTIN(__iospace_eieio, "v", "")
+BUILTIN(__isync, "v", "")
+BUILTIN(__lwsync, "v", "")
+BUILTIN(__iospace_lwsync, "v", "")
+BUILTIN(__sync, "v", "")
+BUILTIN(__iospace_sync, "v", "")
+BUILTIN(__dcbfl, "vvC*", "")
+BUILTIN(__dcbflp, "vvC*", "")
+BUILTIN(__dcbst, "vvC*", "")
+BUILTIN(__dcbt, "vv*", "")
+BUILTIN(__dcbtst, "vv*", "")
+BUILTIN(__dcbz, "vv*", "")
+BUILTIN(__icbt, "vv*", "")
+
 BUILTIN(__builtin_ppc_get_timebase, "ULLi", "n")
 
 // This is just a placeholder, the types and attributes are wrong.
 BUILTIN(__builtin_altivec_vaddcuw, "V4UiV4UiV4Ui", "")
 
 BUILTIN(__builtin_altivec_vaddsbs, "V16ScV16ScV16Sc", "")
 BUILTIN(__builtin_altivec_vaddubs, "V16UcV16UcV16Uc", "")
 BUILTIN(__builtin_altivec_vaddshs, "V8SsV8SsV8Ss", "")

llvm/include/llvm/IR/IntrinsicsPowerPC.td

 //
 
 // Non-altivec intrinsics.
 let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   // dcba/dcbf/dcbi/dcbst/dcbt/dcbz/dcbzl(PPC970) instructions.
   def int_ppc_dcba  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbf : GCCBuiltin<"__builtin_dcbf">,
                       Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
-  def int_ppc_dcbfl : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
-  def int_ppc_dcbflp : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
+  def int_ppc_dcbfl : GCCBuiltin<"__dcbfl">,
+                      Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
+  def int_ppc_dcbflp : GCCBuiltin<"__dcbflp">,
+                       Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
   def int_ppc_dcbfps : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
   def int_ppc_dcbstps : Intrinsic<[], [llvm_ptr_ty], [IntrArgMemOnly]>;
   def int_ppc_dcbi  : Intrinsic<[], [llvm_ptr_ty], []>;
-  def int_ppc_dcbst : Intrinsic<[], [llvm_ptr_ty], []>;
-  def int_ppc_dcbt  : Intrinsic<[], [llvm_ptr_ty],
+  def int_ppc_dcbst : GCCBuiltin<"__dcbst">,
+                      Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbt  : GCCBuiltin<"__dcbt">,
+                      Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
-  def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
+  def int_ppc_dcbtst : GCCBuiltin<"__dcbtst">,
+                       Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
   def int_ppc_dcbt_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
   def int_ppc_dcbtst_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
-  def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_dcbz  : GCCBuiltin<"__dcbz">,
+                      Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
+  def int_ppc_icbt : GCCBuiltin<"__icbt">,
+                     Intrinsic<[], [llvm_ptr_ty], []>;
 
   // Population Count in each Byte.
-  def int_ppc_popcntb : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
+  def int_ppc_popcntb : GCCBuiltin<"__popcntb">,
+                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty], [IntrNoMem]>;
 
   // sync instruction (i.e. sync 0, a.k.a hwsync)
-  def int_ppc_sync : Intrinsic<[], [], []>;
+  def int_ppc_sync : GCCBuiltin<"__sync">,
+                     Intrinsic<[], [], []>;
+  def int_ppc_iospace_sync : GCCBuiltin<"__iospace_sync">,
+                             Intrinsic<[], [], []>;
   // isync instruction
-  def int_ppc_isync : Intrinsic<[], [], []>;
+  def int_ppc_isync : GCCBuiltin<"__isync">,
+                      Intrinsic<[], [], []>;
   // lwsync is sync 1
-  def int_ppc_lwsync : Intrinsic<[], [], []>;
+  def int_ppc_lwsync : GCCBuiltin<"__lwsync">,
+                       Intrinsic<[], [], []>;
+  def int_ppc_iospace_lwsync : GCCBuiltin<"__iospace_lwsync">,
+                               Intrinsic<[], [], []>;
   // eieio instruction
-  def int_ppc_eieio : Intrinsic<[],[],[]>;
+  def int_ppc_eieio : GCCBuiltin<"__eieio">,
+                      Intrinsic<[],[],[]>;
+  def int_ppc_iospace_eieio : GCCBuiltin<"__iospace_eieio">,
+                              Intrinsic<[],[],[]>;
 
   // Get content from current FPSCR register
   def int_ppc_readflm : GCCBuiltin<"__builtin_readflm">,
                         Intrinsic<[llvm_double_ty], [], [IntrNoMem]>;
   // Set FPSCR register, and return previous content
   def int_ppc_setflm : GCCBuiltin<"__builtin_setflm">,
                        Intrinsic<[llvm_double_ty], [llvm_double_ty], []>;
 

llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp

case PPC::LWA: {
     if (MO.isGlobal()) {
       const DataLayout &DL = MO.getGlobal()->getParent()->getDataLayout();
       if (MO.getGlobal()->getPointerAlignment(DL) < 4)
         llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
     }
     // Now process the instruction normally.
     break;
   }
+  case PPC::PseudoEIEIO:
+  case PPC::PseudoIOSPACEEIEIO:
+    EmitToStreamer(
+        *OutStreamer,
+        MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0));
+    EmitToStreamer(
+        *OutStreamer,
+        MCInstBuilder(PPC::ORI).addReg(PPC::X2).addReg(PPC::X2).addImm(0));
+    EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::EnforceIEIO));
+    break;
   }
 
   LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
   EmitToStreamer(*OutStreamer, TmpInst);
 }
 
 void PPCLinuxAsmPrinter::emitInstruction(const MachineInstr *MI) {
   if (!Subtarget->isPPC64())

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def ICBTLS : XForm_icbt<31, 486, (outs), (ins u4imm:$CT, memrr:$src),
                        "icbtls $CT, $src", IIC_LdStLoad>, Requires<[HasICBT]>;
 
 def : Pat<(int_ppc_dcbt xoaddr:$dst),
           (DCBT 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbtst xoaddr:$dst),
           (DCBTST 0, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbf xoaddr:$dst),
           (DCBF 0, xoaddr:$dst)>;
+def : Pat<(int_ppc_icbt xoaddr:$dst),
+          (ICBT 0, xoaddr:$dst)>;
 
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 1)),
           (DCBT 0, xoaddr:$dst)>;   // data prefetch for loads
 def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
           (DCBTST 0, xoaddr:$dst)>; // data prefetch for stores
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
           (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
 
def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
     let L = 0;
   }
 }
 
 // We used to have EIEIO as value but E[0-9A-Z] is a reserved name
 def EnforceIEIO : XForm_24_eieio<31, 854, (outs), (ins),
                                  "eieio", IIC_LdStLoad, []>;
 
+def PseudoEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCEIEIO",
+                  [(int_ppc_eieio)]>;
+def PseudoIOSPACEEIEIO : PPCEmitTimePseudo<(outs), (ins), "#PPCIOSPACEEIEIO",
+                         [(int_ppc_iospace_eieio)]>;
+
 def : Pat<(int_ppc_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
+def : Pat<(int_ppc_iospace_sync),   (SYNC 0)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
+def : Pat<(int_ppc_iospace_lwsync), (SYNC 1)>, Requires<[HasSYNC]>;
 def : Pat<(int_ppc_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
+def : Pat<(int_ppc_iospace_sync),   (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 def : Pat<(int_ppc_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
+def : Pat<(int_ppc_iospace_lwsync), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 def : Pat<(int_ppc_eieio),  (EnforceIEIO)>;
+def : Pat<(int_ppc_iospace_eieio),  (EnforceIEIO)>;
 
 //===----------------------------------------------------------------------===//
 // PPC32 Arithmetic Instructions.
 //
 
 let PPC970_Unit = 1 in {  // FXU Operations.
 def ADDI   : DForm_2<14, (outs gprc:$rD), (ins gprc_nor0:$rA, s16imm:$imm),
                      "addi $rD, $rA, $imm", IIC_IntSimple,

llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat.ll

+; RUN: llc < %s | FileCheck %s
+
+define dso_local void @test_builtin_ppc_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_eieio
+
+entry:
+  call void @llvm.ppc.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_eieio() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_eieio
+
+entry:
+  call void @llvm.ppc.iospace.eieio()
+; CHECK: ori 2, 2, 0
+; CHECK-NEXT: ori 2, 2, 0
+; CHECK-NEXT: eieio
+ 
+  ret void
+}
+
+declare void @llvm.ppc.iospace.eieio() #2
+
+define dso_local void @test_builtin_ppc_iospace_lwsync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_lwsync
+
+entry:
+  call void @llvm.ppc.iospace.lwsync()
+; CHECK: lwsync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.lwsync() #2
+
+define dso_local void @test_builtin_ppc_iospace_sync() #0 {
+; CHECK-LABEL: test_builtin_ppc_iospace_sync
+
+entry:
+  call void @llvm.ppc.iospace.sync()
+; CHECK: sync
+
+  ret void
+}
+
+declare void @llvm.ppc.iospace.sync() #2
+
+define dso_local void @test_builtin_ppc_icbt() #0 {
+; CHECK-LABEL: test_builtin_ppc_icbt
+
+entry:
+  %a = alloca i8*, align 8
+  %0 = load i8*, i8** %a, align 8
+  call void @llvm.ppc.icbt(i8* %0)
+; CHECK: icbt 0, 0, 3
+
+  ret void
+}
+
+declare void @llvm.ppc.icbt(i8*) #2