GlobalISel: Move AArch64 AssignFnVarArg to base class

[arsenm]

Summary

We can handle the distinction easily enough in the generic code, and
this makes it easier to abstract the selection of type/location from
the code to insert code.

[arsenm]

2bdfcf0cac148ada8d3ec36f551c45efb604ac49

llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h

public:
   /// Argument handling is mostly uniform between the four places that
   /// make these decisions: function formal arguments, call
   /// instruction args, call instruction returns and function
   /// returns. However, once a decision has been made on where an
   /// argument should go, exactly what happens can vary slightly. This
   /// class abstracts the differences.
   struct ValueHandler {
     ValueHandler(bool IsIncoming, MachineIRBuilder &MIRBuilder,
-                 MachineRegisterInfo &MRI, CCAssignFn *AssignFn)
-        : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn),
-          IsIncomingArgumentHandler(IsIncoming) {}
+                 MachineRegisterInfo &MRI, CCAssignFn *AssignFn_,
+                 CCAssignFn *AssignFnVarArg_ = nullptr)
+        : MIRBuilder(MIRBuilder), MRI(MRI), AssignFn(AssignFn_),
+          AssignFnVarArg(AssignFnVarArg_),
+          IsIncomingArgumentHandler(IsIncoming) {
+
+      // Some targets change the handler depending on whether the call is
+      // varargs or not. If
+      if (!AssignFnVarArg)
+        AssignFnVarArg = AssignFn;
+    }
 
     virtual ~ValueHandler() = default;
 
     /// Returns true if the handler is dealing with incoming arguments,
     /// i.e. those that move values from some physical location to vregs.
     bool isIncomingArgumentHandler() const {
       return IsIncomingArgumentHandler;
     }
struct ValueHandler {
 
     /// Wrap call to (typically tablegenerated CCAssignFn). This may be
     /// overridden to track additional state information as arguments are
     /// assigned or apply target specific hacks around the legacy
     /// infrastructure.
     virtual bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
                            CCValAssign::LocInfo LocInfo, const ArgInfo &Info,
                            ISD::ArgFlagsTy Flags, CCState &State) {
-      return AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
+      return getAssignFn(State.isVarArg())(ValNo, ValVT, LocVT, LocInfo, Flags,
+                                           State);
     }
 
     MachineIRBuilder &MIRBuilder;
     MachineRegisterInfo &MRI;
+
+    /// Assignment function to use for a general call.
     CCAssignFn *AssignFn;
 
+    /// Assignment function to use for a variadic call. This is usually the same
+    /// as AssignFn.
+    CCAssignFn *AssignFnVarArg;
+
+    /// Select the appropriate assignment function depending on whether this is
+    /// a variadic call.
+    CCAssignFn *getAssignFn(bool IsVarArg) const {
+      return IsVarArg ? AssignFnVarArg : AssignFn;
+    }
+
   private:
     bool IsIncomingArgumentHandler;
     virtual void anchor();
   };
 
   struct IncomingValueHandler : public ValueHandler {
     IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
-                         CCAssignFn *AssignFn)
-        : ValueHandler(true, MIRBuilder, MRI, AssignFn) {}
+                         CCAssignFn *AssignFn_,
+                         CCAssignFn *AssignFnVarArg_ = nullptr)
+        : ValueHandler(true, MIRBuilder, MRI, AssignFn_, AssignFnVarArg_) {}
 
     /// Insert G_ASSERT_ZEXT/G_ASSERT_SEXT or other hint instruction based on \p
     /// VA, returning the new register if a hint was inserted.
     Register buildExtensionHint(CCValAssign &VA, Register SrcReg, LLT NarrowTy);
 
     /// Provides a default implementation for argument handling.
     void assignValueToReg(Register ValVReg, Register PhysReg,
                           CCValAssign &VA) override;
   };
 
   struct OutgoingValueHandler : public ValueHandler {
     OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
-                         CCAssignFn *AssignFn)
-        : ValueHandler(false, MIRBuilder, MRI, AssignFn) {}
+                         CCAssignFn *AssignFn,
+                         CCAssignFn *AssignFnVarArg = nullptr)
+        : ValueHandler(false, MIRBuilder, MRI, AssignFn, AssignFnVarArg) {}
   };
 
 protected:
   /// Getter for generic TargetLowering class.
   const TargetLowering *getTLI() const {
     return TLI;
   }
 

llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp

void assignValueToAddress(Register ValVReg, Register Addr, uint64_t MemSize,
     }
   }
 
   bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
                  CCValAssign::LocInfo LocInfo,
                  const CallLowering::ArgInfo &Info, ISD::ArgFlagsTy Flags,
                  CCState &State) override {
     applyStackPassedSmallTypeDAGHack(OrigVT, ValVT, LocVT);
-    return AssignFn(ValNo, ValVT, LocVT, LocInfo, Flags, State);
+    return getAssignFn(State.isVarArg())(ValNo, ValVT, LocVT, LocInfo, Flags,
+                                         State);
   }
 
   /// How the physical register gets marked varies between formal
   /// parameters (it's a basic-block live-in), and a call instruction
   /// (it's an implicit-def of the BL).
   virtual void markPhysRegUsed(MCRegister PhysReg) = 0;
 
   uint64_t StackUsed;
struct ReturnedArgCallReturnHandler : public CallReturnHandler {
   void markPhysRegUsed(MCRegister PhysReg) override {}
 };
 
 struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler {
   OutgoingArgHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
                      MachineInstrBuilder MIB, CCAssignFn *AssignFn,
                      CCAssignFn *AssignFnVarArg, bool IsReturn,
                      bool IsTailCall = false, int FPDiff = 0)
-      : OutgoingValueHandler(MIRBuilder, MRI, AssignFn), MIB(MIB),
-        AssignFnVarArg(AssignFnVarArg), IsReturn(IsReturn),
-        IsTailCall(IsTailCall), FPDiff(FPDiff), StackSize(0), SPReg(0),
+      : OutgoingValueHandler(MIRBuilder, MRI, AssignFn, AssignFnVarArg),
+        MIB(MIB), IsReturn(IsReturn), IsTailCall(IsTailCall), FPDiff(FPDiff),
+        StackSize(0), SPReg(0),
         Subtarget(MIRBuilder.getMF().getSubtarget<AArch64Subtarget>()) {}
 
   Register getStackAddress(uint64_t Size, int64_t Offset,
                            MachinePointerInfo &MPO,
                            ISD::ArgFlagsTy Flags) override {
     MachineFunction &MF = MIRBuilder.getMF();
     LLT p0 = LLT::pointer(0, 64);
     LLT s64 = LLT::scalar(64);
bool assignArg(unsigned ValNo, EVT OrigVT, MVT ValVT, MVT LocVT,
     else
       Res = AssignFnVarArg(ValNo, ValVT, LocVT, LocInfo, Flags, State);
 
     StackSize = State.getNextStackOffset();
     return Res;
   }
 
   MachineInstrBuilder MIB;
-  CCAssignFn *AssignFnVarArg;
 
   /// Track if this is used for a return instead of function argument
   /// passing. We apply a hack to i1/i8/i16 stack passed values, but do not use
   /// stack passed returns for them and cannot apply the type adjustment.
   bool IsReturn;
   bool IsTailCall;
 
   /// For tail calls, the byte offset of the call's argument area from the