AMDGPU: Fix allowing immediates for tail call pseudo.

[arsenm]

Summary

The pseudo was using SSrc_b64, so it allowed folding immediates into
the destination operand for a tail call to null. However, this is not
a valid operand for the s_setpc_b64 this will be lowered to. Avoids
printing the operand as an invalid immediate.

Avoids a regression when tail calls are enabled in GlobalISel (somehow
tail calls to null get deleted in the DAG).

[dp]

I don't see any restriction noted that this must be a register, so just allow any SSrc_b64 like normal.

Documentation is not clear here, however sp3 does not allow constants for src0 (as opposed to null).

[rampitec]

In D98631#2626123, @dp wrote:

I don't see any restriction noted that this must be a register, so just allow any SSrc_b64 like normal.

Documentation is not clear here, however sp3 does not allow constants for src0 (as opposed to null).

+1. It is defined as OPR_SREG.

[rampitec]

LGTM

[arsenm]

20a24af01de2eeb3d1f88fa22cee7201bf13d608

llvm/lib/Target/AMDGPU/SIInstructions.td

def SI_CALL : SPseudoInstSI <
   let UseNamedOperandTable = 1;
   let SchedRW = [WriteBranch];
   // TODO: Should really base this on the call target
   let isConvergent = 1;
 }
 
 // Tail call handling pseudo
 def SI_TCRETURN : SPseudoInstSI <(outs),
-  (ins SSrc_b64:$src0, unknown:$callee, i32imm:$fpdiff),
+  (ins SReg_64:$src0, unknown:$callee, i32imm:$fpdiff),
   [(AMDGPUtc_return i64:$src0, tglobaladdr:$callee, i32:$fpdiff)]> {
   let Size = 4;
   let isCall = 1;
   let isTerminator = 1;
   let isReturn = 1;
   let isBarrier = 1;
   let UseNamedOperandTable = 1;
   let SchedRW = [WriteBranch];

llvm/test/MC/AMDGPU/sop1-err.s

 s_mov_b32 s102, 1
 // VI: error: register not available on this GPU
 
 s_mov_b32 s103, 1
 // VI: error: register not available on this GPU
 
 s_mov_b64 s[102:103], -1
 // VI: error: register not available on this GPU
+
+s_setpc_b64 0
+// GCN: error: invalid operand for instruction