[RISCV] Precommit a test case that test accessing a fixed object when has rvv vector object existed

[HsiangKai]

LGTM.

[frasercrmck]

llvm/test/CodeGen/RISCV/rvv/localvar.ll

290

Maybe if this is wrong code add a little FIXME comment to explain what's wrong? Just in case your follow-up patch takes a while to land.

[StephenFan]

llvm/test/CodeGen/RISCV/rvv/localvar.ll

290

Maybe if this is wrong code add a little FIXME comment to explain what's wrong? Just in case your follow-up patch takes a while to land.

290

I'm sorry that I forgot your comment. Recently, the patch that fix this wrong code is accepted.

[StephenFan]

rebase.

llvm/test/CodeGen/RISCV/rvv/localvar.ll

; RV64IV-NEXT:    ret
   call void @notdead2(i8* %1, i32* %2, <vscale x 16 x i8>* %local0)
   load volatile i32, i32* %local_scalar0
   load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local0
   load volatile <vscale x 16 x i8>, <vscale x 16 x i8>* %local1
   load volatile i32, i32* %local_scalar1
   ret void
 }
 
+define i64 @fixed_object(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5, i64 %6, i64 %7, i64 %8) nounwind {
+; RV64IV-LABEL: fixed_object:
+; RV64IV:       # %bb.0:
+; RV64IV-NEXT:    addi sp, sp, -32
+; RV64IV-NEXT:    csrr a0, vlenb
+; RV64IV-NEXT:    slli a0, a0, 3
+; RV64IV-NEXT:    sub sp, sp, a0
+; RV64IV-NEXT:    ld a0, 32(sp)
+; RV64IV-NEXT:    csrr a1, vlenb
+; RV64IV-NEXT:    slli a1, a1, 3
+; RV64IV-NEXT:    add sp, sp, a1
+; RV64IV-NEXT:    addi sp, sp, 32
+; RV64IV-NEXT:    ret
+  %fixed_size = alloca i32
+  %rvv_vector = alloca <vscale x 8 x i64>, align 8
+  ret i64 %8
+}
+
 declare void @notdead(i8*, <vscale x 16 x i8>*)
 declare void @notdead2(i8*, i32*, <vscale x 16 x i8>*)