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Differential D100217

[RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf and vfwsub.wf.
ClosedPublic

Authored by craig.topper on Apr 9 2021, 10:42 AM.

Details

Reviewers
frasercrmck
HsiangKai
khchen
arcbbb
evandro
Commits
rG3ae71226ef49: [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf…
Summary

The first source has the same EEW as the destination and the other
source is a scalar so the overlap constraints don't apply to
the unmasked version.

For the masked version we have a constraint that the destination
can't be V0 so that covers the only overlap issue there.

Diff Detail

Event Timeline

craig.topper created this revision.Apr 9 2021, 10:42 AM
Herald added subscribers: StephenFan, vkmr, luismarques and 24 others. · View Herald TranscriptApr 9 2021, 10:42 AM
craig.topper requested review of this revision.Apr 9 2021, 10:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 9 2021, 10:42 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B98035: Diff 336515.Apr 9 2021, 11:39 AM
khchen accepted this revision.Apr 11 2021, 5:58 AM

Good catch! LGTM.

This revision is now accepted and ready to land.Apr 11 2021, 5:58 AM
Closed by commit rG3ae71226ef49: [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf… (authored by craig.topper). · Explain WhyApr 11 2021, 10:28 AM
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rG3ae71226ef49: [RISCV] Drop earlyclobber constraint from vwadd(u).wx, vwsub(u).wx, vfwadd.wf….

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
6 lines
test/
CodeGen/
RISCV/
rvv/
27 lines
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Diff 336677

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 1,592 Lines • ▼ Show 20 Lines
multiclass VPseudoBinaryW_WV { multiclass VPseudoBinaryW_WV {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m, defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
multiclass VPseudoBinaryW_WX { multiclass VPseudoBinaryW_WX {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m, defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m>;
"@earlyclobber $rd">;
} }
multiclass VPseudoBinaryW_WF { multiclass VPseudoBinaryW_WF {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
foreach f = FPList.fpinfo[0-1] in foreach f = FPList.fpinfo[0-1] in
defm "_W" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass, defm "_W" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass,
f.fprclass, m, f.fprclass, m>;
"@earlyclobber $rd">;
} }
multiclass VPseudoBinaryV_WV { multiclass VPseudoBinaryV_WV {
foreach m = MxList.m[0-5] in foreach m = MxList.m[0-5] in
defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m, defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">; "@earlyclobber $rd">;
} }
▲ Show 20 Lines • Show All 2,800 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv32.ll

Show First 20 Lines • Show All 412 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16(
half, half,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfwadd.wf v25, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
Show All 29 Linesdeclare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16(
half, half,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfwadd.wf v25, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
Show All 29 Linesdeclare <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16(
half, half,
i32); i32);
define <vscale x 4 x float> @intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfwadd.wf v26, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
Show All 29 Linesdeclare <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16(
half, half,
i32); i32);
define <vscale x 8 x float> @intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfwadd.wf v28, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
Show All 29 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16(
half, half,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfwadd.wf v16, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
Show All 29 Linesdeclare <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32(
float, float,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfwadd.wf v25, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
Show All 29 Linesdeclare <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32(
float, float,
i32); i32);
define <vscale x 2 x double> @intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfwadd.wf v26, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
Show All 29 Linesdeclare <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32(
float, float,
i32); i32);
define <vscale x 4 x double> @intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfwadd.wf v28, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
Show All 29 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32(
float, float,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfwadd.wf v16, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
Show All 26 Lines

llvm/test/CodeGen/RISCV/rvv/vfwadd.w-rv64.ll

Show First 20 Lines • Show All 412 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16(
half, half,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfwadd.wf v25, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwadd.w.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
Show All 29 Linesdeclare <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16(
half, half,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfwadd.wf v25, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwadd.w.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
Show All 29 Linesdeclare <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16(
half, half,
i64); i64);
define <vscale x 4 x float> @intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfwadd.wf v26, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwadd.w.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
Show All 29 Linesdeclare <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16(
half, half,
i64); i64);
define <vscale x 8 x float> @intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfwadd.wf v28, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwadd.w.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
Show All 29 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16(
half, half,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfwadd.wf v16, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwadd.w.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
Show All 29 Linesdeclare <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32(
float, float,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfwadd.wf v25, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwadd.w.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
Show All 29 Linesdeclare <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32(
float, float,
i64); i64);
define <vscale x 2 x double> @intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfwadd.wf v26, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwadd.w.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
Show All 29 Linesdeclare <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32(
float, float,
i64); i64);
define <vscale x 4 x double> @intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfwadd.wf v28, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwadd.w.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
Show All 29 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32(
float, float,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32: ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfwadd.wf v16, v8, ft0 ; CHECK-NEXT: vfwadd.wf v8, v8, ft0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwadd.w.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
Show All 26 Lines

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv32.ll

Show First 20 Lines • Show All 412 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
half, half,
i32); i32);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i32 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfwsub.wf v25, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
Show All 29 Linesdeclare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
half, half,
i32); i32);
define <vscale x 2 x float> @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i32 %2) nounwind { define <vscale x 2 x float> @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfwsub.wf v25, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
Show All 29 Linesdeclare <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
half, half,
i32); i32);
define <vscale x 4 x float> @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i32 %2) nounwind { define <vscale x 4 x float> @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfwsub.wf v26, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
Show All 29 Linesdeclare <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
half, half,
i32); i32);
define <vscale x 8 x float> @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i32 %2) nounwind { define <vscale x 8 x float> @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfwsub.wf v28, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
Show All 29 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
half, half,
i32); i32);
define <vscale x 16 x float> @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i32 %2) nounwind { define <vscale x 16 x float> @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfwsub.wf v16, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
i32 %2) i32 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
Show All 29 Linesdeclare <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32(
float, float,
i32); i32);
define <vscale x 1 x double> @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i32 %2) nounwind { define <vscale x 1 x double> @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfwsub.wf v25, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
Show All 29 Linesdeclare <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32(
float, float,
i32); i32);
define <vscale x 2 x double> @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i32 %2) nounwind { define <vscale x 2 x double> @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfwsub.wf v26, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
Show All 29 Linesdeclare <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32(
float, float,
i32); i32);
define <vscale x 4 x double> @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i32 %2) nounwind { define <vscale x 4 x double> @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfwsub.wf v28, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
Show All 29 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32(
float, float,
i32); i32);
define <vscale x 8 x double> @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i32 %2) nounwind { define <vscale x 8 x double> @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfwsub.wf v16, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
i32 %2) i32 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
Show All 26 Lines

llvm/test/CodeGen/RISCV/rvv/vfwsub.w-rv64.ll

Show First 20 Lines • Show All 412 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
half, half,
i64); i64);
define <vscale x 1 x float> @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i64 %2) nounwind { define <vscale x 1 x float> @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16(<vscale x 1 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,mf4,ta,mu
; CHECK-NEXT: vfwsub.wf v25, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16( %a = call <vscale x 1 x float> @llvm.riscv.vfwsub.w.nxv1f32.f16(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
Show All 29 Linesdeclare <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
half, half,
i64); i64);
define <vscale x 2 x float> @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i64 %2) nounwind { define <vscale x 2 x float> @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16(<vscale x 2 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,mf2,ta,mu
; CHECK-NEXT: vfwsub.wf v25, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16( %a = call <vscale x 2 x float> @llvm.riscv.vfwsub.w.nxv2f32.f16(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
Show All 29 Linesdeclare <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
half, half,
i64); i64);
define <vscale x 4 x float> @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i64 %2) nounwind { define <vscale x 4 x float> @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16(<vscale x 4 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m1,ta,mu
; CHECK-NEXT: vfwsub.wf v26, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16( %a = call <vscale x 4 x float> @llvm.riscv.vfwsub.w.nxv4f32.f16(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
Show All 29 Linesdeclare <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
half, half,
i64); i64);
define <vscale x 8 x float> @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i64 %2) nounwind { define <vscale x 8 x float> @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16(<vscale x 8 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m2,ta,mu
; CHECK-NEXT: vfwsub.wf v28, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16( %a = call <vscale x 8 x float> @llvm.riscv.vfwsub.w.nxv8f32.f16(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
Show All 29 Linesdeclare <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
half, half,
i64); i64);
define <vscale x 16 x float> @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i64 %2) nounwind { define <vscale x 16 x float> @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16(<vscale x 16 x float> %0, half %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.h.x ft0, a0 ; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e16,m4,ta,mu
; CHECK-NEXT: vfwsub.wf v16, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16( %a = call <vscale x 16 x float> @llvm.riscv.vfwsub.w.nxv16f32.f16(
<vscale x 16 x float> %0, <vscale x 16 x float> %0,
half %1, half %1,
i64 %2) i64 %2)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
Show All 29 Linesdeclare <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32(
float, float,
i64); i64);
define <vscale x 1 x double> @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i64 %2) nounwind { define <vscale x 1 x double> @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32(<vscale x 1 x double> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,mf2,ta,mu
; CHECK-NEXT: vfwsub.wf v25, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32( %a = call <vscale x 1 x double> @llvm.riscv.vfwsub.w.nxv1f64.f32(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
float %1, float %1,
i64 %2) i64 %2)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
Show All 29 Linesdeclare <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32(
float, float,
i64); i64);
define <vscale x 2 x double> @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i64 %2) nounwind { define <vscale x 2 x double> @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32(<vscale x 2 x double> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m1,ta,mu
; CHECK-NEXT: vfwsub.wf v26, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32( %a = call <vscale x 2 x double> @llvm.riscv.vfwsub.w.nxv2f64.f32(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
float %1, float %1,
i64 %2) i64 %2)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
Show All 29 Linesdeclare <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32(
float, float,
i64); i64);
define <vscale x 4 x double> @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i64 %2) nounwind { define <vscale x 4 x double> @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32(<vscale x 4 x double> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m2,ta,mu
; CHECK-NEXT: vfwsub.wf v28, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32( %a = call <vscale x 4 x double> @llvm.riscv.vfwsub.w.nxv4f64.f32(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
float %1, float %1,
i64 %2) i64 %2)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
Show All 29 Linesdeclare <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32(
float, float,
i64); i64);
define <vscale x 8 x double> @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i64 %2) nounwind { define <vscale x 8 x double> @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32(<vscale x 8 x double> %0, float %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32: ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: fmv.w.x ft0, a0 ; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a0, a1, e32,m4,ta,mu
; CHECK-NEXT: vfwsub.wf v16, v8, ft0 ; CHECK-NEXT: vfwsub.wf v8, v8, ft0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32( %a = call <vscale x 8 x double> @llvm.riscv.vfwsub.w.nxv8f64.f32(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
float %1, float %1,
i64 %2) i64 %2)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
Show All 26 Lines

llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv32.ll

Show First 20 Lines • Show All 682 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
Show All 27 Linesdeclare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
Show All 27 Linesdeclare <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
Show All 27 Linesdeclare <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vwadd.wx v26, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
Show All 27 Linesdeclare <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vwadd.wx v28, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
Show All 27 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwadd.w.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vwadd.wx v16, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
Show All 27 Linesdeclare <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
Show All 27 Linesdeclare <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
Show All 27 Linesdeclare <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vwadd.wx v26, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
Show All 27 Linesdeclare <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vwadd.wx v28, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
Show All 27 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwadd.w.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vwadd.wx v16, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
Show All 27 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
Show All 27 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vwadd.wx v26, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
Show All 27 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vwadd.wx v28, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
Show All 27 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwadd.w.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vwadd.wx v16, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
Show All 25 Lines

llvm/test/CodeGen/RISCV/rvv/vwadd.w-rv64.ll

Show First 20 Lines • Show All 682 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i16_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwadd.w.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
Show All 27 Linesdeclare <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i16_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwadd.w.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
Show All 27 Linesdeclare <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i16_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwadd.w.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
Show All 27 Linesdeclare <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i16_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vwadd.wx v26, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwadd.w.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
Show All 27 Linesdeclare <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i16_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vwadd.wx v28, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwadd.w.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
Show All 27 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwadd.w.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv32i16_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vwadd.wx v16, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwadd.w.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
Show All 27 Linesdeclare <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i32_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwadd.w.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
Show All 27 Linesdeclare <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i32_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwadd.w.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
Show All 27 Linesdeclare <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i32_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vwadd.wx v26, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwadd.w.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
Show All 27 Linesdeclare <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i32_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vwadd.wx v28, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwadd.w.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
Show All 27 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwadd.w.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv16i32_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vwadd.wx v16, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwadd.w.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
Show All 27 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv1i64_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vwadd.wx v25, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwadd.w.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
Show All 27 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv2i64_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vwadd.wx v26, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwadd.w.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
Show All 27 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv4i64_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vwadd.wx v28, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwadd.w.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
Show All 27 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwadd.w.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vwadd.w_wx_nxv8i64_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vwadd.wx v16, v8, a0 ; CHECK-NEXT: vwadd.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwadd.w.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
Show All 25 Lines

llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv32.ll

Show First 20 Lines • Show All 682 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
Show All 27 Linesdeclare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
Show All 27 Linesdeclare <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
Show All 27 Linesdeclare <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vwaddu.wx v26, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
Show All 27 Linesdeclare <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vwaddu.wx v28, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
Show All 27 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vwaddu.wx v16, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
Show All 27 Linesdeclare <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
Show All 27 Linesdeclare <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
Show All 27 Linesdeclare <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vwaddu.wx v26, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
Show All 27 Linesdeclare <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vwaddu.wx v28, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
Show All 27 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vwaddu.wx v16, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
Show All 27 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
Show All 27 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vwaddu.wx v26, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
Show All 27 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vwaddu.wx v28, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
Show All 27 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vwaddu.wx v16, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
Show All 25 Lines

llvm/test/CodeGen/RISCV/rvv/vwaddu.w-rv64.ll

Show First 20 Lines • Show All 682 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i16_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwaddu.w.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
Show All 27 Linesdeclare <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i16_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwaddu.w.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
Show All 27 Linesdeclare <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i16_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwaddu.w.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
Show All 27 Linesdeclare <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i16_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vwaddu.wx v26, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwaddu.w.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
Show All 27 Linesdeclare <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i16_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vwaddu.wx v28, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwaddu.w.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
Show All 27 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv32i16_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vwaddu.wx v16, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwaddu.w.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
Show All 27 Linesdeclare <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i32_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwaddu.w.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
Show All 27 Linesdeclare <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i32_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwaddu.w.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
Show All 27 Linesdeclare <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i32_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vwaddu.wx v26, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwaddu.w.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
Show All 27 Linesdeclare <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i32_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vwaddu.wx v28, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwaddu.w.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
Show All 27 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv16i32_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vwaddu.wx v16, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwaddu.w.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
Show All 27 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv1i64_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vwaddu.wx v25, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwaddu.w.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
Show All 27 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv2i64_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vwaddu.wx v26, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwaddu.w.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
Show All 27 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv4i64_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vwaddu.wx v28, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwaddu.w.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
Show All 27 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vwaddu.w_wx_nxv8i64_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vwaddu.wx v16, v8, a0 ; CHECK-NEXT: vwaddu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwaddu.w.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
Show All 25 Lines

llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll

Show First 20 Lines • Show All 682 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
Show All 27 Linesdeclare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
Show All 27 Linesdeclare <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
Show All 27 Linesdeclare <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vwsub.wx v26, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
Show All 27 Linesdeclare <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vwsub.wx v28, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
Show All 27 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vwsub.wx v16, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
Show All 27 Linesdeclare <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
Show All 27 Linesdeclare <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
Show All 27 Linesdeclare <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vwsub.wx v26, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
Show All 27 Linesdeclare <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vwsub.wx v28, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
Show All 27 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwsub.w.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vwsub.wx v16, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
Show All 27 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
Show All 27 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vwsub.wx v26, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
Show All 27 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vwsub.wx v28, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
Show All 27 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vwsub.wx v16, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
Show All 25 Lines

llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll

Show First 20 Lines • Show All 682 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i16_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
Show All 27 Linesdeclare <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i16_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
Show All 27 Linesdeclare <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i16_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
Show All 27 Linesdeclare <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i16_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vwsub.wx v26, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
Show All 27 Linesdeclare <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i16_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vwsub.wx v28, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
Show All 27 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv32i16_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vwsub.wx v16, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
Show All 27 Linesdeclare <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i32_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
Show All 27 Linesdeclare <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i32_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
Show All 27 Linesdeclare <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i32_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vwsub.wx v26, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
Show All 27 Linesdeclare <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i32_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vwsub.wx v28, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
Show All 27 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwsub.w.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv16i32_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vwsub.wx v16, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
Show All 27 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv1i64_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vwsub.wx v25, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
Show All 27 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv2i64_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vwsub.wx v26, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
Show All 27 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv4i64_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vwsub.wx v28, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
Show All 27 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vwsub.w_wx_nxv8i64_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vwsub.wx v16, v8, a0 ; CHECK-NEXT: vwsub.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
Show All 25 Lines

llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll

Show First 20 Lines • Show All 682 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
i32); i32);
define <vscale x 1 x i16> @intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
Show All 27 Linesdeclare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
i32); i32);
define <vscale x 2 x i16> @intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
Show All 27 Linesdeclare <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
i32); i32);
define <vscale x 4 x i16> @intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
Show All 27 Linesdeclare <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
i32); i32);
define <vscale x 8 x i16> @intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vwsubu.wx v26, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
Show All 27 Linesdeclare <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
i32); i32);
define <vscale x 16 x i16> @intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vwsubu.wx v28, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
Show All 27 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
i32); i32);
define <vscale x 32 x i16> @intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vwsubu.wx v16, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
i32 %2) i32 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
Show All 27 Linesdeclare <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
i32); i32);
define <vscale x 1 x i32> @intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
Show All 27 Linesdeclare <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
i32); i32);
define <vscale x 2 x i32> @intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
Show All 27 Linesdeclare <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
i32); i32);
define <vscale x 4 x i32> @intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vwsubu.wx v26, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
Show All 27 Linesdeclare <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
i32); i32);
define <vscale x 8 x i32> @intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vwsubu.wx v28, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
Show All 27 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
i32); i32);
define <vscale x 16 x i32> @intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vwsubu.wx v16, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
i32 %2) i32 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
Show All 27 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i32); i32);
define <vscale x 1 x i64> @intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
Show All 27 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i32); i32);
define <vscale x 2 x i64> @intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vwsubu.wx v26, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
Show All 27 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i32); i32);
define <vscale x 4 x i64> @intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vwsubu.wx v28, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
Show All 27 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
i32); i32);
define <vscale x 8 x i64> @intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vwsubu.wx v16, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
i32 %2) i32 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
Show All 25 Lines

llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll

Show First 20 Lines • Show All 682 Lines • ▼ Show 20 Linesdeclare <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8(
<vscale x 1 x i16>, <vscale x 1 x i16>,
i8, i8,
i64); i64);
define <vscale x 1 x i16> @intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 1 x i16> @intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8(<vscale x 1 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i16_nxv1i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8( %a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.i8(
<vscale x 1 x i16> %0, <vscale x 1 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i16> %a ret <vscale x 1 x i16> %a
Show All 27 Linesdeclare <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8(
<vscale x 2 x i16>, <vscale x 2 x i16>,
i8, i8,
i64); i64);
define <vscale x 2 x i16> @intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 2 x i16> @intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8(<vscale x 2 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i16_nxv2i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8( %a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.i8(
<vscale x 2 x i16> %0, <vscale x 2 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i16> %a ret <vscale x 2 x i16> %a
Show All 27 Linesdeclare <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.i8(
<vscale x 4 x i16>, <vscale x 4 x i16>,
i8, i8,
i64); i64);
define <vscale x 4 x i16> @intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 4 x i16> @intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8(<vscale x 4 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i16_nxv4i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.i8( %a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.i8(
<vscale x 4 x i16> %0, <vscale x 4 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i16> %a ret <vscale x 4 x i16> %a
Show All 27 Linesdeclare <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.i8(
<vscale x 8 x i16>, <vscale x 8 x i16>,
i8, i8,
i64); i64);
define <vscale x 8 x i16> @intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 8 x i16> @intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8(<vscale x 8 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i16_nxv8i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vwsubu.wx v26, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.i8( %a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.i8(
<vscale x 8 x i16> %0, <vscale x 8 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i16> %a ret <vscale x 8 x i16> %a
Show All 27 Linesdeclare <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.i8(
<vscale x 16 x i16>, <vscale x 16 x i16>,
i8, i8,
i64); i64);
define <vscale x 16 x i16> @intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 16 x i16> @intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8(<vscale x 16 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i16_nxv16i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m2,ta,mu
; CHECK-NEXT: vwsubu.wx v28, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.i8( %a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.i8(
<vscale x 16 x i16> %0, <vscale x 16 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i16> %a ret <vscale x 16 x i16> %a
Show All 27 Linesdeclare <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.i8(
<vscale x 32 x i16>, <vscale x 32 x i16>,
i8, i8,
i64); i64);
define <vscale x 32 x i16> @intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind { define <vscale x 32 x i16> @intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8(<vscale x 32 x i16> %0, i8 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv32i16_nxv32i16_i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e8,m4,ta,mu
; CHECK-NEXT: vwsubu.wx v16, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.i8( %a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.i8(
<vscale x 32 x i16> %0, <vscale x 32 x i16> %0,
i8 %1, i8 %1,
i64 %2) i64 %2)
ret <vscale x 32 x i16> %a ret <vscale x 32 x i16> %a
Show All 27 Linesdeclare <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.i16(
<vscale x 1 x i32>, <vscale x 1 x i32>,
i16, i16,
i64); i64);
define <vscale x 1 x i32> @intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 1 x i32> @intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16(<vscale x 1 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i32_nxv1i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.i16( %a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.i16(
<vscale x 1 x i32> %0, <vscale x 1 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i32> %a ret <vscale x 1 x i32> %a
Show All 27 Linesdeclare <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.i16(
<vscale x 2 x i32>, <vscale x 2 x i32>,
i16, i16,
i64); i64);
define <vscale x 2 x i32> @intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 2 x i32> @intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16(<vscale x 2 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i32_nxv2i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.i16( %a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.i16(
<vscale x 2 x i32> %0, <vscale x 2 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i32> %a ret <vscale x 2 x i32> %a
Show All 27 Linesdeclare <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.i16(
<vscale x 4 x i32>, <vscale x 4 x i32>,
i16, i16,
i64); i64);
define <vscale x 4 x i32> @intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 4 x i32> @intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16(<vscale x 4 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i32_nxv4i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vwsubu.wx v26, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.i16( %a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.i16(
<vscale x 4 x i32> %0, <vscale x 4 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i32> %a ret <vscale x 4 x i32> %a
Show All 27 Linesdeclare <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.i16(
<vscale x 8 x i32>, <vscale x 8 x i32>,
i16, i16,
i64); i64);
define <vscale x 8 x i32> @intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 8 x i32> @intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16(<vscale x 8 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i32_nxv8i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m2,ta,mu
; CHECK-NEXT: vwsubu.wx v28, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.i16( %a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.i16(
<vscale x 8 x i32> %0, <vscale x 8 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i32> %a ret <vscale x 8 x i32> %a
Show All 27 Linesdeclare <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.i16(
<vscale x 16 x i32>, <vscale x 16 x i32>,
i16, i16,
i64); i64);
define <vscale x 16 x i32> @intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind { define <vscale x 16 x i32> @intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16(<vscale x 16 x i32> %0, i16 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv16i32_nxv16i32_i16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e16,m4,ta,mu
; CHECK-NEXT: vwsubu.wx v16, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.i16( %a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.i16(
<vscale x 16 x i32> %0, <vscale x 16 x i32> %0,
i16 %1, i16 %1,
i64 %2) i64 %2)
ret <vscale x 16 x i32> %a ret <vscale x 16 x i32> %a
Show All 27 Linesdeclare <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.i32(
<vscale x 1 x i64>, <vscale x 1 x i64>,
i32, i32,
i64); i64);
define <vscale x 1 x i64> @intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 1 x i64> @intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32(<vscale x 1 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv1i64_nxv1i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vwsubu.wx v25, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.i32( %a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.i32(
<vscale x 1 x i64> %0, <vscale x 1 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 1 x i64> %a ret <vscale x 1 x i64> %a
Show All 27 Linesdeclare <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.i32(
<vscale x 2 x i64>, <vscale x 2 x i64>,
i32, i32,
i64); i64);
define <vscale x 2 x i64> @intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 2 x i64> @intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32(<vscale x 2 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv2i64_nxv2i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vwsubu.wx v26, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.i32( %a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.i32(
<vscale x 2 x i64> %0, <vscale x 2 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 2 x i64> %a ret <vscale x 2 x i64> %a
Show All 27 Linesdeclare <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.i32(
<vscale x 4 x i64>, <vscale x 4 x i64>,
i32, i32,
i64); i64);
define <vscale x 4 x i64> @intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 4 x i64> @intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32(<vscale x 4 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv4i64_nxv4i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m2,ta,mu
; CHECK-NEXT: vwsubu.wx v28, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.i32( %a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.i32(
<vscale x 4 x i64> %0, <vscale x 4 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 4 x i64> %a ret <vscale x 4 x i64> %a
Show All 27 Linesdeclare <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.i32(
<vscale x 8 x i64>, <vscale x 8 x i64>,
i32, i32,
i64); i64);
define <vscale x 8 x i64> @intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind { define <vscale x 8 x i64> @intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32(<vscale x 8 x i64> %0, i32 %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32: ; CHECK-LABEL: intrinsic_vwsubu.w_wx_nxv8i64_nxv8i64_i32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu ; CHECK-NEXT: vsetvli a1, a1, e32,m4,ta,mu
; CHECK-NEXT: vwsubu.wx v16, v8, a0 ; CHECK-NEXT: vwsubu.wx v8, v8, a0
; CHECK-NEXT: vmv8r.v v8, v16
; CHECK-NEXT: jalr zero, 0(ra) ; CHECK-NEXT: jalr zero, 0(ra)
entry: entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.i32( %a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.i32(
<vscale x 8 x i64> %0, <vscale x 8 x i64> %0,
i32 %1, i32 %1,
i64 %2) i64 %2)
ret <vscale x 8 x i64> %a ret <vscale x 8 x i64> %a
Show All 25 Lines