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Differential D99955

AMDGPU: Add isBranch=1 to SOPP branch instructions
ClosedPublic

Authored by kzhuravl on Apr 6 2021, 7:12 AM.

Details

Reviewers
rampitec
Joe_Nash
arsenm
Commits
rG844012940e17: AMDGPU: Add isBranch=1 to SOPP branch instructions
Summary

This might have been lost during refactoring.

Diff Detail

Unit TestsFailed

TimeTest
130 msx64 debian > cfi-devirt-lld-thinlto-x86_64.icall::bad-signature.c
140 msx64 debian > cfi-devirt-lld-x86_64.icall::bad-signature.c
120 msx64 debian > cfi-standalone-lld-thinlto-x86_64.icall::bad-signature.c
170 msx64 debian > cfi-standalone-lld-x86_64.icall::bad-signature.c

Event Timeline

kzhuravl created this revision.Apr 6 2021, 7:12 AM
Herald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptApr 6 2021, 7:12 AM
kzhuravl requested review of this revision.Apr 6 2021, 7:12 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 6 2021, 7:12 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
kzhuravl added reviewers: Joe_Nash, arsenm.Apr 6 2021, 7:13 AM
arsenm accepted this revision.Apr 6 2021, 7:28 AM
This revision is now accepted and ready to land.Apr 6 2021, 7:28 AM
Joe_Nash accepted this revision.Apr 6 2021, 7:29 AM
Harbormaster completed remote builds in B97300: Diff 335504.Apr 6 2021, 7:47 AM
This revision was landed with ongoing or failed builds.Apr 6 2021, 7:59 AM
Closed by commit rG844012940e17: AMDGPU: Add isBranch=1 to SOPP branch instructions (authored by kzhuravl). · Explain Why
This revision was automatically updated to reflect the committed changes.
kzhuravl added a commit: rG844012940e17: AMDGPU: Add isBranch=1 to SOPP branch instructions.
dp mentioned this in D106072: [AMDGPU][MC] Added missing isCall/isBranch flags.Jul 15 2021, 8:41 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AMDGPU/
25 lines

Diff 335504

llvm/lib/Target/AMDGPU/SOPInstructions.td

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//relaxation for insts with no operands not implemented //relaxation for insts with no operands not implemented
multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> { multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<bits<7> op> {
defm "" : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<op>; defm "" : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<op>;
defm _pad_s_nop : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<op>; defm _pad_s_nop : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10<op>;
} }
defm S_NOP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x000>; defm S_NOP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x000>;
defm S_ENDPGM : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x001, "s_endpgm">; defm S_ENDPGM : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x001, "s_endpgm">;
defm S_BRANCH : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x002>;
defm S_WAKEUP : SOPP_Real_32_gfx8_gfx9_gfx10<0x003>; defm S_WAKEUP : SOPP_Real_32_gfx8_gfx9_gfx10<0x003>;
defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x004>;
defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x005>;
defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x006>;
defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x007>;
defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x008>;
defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x009>;
defm S_CBRANCH_CDBGSYS : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x017>;
defm S_CBRANCH_CDBGUSER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x018>;
defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x019>;
defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x01A>;
defm S_BARRIER : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00a>; defm S_BARRIER : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00a>;
defm S_WAITCNT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00c>; defm S_WAITCNT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00c>;
defm S_SETHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00d>; defm S_SETHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00d>;
defm S_SETKILL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00b>; defm S_SETKILL : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00b>;
defm S_SLEEP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00e>; defm S_SLEEP : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00e>;
defm S_SETPRIO : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00f>; defm S_SETPRIO : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x00f>;
defm S_SENDMSG : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x010>; defm S_SENDMSG : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x010>;
defm S_SENDMSGHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x011>; defm S_SENDMSGHALT : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10<0x011>;
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defm S_INST_PREFETCH : SOPP_Real_32_gfx10<0x020>; defm S_INST_PREFETCH : SOPP_Real_32_gfx10<0x020>;
defm S_CLAUSE : SOPP_Real_32_gfx10<0x021>; defm S_CLAUSE : SOPP_Real_32_gfx10<0x021>;
defm S_WAIT_IDLE : SOPP_Real_32_gfx10<0x022>; defm S_WAIT_IDLE : SOPP_Real_32_gfx10<0x022>;
defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx10<0x023>; defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx10<0x023>;
defm S_ROUND_MODE : SOPP_Real_32_gfx10<0x024>; defm S_ROUND_MODE : SOPP_Real_32_gfx10<0x024>;
defm S_DENORM_MODE : SOPP_Real_32_gfx10<0x025>; defm S_DENORM_MODE : SOPP_Real_32_gfx10<0x025>;
defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx10<0x028>; defm S_TTRACEDATA_IMM : SOPP_Real_32_gfx10<0x028>;
let isBranch = 1 in {
defm S_BRANCH : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x002>;
defm S_CBRANCH_SCC0 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x004>;
defm S_CBRANCH_SCC1 : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x005>;
defm S_CBRANCH_VCCZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x006>;
defm S_CBRANCH_VCCNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x007>;
defm S_CBRANCH_EXECZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x008>;
defm S_CBRANCH_EXECNZ : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x009>;
defm S_CBRANCH_CDBGSYS : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x017>;
defm S_CBRANCH_CDBGUSER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x018>;
defm S_CBRANCH_CDBGSYS_OR_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x019>;
defm S_CBRANCH_CDBGSYS_AND_USER : SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10<0x01A>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SOPC - GFX6, GFX7, GFX8, GFX9, GFX10 // SOPC - GFX6, GFX7, GFX8, GFX9, GFX10
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
multiclass SOPC_Real_gfx6_gfx7<bits<7> op> { multiclass SOPC_Real_gfx6_gfx7<bits<7> op> {
def _gfx6_gfx7 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>, def _gfx6_gfx7 : SOPC_Real<op, !cast<SOPC_Pseudo>(NAME)>,
Select_gfx6_gfx7<!cast<SOPC_Pseudo>(NAME).Mnemonic>; Select_gfx6_gfx7<!cast<SOPC_Pseudo>(NAME).Mnemonic>;
} }
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