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Differential D99454

[RISCV] Add vfabs.v pseudo instruction.
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Authored by HsiangKai on Mar 27 2021, 4:44 AM.

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craig.topper
rogfer01
frasercrmck
Commits
rGbc82e9bf25ab: [RISCV] Add vfabs.v pseudo instruction.

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HsiangKai created this revision.Mar 27 2021, 4:44 AM
Herald added subscribers: StephenFan, vkmr, evandro and 24 others. · View Herald TranscriptMar 27 2021, 4:44 AM
HsiangKai requested review of this revision.Mar 27 2021, 4:44 AM
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Harbormaster completed remote builds in B95960: Diff 333668.Mar 27 2021, 5:30 AM
craig.topper accepted this revision.Mar 27 2021, 3:08 PM

LGTM

This revision is now accepted and ready to land.Mar 27 2021, 3:08 PM
Closed by commit rGbc82e9bf25ab: [RISCV] Add vfabs.v pseudo instruction. (authored by HsiangKai). · Explain WhyMar 27 2021, 8:34 PM
This revision was automatically updated to reflect the committed changes.
HsiangKai added a commit: rGbc82e9bf25ab: [RISCV] Add vfabs.v pseudo instruction..

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
test/
MC/
RISCV/
rvv/
3 lines

Diff 333668

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

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// Vector Floating-Point Sign-Injection Instructions // Vector Floating-Point Sign-Injection Instructions
defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>; defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>;
defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>; defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>;
defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>; defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>;
def : InstAlias<"vfneg.v $vd, $vs$vm", def : InstAlias<"vfneg.v $vd, $vs$vm",
(VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>; (VFSGNJN_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>;
def : InstAlias<"vfabs.v $vd, $vs$vm",
(VFSGNJX_VV VR:$vd, VR:$vs, VR:$vs, VMaskOp:$vm)>;
// Vector Floating-Point Compare Instructions // Vector Floating-Point Compare Instructions
let RVVConstraint = NoConstraint in { let RVVConstraint = NoConstraint in {
defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>; defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>;
defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>; defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>;
defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>; defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>;
defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>; defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>;
defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>; defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>;
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llvm/test/MC/RISCV/rvv/aliases.s

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# NO-ALIAS: vrsub.vx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0x0c] # NO-ALIAS: vrsub.vx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0x0c]
vneg.v v2, v1, v0.t vneg.v v2, v1, v0.t
# ALIAS: vncvt.x.x.w v2, v1, v0.t # encoding: [0x57,0x41,0x10,0xb0] # ALIAS: vncvt.x.x.w v2, v1, v0.t # encoding: [0x57,0x41,0x10,0xb0]
# NO-ALIAS: vnsrl.wx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0xb0] # NO-ALIAS: vnsrl.wx v2, v1, zero, v0.t # encoding: [0x57,0x41,0x10,0xb0]
vncvt.x.x.w v2, v1, v0.t vncvt.x.x.w v2, v1, v0.t
# ALIAS: vfneg.v v2, v1, v0.t # encoding: [0x57,0x91,0x10,0x24] # ALIAS: vfneg.v v2, v1, v0.t # encoding: [0x57,0x91,0x10,0x24]
# NO-ALIAS: vfsgnjn.vv v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x24] # NO-ALIAS: vfsgnjn.vv v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x24]
vfneg.v v2, v1, v0.t vfneg.v v2, v1, v0.t
# ALIAS: vfabs.v v2, v1, v0.t # encoding: [0x57,0x91,0x10,0x28]
# NO-ALIAS: vfsgnjx.vv v2, v1, v1, v0.t # encoding: [0x57,0x91,0x10,0x28]
vfabs.v v2, v1, v0.t