[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices

[dp]

Summary

Corrected invalid opcode suffices.

See bugs 49643, 49644, 49645.

[Joe_Nash]

LGTM

llvm/lib/Target/AMDGPU/VOP2Instructions.td

def _dpp8_w64_gfx10 :
         let WaveSizePredicate = isWave64;
       }
   }
 
   //===----------------------------- VOP3Only -----------------------------===//
   multiclass VOP3Only_Real_gfx10<bits<10> op> {
     def _e64_gfx10 :
       VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
-      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
+      VOP3e_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
+        let IsSingle = 1;
+      }
   }
 
   //===---------------------------- VOP3beOnly ----------------------------===//
   multiclass VOP3beOnly_Real_gfx10<bits<10> op> {
     def _e64_gfx10 :
       VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
-      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
+      VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
+        let IsSingle = 1;
+      }
   }
 } // End AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10"
 
 multiclass VOP2be_Real_gfx10<bits<6> op, string opName, string asmName> :
   VOP2be_Real_e32_gfx10<op, opName, asmName>,
   VOP2be_Real_e64_gfx10<op, opName, asmName>,
   VOP2be_Real_sdwa_gfx10<op, opName, asmName>,
   VOP2be_Real_dpp_gfx10<op, opName, asmName>,

 defm V_SUBREV_F16      : VOP2_Real_gfx10<0x034>;
 defm V_MUL_F16         : VOP2_Real_gfx10<0x035>;
 defm V_FMAC_F16        : VOP2_Real_gfx10<0x036>;
 defm V_FMAMK_F16       : VOP2Only_Real_MADK_gfx10<0x037>;
 defm V_FMAAK_F16       : VOP2Only_Real_MADK_gfx10<0x038>;
 defm V_MAX_F16         : VOP2_Real_gfx10<0x039>;
 defm V_MIN_F16         : VOP2_Real_gfx10<0x03a>;
 defm V_LDEXP_F16       : VOP2_Real_gfx10<0x03b>;
+
+let IsSingle = 1 in {
 defm V_PK_FMAC_F16     : VOP2_Real_e32_gfx10<0x03c>;
+}
 
 // VOP2 no carry-in, carry-out.
 defm V_ADD_NC_U32 :
   VOP2_Real_gfx10_with_name<0x025, "V_ADD_U32", "v_add_nc_u32">;
 defm V_SUB_NC_U32 :
   VOP2_Real_gfx10_with_name<0x026, "V_SUB_U32", "v_sub_nc_u32">;
 defm V_SUBREV_NC_U32 :
   VOP2_Real_gfx10_with_name<0x027, "V_SUBREV_U32", "v_subrev_nc_u32">;
foreach _ = BoolToList<!cast<VOP2_Pseudo>(NAME#"_e32").Pfl.HasExtDPP>.ret in
         VOP2_DPPe<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")> {
           let DecoderNamespace = "SDWA9";
         }
   }
 } // End AssemblerPredicate = isGFX90APlus, DecoderNamespace = "GFX90A"
 
 let SubtargetPredicate = isGFX90APlus in {
   defm V_FMAC_F64       : VOP2_Real_e32e64_gfx90a <0x4>;
+  let IsSingle = 1 in {
     defm V_MUL_LEGACY_F32 : VOP2_Real_e64_gfx90a <0x2a1>;
+  }
 } // End SubtargetPredicate = isGFX90APlus
 
 multiclass VOP2_Real_DOT_ACC_gfx9<bits<6> op> : VOP2_Real_e32_vi<op> {
   def _dpp_vi : VOP2_DPP<op, !cast<VOP2_DPP_Pseudo>(NAME#"_dpp")>;
 }
 
 multiclass VOP2_Real_DOT_ACC_gfx10<bits<6> op> :
   VOP2_Real_e32_gfx10<op>,

llvm/lib/Target/AMDGPU/VOP3Instructions.td

let AssemblerPredicate = isGFX10Plus, DecoderNamespace = "GFX10" in {
   }
   multiclass VOP3_Real_gfx10_with_name<bits<10> op, string opName,
                                        string asmName> {
     def _gfx10 :
       VOP3_Real<!cast<VOP3_Pseudo>(opName#"_e64"), SIEncodingFamily.GFX10>,
       VOP3e_gfx10<op, !cast<VOP3_Pseudo>(opName#"_e64").Pfl> {
         VOP3_Pseudo ps = !cast<VOP3_Pseudo>(opName#"_e64");
         let AsmString = asmName # ps.AsmOperands;
+        let IsSingle = 1;
       }
   }
   multiclass VOP3be_Real_gfx10<bits<10> op> {
     def _gfx10 :
       VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
       VOP3be_gfx10<op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
   }
   multiclass VOP3Interp_Real_gfx10<bits<10> op> {

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_ashr_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
 ; GFX10-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, v1, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = ashr i8 %value, %amount
   ret i8 %result
 }
 
 define i8 @v_ashr_i8_7(i8 %value) {
 ; GFX6-LABEL: v_ashr_i8_7:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_ashrrev_i16_sdwa v0, v1, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_ashr_i8_7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_bfe_i32 v0, v0, 0, 8
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 7, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 7, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = ashr i8 %value, 7
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_ashr_i8(i8 inreg %value, i8 inreg %amount) {
 ; GFX6-LABEL: s_ashr_i8:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, v1, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_ashr_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, v1, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = ashr i16 %value, %amount
   ret i16 %result
 }
 
 define i16 @v_ashr_i16_31(i16 %value) {
 ; GCN-LABEL: v_ashr_i16_31:
 ; GCN:       ; %bb.0:

 ;
 ; GFX9-LABEL: ashr_i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_ashrrev_i16_e64 v0, v0, s0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: ashr_i16_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, v0, s0
+; GFX10-NEXT:    v_ashrrev_i16 v0, v0, s0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = ashr i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define amdgpu_ps half @ashr_i16_vs(i16 %value, i16 inreg %amount) {
 ; GFX6-LABEL: ashr_i16_vs:

 ;
 ; GFX9-LABEL: ashr_i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: ashr_i16_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, s0, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = ashr i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define <2 x i16> @v_ashr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
 ; GFX6-LABEL: v_ashr_v2i16:

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-short-clamp.ll

 ; RUN: llc -global-isel -mcpu=tahiti -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX678,GFX6789 %s
 ; RUN: llc -global-isel -mcpu=gfx900 -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX9,GFX6789 %s
 ; RUN: llc -global-isel -mcpu=gfx1010 -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
 
 declare i64 @llvm.smax.i64(i64, i64)
 declare i64 @llvm.smin.i64(i64, i64)
 
 ; GFX10-LABEL: {{^}}v_clamp_i64_i16
 ; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
 ; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
 ; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
+; GFX10: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX10: v_mov_b32_e32 [[B]], 0x7fff
 ; GFX10: v_med3_i32 [[A]], 0xffff8000, [[A]], [[B]]
 define i16 @v_clamp_i64_i16(i64 %in) #0 {
 entry:
   %max = call i64 @llvm.smax.i64(i64 %in, i64 -32768)
   %min = call i64 @llvm.smin.i64(i64 %max, i64 32767)
   %result = trunc i64 %min to i16
   ret i16 %result
 }
 
 ; GFX10-LABEL: {{^}}v_clamp_i64_i16_reverse
 ; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX6789: v_mov_b32_e32 [[B]], 0xffff8000
 ; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x7fff
 ; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
+; GFX10: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX10: v_mov_b32_e32 [[B]], 0x7fff
 ; GFX10: v_med3_i32 [[A]], 0xffff8000, [[A]], [[B]] 
 define i16 @v_clamp_i64_i16_reverse(i64 %in) #0 {
 entry:
   %min = call i64 @llvm.smin.i64(i64 %in, i64 32767)
   %max = call i64 @llvm.smax.i64(i64 %min, i64 -32768)
   %result = trunc i64 %max to i16
   ret i16 %result

 }
 
 ; GFX10-LABEL: {{^}}v_clamp_i64_i16_lower_than_short
 ; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
 ; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
 ; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
+; GFX10: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX10: v_mov_b32_e32 [[B]], 0x100
 ; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[B]]
 define i16 @v_clamp_i64_i16_lower_than_short(i64 %in) #0 {
 entry:
   %min = call i64 @llvm.smin.i64(i64 %in, i64 256)
   %max = call i64 @llvm.smax.i64(i64 %min, i64 -255)
   %result = trunc i64 %max to i16
   ret i16 %result
 }
 
 ; GFX10-LABEL: {{^}}v_clamp_i64_i16_lower_than_short_reverse
 ; GFX678: v_cvt_pk_i16_i32_e32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX9: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX6789: v_mov_b32_e32 [[B]], 0xffffff01
 ; GFX6789: v_mov_b32_e32 [[C:v[0-9]+]], 0x100
 ; GFX6789: v_med3_i32 [[A]], [[B]], [[A]], [[C]]
-; GFX10: v_cvt_pk_i16_i32_e64 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
+; GFX10: v_cvt_pk_i16_i32 [[A:v[0-9]+]], [[A]], [[B:v[0-9]+]]
 ; GFX10: v_mov_b32_e32 [[B]], 0x100
 ; GFX10: v_med3_i32 [[A]], 0xffffff01, [[A]], [[B]]
 define i16 @v_clamp_i64_i16_lower_than_short_reverse(i64 %in) #0 {
 entry:
   %max = call i64 @llvm.smax.i64(i64 %in, i64 -255)
   %min = call i64 @llvm.smin.i64(i64 %max, i64 256)
   %result = trunc i64 %min to i16
   ret i16 %result

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

 ; GFX10-LABEL: v_extract_v64i32_37:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_movk_i32 s4, 0x80
 ; GFX10-NEXT:    s_mov_b32 s5, 0
 ; GFX10-NEXT:    v_mov_b32_e32 v2, s4
 ; GFX10-NEXT:    v_mov_b32_e32 v3, s5
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    global_load_dwordx4 v[4:7], v[0:1], off offset:16
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v0, v5
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %vec = load <64 x i32>, <64 x i32> addrspace(1)* %ptr
   %elt = extractelement <64 x i32> %vec, i32 37
   ret i32 %elt
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll

 ; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 7
 ; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
 ; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
 ; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX10-NEXT:    v_sub_nc_u16_e64 v1, 6, v0
+; GFX10-NEXT:    v_sub_nc_u16 v1, 6, v0
 ; GFX10-NEXT:    v_and_b32_e32 v0, s3, v0
 ; GFX10-NEXT:    v_and_b32_e32 v1, s3, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v1, s1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v0, s0
+; GFX10-NEXT:    v_lshrrev_b16 v1, v1, s1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.fshl.i7(i7 %lhs, i7 %rhs, i7 %amt)
   ret i7 %result
 }
 
 define i7 @v_fshl_i7(i7 %lhs, i7 %rhs, i7 %amt) {

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
 ; GFX10-NEXT:    s_sub_i32 s4, 0, 7
 ; GFX10-NEXT:    v_and_b32_e32 v2, 0x7f, v2
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0x7f, v1
 ; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 1, v1
+; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
 ; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
 ; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX10-NEXT:    v_mul_lo_u32 v4, s4, v3
 ; GFX10-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v4
 ; GFX10-NEXT:    v_mul_hi_u32 v3, v2, v3
 ; GFX10-NEXT:    v_mul_lo_u32 v3, v3, 7
 ; GFX10-NEXT:    v_sub_nc_u32_e32 v2, v2, v3
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
 ; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
 ; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
 ; GFX10-NEXT:    v_mov_b32_e32 v3, 0x7f
-; GFX10-NEXT:    v_sub_nc_u16_e64 v4, 6, v2
+; GFX10-NEXT:    v_sub_nc_u16 v4, 6, v2
 ; GFX10-NEXT:    v_and_b32_e32 v2, v2, v3
 ; GFX10-NEXT:    v_and_b32_e32 v3, v4, v3
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v2, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v3, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, v3, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.fshl.i7(i7 %lhs, i7 %rhs, i7 %amt)
   ret i7 %result
 }
 
 define amdgpu_ps i8 @s_fshl_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
 ; GFX6-LABEL: s_fshl_i8:

 ; GFX10-LABEL: v_fshl_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
 ; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
 ; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 1, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v2, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v3, v1
+; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, v3, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 %amt)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_fshl_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_fshl_i8_4:

 ; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshl_i8_4:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 4, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 4, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 4, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, 4, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 4)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_fshl_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_fshl_i8_5:

 ; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshl_i8_5:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 5, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 3, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 5, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, 3, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.fshl.i8(i8 %lhs, i8 %rhs, i8 5)
   ret i8 %result
 }
 
 define amdgpu_ps i16 @s_fshl_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 inreg %amt.arg) {
 ; GFX6-LABEL: s_fshl_v2i8:

 ; GFX10-NEXT:    v_xor_b32_e32 v7, -1, v2
 ; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
 ; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v3
 ; GFX10-NEXT:    v_and_b32_e32 v4, s4, v4
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 8, v0
 ; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
 ; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
 ; GFX10-NEXT:    v_and_b32_e32 v6, 7, v6
-; GFX10-NEXT:    v_lshrrev_b16_e64 v4, 1, v4
+; GFX10-NEXT:    v_lshrrev_b16 v4, 1, v4
 ; GFX10-NEXT:    v_and_b32_e32 v7, 7, v7
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 1, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v3, v3, v5
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v2, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v4, v6, v4
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v7, v1
+; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
+; GFX10-NEXT:    v_lshlrev_b16 v3, v3, v5
+; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
+; GFX10-NEXT:    v_lshrrev_b16 v4, v6, v4
+; GFX10-NEXT:    v_lshrrev_b16 v1, v7, v1
 ; GFX10-NEXT:    v_or_b32_e32 v2, v3, v4
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %amt = bitcast i16 %amt.arg to <2 x i8>

 ; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 8, v2
 ; GFX10-NEXT:    v_and_b32_e32 v11, 7, v2
 ; GFX10-NEXT:    v_xor_b32_e32 v10, -1, v2
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v9, 16, v2
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 24, v2
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v11, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, v11, v0
 ; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v8
 ; GFX10-NEXT:    v_and_b32_e32 v8, 7, v8
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 8, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v15, 0xff
 ; GFX10-NEXT:    s_movk_i32 s4, 0xff
 ; GFX10-NEXT:    v_xor_b32_e32 v13, -1, v2
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
 ; GFX10-NEXT:    v_and_b32_e32 v12, s4, v1
 ; GFX10-NEXT:    v_and_b32_e32 v6, s4, v6
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v1, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
-; GFX10-NEXT:    v_lshlrev_b16_e64 v3, v8, v3
+; GFX10-NEXT:    v_lshlrev_b16 v3, v8, v3
 ; GFX10-NEXT:    v_xor_b32_e32 v8, -1, v9
 ; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
 ; GFX10-NEXT:    v_and_b32_e32 v9, 7, v9
 ; GFX10-NEXT:    v_and_b32_e32 v11, 7, v11
-; GFX10-NEXT:    v_lshrrev_b16_e64 v6, 1, v6
+; GFX10-NEXT:    v_lshrrev_b16 v6, 1, v6
 ; GFX10-NEXT:    v_and_b32_e32 v8, 7, v8
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 1, v1
+; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
 ; GFX10-NEXT:    v_and_b32_e32 v13, 7, v13
-; GFX10-NEXT:    v_lshrrev_b16_e64 v7, 1, v7
-; GFX10-NEXT:    v_lshrrev_b16_e64 v6, v11, v6
-; GFX10-NEXT:    v_lshlrev_b16_e64 v2, v2, v5
+; GFX10-NEXT:    v_lshrrev_b16 v7, 1, v7
+; GFX10-NEXT:    v_lshrrev_b16 v6, v11, v6
+; GFX10-NEXT:    v_lshlrev_b16 v2, v2, v5
 ; GFX10-NEXT:    v_and_b32_e32 v10, 7, v10
-; GFX10-NEXT:    v_lshrrev_b16_e64 v12, 1, v12
-; GFX10-NEXT:    v_lshrrev_b16_e64 v5, v13, v7
-; GFX10-NEXT:    v_lshlrev_b16_e64 v4, v9, v4
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v8, v1
+; GFX10-NEXT:    v_lshrrev_b16 v12, 1, v12
+; GFX10-NEXT:    v_lshrrev_b16 v5, v13, v7
+; GFX10-NEXT:    v_lshlrev_b16 v4, v9, v4
+; GFX10-NEXT:    v_lshrrev_b16 v1, v8, v1
 ; GFX10-NEXT:    v_or_b32_e32 v3, v3, v6
-; GFX10-NEXT:    v_lshrrev_b16_e64 v7, v10, v12
+; GFX10-NEXT:    v_lshrrev_b16 v7, v10, v12
 ; GFX10-NEXT:    v_or_b32_e32 v2, v2, v5
 ; GFX10-NEXT:    v_mov_b32_e32 v6, 8
 ; GFX10-NEXT:    v_or_b32_e32 v1, v4, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v7
 ; GFX10-NEXT:    v_and_b32_e32 v2, s4, v2
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v3, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 24, v2

 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshl_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
 ; GFX10-NEXT:    v_and_b32_e32 v2, 15, v2
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 1, v1
+; GFX10-NEXT:    v_lshrrev_b16 v1, 1, v1
 ; GFX10-NEXT:    v_and_b32_e32 v3, 15, v3
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v2, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v3, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, v3, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
   ret i16 %result
 }
 
 define i16 @v_fshl_i16_4(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_fshl_i16_4:

 ; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 12, v1
 ; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshl_i16_4:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 4, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 12, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 4, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, 12, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 4)
   ret i16 %result
 }
 
 define i16 @v_fshl_i16_5(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_fshl_i16_5:

 ; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 11, v1
 ; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshl_i16_5:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 5, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 11, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 5, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, 11, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 5)
   ret i16 %result
 }
 
 define amdgpu_ps half @v_fshl_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt) {
 ; GFX6-LABEL: v_fshl_i16_ssv:

 ; GFX10-LABEL: v_fshl_i16_ssv:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
 ; GFX10-NEXT:    v_and_b32_e32 v0, 15, v0
 ; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
 ; GFX10-NEXT:    s_bfe_u32 s2, 1, 0x100000
 ; GFX10-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX10-NEXT:    s_lshr_b32 s1, s1, s2
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v1, s1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v0, s0
+; GFX10-NEXT:    v_lshrrev_b16 v1, v1, s1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
   %cast.result = bitcast i16 %result to half
   ret half %cast.result
 }
 
 define amdgpu_ps half @v_fshl_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt) {

 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 1, v0
 ; GFX9-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, s1, v0
 ; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: v_fshl_i16_svs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshrrev_b16 v0, 1, v0
 ; GFX10-NEXT:    s_andn2_b32 s2, 15, s1
 ; GFX10-NEXT:    s_and_b32 s1, s1, 15
 ; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, s2, v0
+; GFX10-NEXT:    v_lshrrev_b16 v0, s2, v0
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s1
 ; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
   %cast.result = bitcast i16 %result to half
   ret half %cast.result
 }
 

 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: v_fshl_i16_vss:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_and_b32 s2, s1, 15
 ; GFX10-NEXT:    s_andn2_b32 s1, 15, s1
 ; GFX10-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX10-NEXT:    s_bfe_u32 s3, 1, 0x100000
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, s2, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, s2, v0
 ; GFX10-NEXT:    s_lshr_b32 s0, s0, s3
 ; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
 ; GFX10-NEXT:    s_lshr_b32 s0, s0, s1
 ; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.fshl.i16(i16 %lhs, i16 %rhs, i16 %amt)
   %cast.result = bitcast i16 %result to half
   ret half %cast.result

llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll

 ; GFX10-NEXT:    v_mul_lo_u32 v0, v0, 7
 ; GFX10-NEXT:    v_sub_nc_u32_e32 v0, s2, v0
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
 ; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, 7, v0
 ; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v1, vcc_lo
-; GFX10-NEXT:    v_sub_nc_u16_e64 v1, 6, v0
+; GFX10-NEXT:    v_sub_nc_u16 v1, 6, v0
 ; GFX10-NEXT:    v_and_b32_e32 v0, s3, v0
 ; GFX10-NEXT:    v_and_b32_e32 v1, s3, v1
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, v0, s1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
+; GFX10-NEXT:    v_lshrrev_b16 v0, v0, s1
+; GFX10-NEXT:    v_lshlrev_b16 v1, v1, s0
 ; GFX10-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.fshr.i7(i7 %lhs, i7 %rhs, i7 %amt)
   ret i7 %result
 }
 
 define i7 @v_fshr_i7(i7 %lhs, i7 %rhs, i7 %amt) {

 ;
 ; GFX10-LABEL: v_fshr_i7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v3, 7
 ; GFX10-NEXT:    s_sub_i32 s4, 0, 7
 ; GFX10-NEXT:    v_and_b32_e32 v2, 0x7f, v2
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0x7f, v1
 ; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3
 ; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3
 ; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3
 ; GFX10-NEXT:    v_mul_lo_u32 v4, s4, v3
 ; GFX10-NEXT:    v_mul_hi_u32 v4, v3, v4
 ; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v4
 ; GFX10-NEXT:    v_mul_hi_u32 v3, v2, v3
 ; GFX10-NEXT:    v_mul_lo_u32 v3, v3, 7
 ; GFX10-NEXT:    v_sub_nc_u32_e32 v2, v2, v3
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
 ; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
 ; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, 7, v2
 ; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, 7, v2
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc_lo
 ; GFX10-NEXT:    v_mov_b32_e32 v3, 0x7f
-; GFX10-NEXT:    v_sub_nc_u16_e64 v4, 6, v2
+; GFX10-NEXT:    v_sub_nc_u16 v4, 6, v2
 ; GFX10-NEXT:    v_and_b32_e32 v2, v2, v3
 ; GFX10-NEXT:    v_and_b32_e32 v7, v4, v3
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v2, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v7, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, v2, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v7, v0
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.fshr.i7(i7 %lhs, i7 %rhs, i7 %amt)
   ret i7 %result
 }
 
 define amdgpu_ps i8 @s_fshr_i8(i8 inreg %lhs, i8 inreg %rhs, i8 inreg %amt) {
 ; GFX6-LABEL: s_fshr_i8:

 ;
 ; GFX10-LABEL: v_fshr_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
 ; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
 ; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v2, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v3, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, v2, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v3, v0
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 %amt)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_fshr_i8_4(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_fshr_i8_4:

 ; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshr_i8_4:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 4, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 4, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 4, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, 4, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 4)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_fshr_i8_5(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_fshr_i8_5:

 ; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshr_i8_5:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 3, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 5, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 3, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, 5, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.fshr.i8(i8 %lhs, i8 %rhs, i8 5)
   ret i8 %result
 }
 
 define amdgpu_ps i16 @s_fshr_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg, i16 inreg %amt.arg) {
 ; GFX6-LABEL: s_fshr_v2i8:

 ; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 8, v0
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 8, v1
 ; GFX10-NEXT:    s_movk_i32 s4, 0xff
 ; GFX10-NEXT:    v_and_b32_e32 v7, 7, v2
 ; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v3
 ; GFX10-NEXT:    v_xor_b32_e32 v2, -1, v2
 ; GFX10-NEXT:    v_and_b32_e32 v3, 7, v3
 ; GFX10-NEXT:    v_and_b32_e32 v5, s4, v5
-; GFX10-NEXT:    v_lshlrev_b16_e64 v4, 1, v4
+; GFX10-NEXT:    v_lshlrev_b16 v4, 1, v4
 ; GFX10-NEXT:    v_and_b32_e32 v6, 7, v6
 ; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
 ; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
-; GFX10-NEXT:    v_lshrrev_b16_e64 v3, v3, v5
-; GFX10-NEXT:    v_lshlrev_b16_e64 v4, v6, v4
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v7, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v2, v0
+; GFX10-NEXT:    v_lshrrev_b16 v3, v3, v5
+; GFX10-NEXT:    v_lshlrev_b16 v4, v6, v4
+; GFX10-NEXT:    v_lshrrev_b16 v1, v7, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v2, v0
 ; GFX10-NEXT:    v_or_b32_e32 v2, v4, v3
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v2, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %lhs = bitcast i16 %lhs.arg to <2 x i8>
   %rhs = bitcast i16 %rhs.arg to <2 x i8>
   %amt = bitcast i16 %amt.arg to <2 x i8>

 ; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v0
 ; GFX10-NEXT:    v_xor_b32_e32 v8, -1, v2
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v4, 16, v0
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 24, v0
 ; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v6
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 16, v2
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v12, 24, v2
 ; GFX10-NEXT:    v_and_b32_e32 v15, 7, v8
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
 ; GFX10-NEXT:    v_and_b32_e32 v14, 7, v11
-; GFX10-NEXT:    v_lshlrev_b16_e64 v3, 1, v3
+; GFX10-NEXT:    v_lshlrev_b16 v3, 1, v3
 ; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v10
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 8, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v15, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, v15, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v15, 0xff
-; GFX10-NEXT:    v_lshlrev_b16_e64 v3, v14, v3
+; GFX10-NEXT:    v_lshlrev_b16 v3, v14, v3
 ; GFX10-NEXT:    v_xor_b32_e32 v14, -1, v12
 ; GFX10-NEXT:    s_movk_i32 s4, 0xff
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v9, 24, v1
 ; GFX10-NEXT:    v_and_b32_e32 v8, s4, v1
 ; GFX10-NEXT:    v_and_b32_sdwa v1, v1, v15 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-NEXT:    v_and_b32_e32 v10, 7, v10
 ; GFX10-NEXT:    v_and_b32_e32 v6, 7, v6
 ; GFX10-NEXT:    v_and_b32_e32 v7, s4, v7
 ; GFX10-NEXT:    v_and_b32_e32 v11, 7, v11
-; GFX10-NEXT:    v_lshlrev_b16_e64 v4, 1, v4
+; GFX10-NEXT:    v_lshlrev_b16 v4, 1, v4
 ; GFX10-NEXT:    v_and_b32_e32 v15, 7, v14
-; GFX10-NEXT:    v_lshlrev_b16_e64 v5, 1, v5
+; GFX10-NEXT:    v_lshlrev_b16 v5, 1, v5
 ; GFX10-NEXT:    v_and_b32_e32 v12, 7, v12
 ; GFX10-NEXT:    v_and_b32_e32 v2, 7, v2
-; GFX10-NEXT:    v_lshrrev_b16_e64 v6, v6, v7
-; GFX10-NEXT:    v_lshlrev_b16_e64 v4, v11, v4
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v10, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v5, v15, v5
-; GFX10-NEXT:    v_lshrrev_b16_e64 v7, v12, v9
-; GFX10-NEXT:    v_lshrrev_b16_e64 v2, v2, v8
+; GFX10-NEXT:    v_lshrrev_b16 v6, v6, v7
+; GFX10-NEXT:    v_lshlrev_b16 v4, v11, v4
+; GFX10-NEXT:    v_lshrrev_b16 v1, v10, v1
+; GFX10-NEXT:    v_lshlrev_b16 v5, v15, v5
+; GFX10-NEXT:    v_lshrrev_b16 v7, v12, v9
+; GFX10-NEXT:    v_lshrrev_b16 v2, v2, v8
 ; GFX10-NEXT:    v_or_b32_e32 v3, v3, v6
 ; GFX10-NEXT:    v_or_b32_e32 v1, v4, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v6, 8
 ; GFX10-NEXT:    v_or_b32_e32 v4, v5, v7
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
 ; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, v6, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX10-NEXT:    v_and_b32_e32 v3, s4, v4

 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshr_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
 ; GFX10-NEXT:    v_and_b32_e32 v2, 15, v2
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
 ; GFX10-NEXT:    v_and_b32_e32 v3, 15, v3
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v2, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v3, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, v2, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v3, v0
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
   ret i16 %result
 }
 
 define i16 @v_fshr_i16_4(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_fshr_i16_4:

 ; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 4, v1
 ; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshr_i16_4:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 12, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 4, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 12, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, 4, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 4)
   ret i16 %result
 }
 
 define i16 @v_fshr_i16_5(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_fshr_i16_5:

 ; GFX9-NEXT:    v_lshrrev_b16_e32 v1, 5, v1
 ; GFX9-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_fshr_i16_5:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 11, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, 5, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 11, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, 5, v1
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 5)
   ret i16 %result
 }
 
 define amdgpu_ps half @v_fshr_i16_ssv(i16 inreg %lhs, i16 inreg %rhs, i16 %amt) {
 ; GFX6-LABEL: v_fshr_i16_ssv:

 ;
 ; GFX10-LABEL: v_fshr_i16_ssv:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_xor_b32_e32 v1, -1, v0
 ; GFX10-NEXT:    v_and_b32_e32 v0, 15, v0
 ; GFX10-NEXT:    s_bfe_u32 s2, 1, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX10-NEXT:    v_and_b32_e32 v1, 15, v1
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, v0, s1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, v1, s0
+; GFX10-NEXT:    v_lshrrev_b16 v0, v0, s1
+; GFX10-NEXT:    v_lshlrev_b16 v1, v1, s0
 ; GFX10-NEXT:    v_or_b32_e32 v0, v1, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
   %cast.result = bitcast i16 %result to half
   ret half %cast.result
 }
 
 define amdgpu_ps half @v_fshr_i16_svs(i16 inreg %lhs, i16 %rhs, i16 inreg %amt) {

 ; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: v_fshr_i16_svs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_and_b32 s2, s1, 15
 ; GFX10-NEXT:    s_andn2_b32 s1, 15, s1
 ; GFX10-NEXT:    s_bfe_u32 s3, 1, 0x100000
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, s2, v0
+; GFX10-NEXT:    v_lshrrev_b16 v0, s2, v0
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s3
 ; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s1
 ; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
   %cast.result = bitcast i16 %result to half
   ret half %cast.result

 ; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX9-NEXT:    s_bfe_u32 s1, s2, 0x100000
 ; GFX9-NEXT:    s_lshr_b32 s0, s0, s1
 ; GFX9-NEXT:    v_or_b32_e32 v0, s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: v_fshr_i16_vss:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
 ; GFX10-NEXT:    s_andn2_b32 s2, 15, s1
 ; GFX10-NEXT:    s_and_b32 s1, s1, 15
 ; GFX10-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX10-NEXT:    s_bfe_u32 s1, s1, 0x100000
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, s2, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, s2, v0
 ; GFX10-NEXT:    s_lshr_b32 s0, s0, s1
 ; GFX10-NEXT:    v_or_b32_e32 v0, s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.fshr.i16(i16 %lhs, i16 %rhs, i16 %amt)
   %cast.result = bitcast i16 %result to half
   ret half %cast.result
 }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll

 ; GFX10-NEXT:    v_mov_b32_e32 v6, s1
 ; GFX10-NEXT:    v_mov_b32_e32 v5, s0
 ; GFX10-NEXT:    s_clause 0x4
 ; GFX10-NEXT:    global_load_dwordx4 v[32:35], v70, s[0:1]
 ; GFX10-NEXT:    global_load_dwordx4 v[36:39], v70, s[0:1] offset:16
 ; GFX10-NEXT:    global_load_dwordx4 v[40:43], v70, s[0:1] offset:32
 ; GFX10-NEXT:    global_load_dwordx4 v[44:47], v70, s[0:1] offset:48
 ; GFX10-NEXT:    global_load_dwordx4 v[48:51], v70, s[0:1] offset:64
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v5, v70
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v5, v70
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, 0, v6, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v64, vcc_lo, v0, 64
+; GFX10-NEXT:    v_add_co_u32 v64, vcc_lo, v0, 64
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v65, vcc_lo, 0, v5, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v66, vcc_lo, v0, v1
+; GFX10-NEXT:    v_add_co_u32 v66, vcc_lo, v0, v1
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v67, vcc_lo, v5, v2, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v68, vcc_lo, v0, v3
+; GFX10-NEXT:    v_add_co_u32 v68, vcc_lo, v0, v3
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v69, vcc_lo, v5, v4, vcc_lo
 ; GFX10-NEXT:    s_clause 0xa
 ; GFX10-NEXT:    global_load_dwordx4 v[52:55], v[64:65], off offset:16
 ; GFX10-NEXT:    global_load_dwordx4 v[56:59], v[64:65], off offset:32
 ; GFX10-NEXT:    global_load_dwordx4 v[60:63], v[64:65], off offset:48
 ; GFX10-NEXT:    global_load_dwordx4 v[4:7], v[66:67], off offset:16
 ; GFX10-NEXT:    global_load_dwordx4 v[8:11], v[66:67], off offset:32
 ; GFX10-NEXT:    global_load_dwordx4 v[12:15], v[66:67], off offset:48

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll

 ; GFX10-LABEL: flat_atomic_inc_ret_i32_offset_addr64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v3, 42
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s3
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, 20
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 20
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_atomic_inc v3, v[0:1], v3 glc
 ; GFX10-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s1
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    flat_store_dword v[0:1], v3
 ; GFX10-NEXT:    s_endpgm
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.tid = getelementptr i32, i32* %ptr, i32 %id
   %out.gep = getelementptr i32, i32* %out, i32 %id
   %gep = getelementptr i32, i32* %gep.tid, i32 5

 ;
 ; GFX10-LABEL: flat_atomic_inc_noret_i32_offset_addr64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 2, v0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s1
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 42
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, 20
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 20
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_atomic_inc v0, v[0:1], v2 glc
 ; GFX10-NEXT:    s_endpgm
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.tid = getelementptr i32, i32* %ptr, i32 %id
   %gep = getelementptr i32, i32* %gep.tid, i32 5
   %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
   ret void

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v4, 3, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 42
 ; GFX10-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v8, s3
 ; GFX10-NEXT:    v_mov_b32_e32 v7, s2
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v7, v4
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v7, v4
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v8, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, 40
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 40
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
 ; GFX10-NEXT:    v_mov_b32_e32 v3, s1
 ; GFX10-NEXT:    v_mov_b32_e32 v2, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, v4
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v2, v4
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
 ; GFX10-NEXT:    s_endpgm
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.tid = getelementptr i64, i64* %ptr, i32 %id
   %out.gep = getelementptr i64, i64* %out, i32 %id
   %gep = getelementptr i64, i64* %gep.tid, i32 5

 ;
 ; GFX10-LABEL: flat_atomic_inc_noret_i64_offset_addr64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 3, v0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v0, s0
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s1
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 42
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    v_mov_b32_e32 v3, 0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, 40
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 40
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_atomic_inc_x2 v[0:1], v[0:1], v[2:3] glc
 ; GFX10-NEXT:    s_endpgm
   %id = call i32 @llvm.amdgcn.workitem.id.x()
   %gep.tid = getelementptr i64, i64* %ptr, i32 %id
   %gep = getelementptr i64, i64* %gep.tid, i32 5
   %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
   ret void

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll

 ; GCN-LABEL: global_atomic_csub_offset:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GCN-NEXT:    s_movk_i32 s4, 0x1000
 ; GCN-NEXT:    s_mov_b32 s5, 0
 ; GCN-NEXT:    v_mov_b32_e32 v3, s4
 ; GCN-NEXT:    v_mov_b32_e32 v4, s5
-; GCN-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v3
+; GCN-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v3
 ; GCN-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
 ; GCN-NEXT:    global_atomic_csub v0, v[0:1], v2, off glc
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
   %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
   ret i32 %ret
 }

 ; GCN-LABEL: global_atomic_csub_offset_nortn:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GCN-NEXT:    s_movk_i32 s4, 0x1000
 ; GCN-NEXT:    s_mov_b32 s5, 0
 ; GCN-NEXT:    v_mov_b32_e32 v3, s4
 ; GCN-NEXT:    v_mov_b32_e32 v4, s5
-; GCN-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v3
+; GCN-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v3
 ; GCN-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v4, vcc_lo
 ; GCN-NEXT:    global_atomic_csub v0, v[0:1], v2, off glc
 ; GCN-NEXT:    s_waitcnt vmcnt(0)
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i32, i32 addrspace(1)* %ptr, i64 1024
   %ret = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %gep, i32 %data)
   ret void
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll

 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_lshr_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
 ; GFX10-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, v1, v0
+; GFX10-NEXT:    v_lshrrev_b16 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = lshr i8 %value, %amount
   ret i8 %result
 }
 
 define i8 @v_lshr_i8_7(i8 %value) {
 ; GFX6-LABEL: v_lshr_i8_7:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_lshrrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_lshr_i8_7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_and_b32_e32 v0, 0xff, v0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 7, v0
+; GFX10-NEXT:    v_lshrrev_b16 v0, 7, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = lshr i8 %value, 7
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_lshr_i8(i8 inreg %value, i8 inreg %amount) {
 ; GFX6-LABEL: s_lshr_i8:
 ; GFX6:       ; %bb.0:

 ; GCN-LABEL: v_lshr_i24:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_mov_b32 s4, 0xffffff
 ; GCN-NEXT:    v_and_b32_e32 v1, s4, v1
 ; GCN-NEXT:    v_and_b32_e32 v0, s4, v0
 ; GCN-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_lshr_i24:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    s_mov_b32 s4, 0xffffff
+; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
+; GFX10-NEXT:    v_and_b32_e32 v0, s4, v0
+; GFX10-NEXT:    v_lshrrev_b32_e32 v0, v1, v0
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = lshr i24 %value, %amount
   ret i24 %result
 }
 
 define i24 @v_lshr_i24_7(i24 %value) {
 ; GCN-LABEL: v_lshr_i24_7:
 ; GCN:       ; %bb.0:
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, v1, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_lshr_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, v1, v0
+; GFX10-NEXT:    v_lshrrev_b16 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = lshr i16 %value, %amount
   ret i16 %result
 }
 
 define i16 @v_lshr_i16_31(i16 %value) {
 ; GCN-LABEL: v_lshr_i16_31:
 ; GCN:       ; %bb.0:

 ;
 ; GFX9-LABEL: lshr_i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshrrev_b16_e64 v0, v0, s0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: lshr_i16_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, v0, s0
+; GFX10-NEXT:    v_lshrrev_b16 v0, v0, s0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = lshr i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define amdgpu_ps half @lshr_i16_vs(i16 %value, i16 inreg %amount) {
 ; GFX6-LABEL: lshr_i16_vs:

 ;
 ; GFX9-LABEL: lshr_i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: lshr_i16_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, s0, v0
+; GFX10-NEXT:    v_lshrrev_b16 v0, s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = lshr i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define <2 x i16> @v_lshr_v2i16(<2 x i16> %value, <2 x i16> %amount) {
 ; GFX6-LABEL: v_lshr_v2i16:

llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u16_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_mul_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_mul_lo_u16_e64 v0, v0, v1
+; GFX10-NEXT:    v_mul_lo_u16 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = mul i16 %num, %den
   ret i16 %result
 }
 
 define amdgpu_ps zeroext i16 @s_mul_i16_zeroext(i16 inreg zeroext %num, i16 inreg zeroext %den) {
 ; GFX7-LABEL: s_mul_i16_zeroext:
 ; GFX7:       ; %bb.0:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_mul_lo_u16_e32 v0, v0, v1
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_mul_i16_zeroext:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_mul_lo_u16_e64 v0, v0, v1
+; GFX10-NEXT:    v_mul_lo_u16 v0, v0, v1
 ; GFX10-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = mul i16 %num, %den
   ret i16 %result
 }
 
 define amdgpu_ps signext i16 @s_mul_i16_signext(i16 inreg signext %num, i16 inreg signext %den) {
 ; GFX7-LABEL: s_mul_i16_signext:

 ; GFX9-NEXT:    v_mul_lo_u16_e32 v0, v0, v1
 ; GFX9-NEXT:    v_bfe_i32 v0, v0, 0, 16
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_mul_i16_signext:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_mul_lo_u16_e64 v0, v0, v1
+; GFX10-NEXT:    v_mul_lo_u16 v0, v0, v1
 ; GFX10-NEXT:    v_bfe_i32 v0, v0, 0, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = mul i16 %num, %den
   ret i16 %result
 }
 
 define amdgpu_ps i32 @s_mul_i32(i32 inreg %num, i32 inreg %den) {
 ; GCN-LABEL: s_mul_i32:

 ; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc
 ; GFX9-NEXT:    v_add_u32_e32 v2, v2, v10
 ; GFX9-NEXT:    v_add_u32_e32 v3, v8, v9
 ; GFX9-NEXT:    v_add3_u32 v1, v2, v5, v1
 ; GFX9-NEXT:    v_add3_u32 v2, v1, v0, v3
 ; GFX9-NEXT:    v_mov_b32_e32 v0, v6
 ; GFX9-NEXT:    v_mov_b32_e32 v1, v7
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_i96:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_mul_lo_u32 v6, v1, v3
+; GFX10-NEXT:    v_mul_lo_u32 v7, v0, v4
+; GFX10-NEXT:    v_mul_hi_u32 v8, v0, v3
+; GFX10-NEXT:    v_mul_lo_u32 v9, v1, v4
+; GFX10-NEXT:    v_mul_lo_u32 v2, v2, v3
+; GFX10-NEXT:    v_mul_lo_u32 v5, v0, v5
+; GFX10-NEXT:    v_mul_hi_u32 v4, v0, v4
+; GFX10-NEXT:    v_mul_lo_u32 v0, v0, v3
+; GFX10-NEXT:    v_add_co_u32 v6, s4, v6, v7
+; GFX10-NEXT:    v_mul_hi_u32 v7, v1, v3
+; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s4
+; GFX10-NEXT:    v_add_nc_u32_e32 v2, v2, v9
+; GFX10-NEXT:    v_add_co_u32 v1, s4, v6, v8
+; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s4
+; GFX10-NEXT:    v_add3_u32 v2, v2, v5, v7
+; GFX10-NEXT:    v_add_nc_u32_e32 v3, v11, v6
+; GFX10-NEXT:    v_add3_u32 v2, v2, v4, v3
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = mul i96 %num, %den
   ret i96 %result
 }
 
 define amdgpu_ps <4 x i32> @s_mul_i128(i128 inreg %num, i128 inreg %den) {
 ; GFX7-LABEL: s_mul_i128:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    v_mov_b32_e32 v0, s4

 ; GFX9-NEXT:    v_add_u32_e32 v3, v3, v12
 ; GFX9-NEXT:    v_add3_u32 v3, v3, v13, v7
 ; GFX9-NEXT:    v_add3_u32 v1, v3, v2, v1
 ; GFX9-NEXT:    v_add3_u32 v3, v1, v0, v11
 ; GFX9-NEXT:    v_mov_b32_e32 v0, v8
 ; GFX9-NEXT:    v_mov_b32_e32 v1, v9
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v10
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_i128:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_mul_lo_u32 v8, v2, v4
+; GFX10-NEXT:    v_mul_lo_u32 v9, v1, v5
+; GFX10-NEXT:    v_mul_lo_u32 v10, v1, v4
+; GFX10-NEXT:    v_mul_lo_u32 v11, v0, v5
+; GFX10-NEXT:    v_mul_hi_u32 v12, v0, v4
+; GFX10-NEXT:    v_mul_lo_u32 v13, v0, v6
+; GFX10-NEXT:    v_mul_hi_u32 v15, v0, v5
+; GFX10-NEXT:    v_mul_lo_u32 v3, v3, v4
+; GFX10-NEXT:    v_mul_lo_u32 v7, v0, v7
+; GFX10-NEXT:    v_add_co_u32 v8, s4, v8, v9
+; GFX10-NEXT:    v_add_co_u32 v9, s5, v10, v11
+; GFX10-NEXT:    v_mul_hi_u32 v11, v1, v4
+; GFX10-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s5
+; GFX10-NEXT:    v_add_co_u32 v13, s4, v8, v13
+; GFX10-NEXT:    v_add_co_u32 v8, s5, v9, v12
+; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s5
+; GFX10-NEXT:    v_add_co_u32 v18, s4, v13, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s4
+; GFX10-NEXT:    v_add_nc_u32_e32 v9, v10, v9
+; GFX10-NEXT:    v_mul_lo_u32 v10, v2, v5
+; GFX10-NEXT:    v_add_co_u32 v11, s4, v18, v15
+; GFX10-NEXT:    v_mul_hi_u32 v15, v2, v4
+; GFX10-NEXT:    v_add3_u32 v12, v14, v12, v13
+; GFX10-NEXT:    v_mul_lo_u32 v13, v1, v6
+; GFX10-NEXT:    v_mul_hi_u32 v1, v1, v5
+; GFX10-NEXT:    v_cndmask_b32_e64 v14, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v2, s4, v11, v9
+; GFX10-NEXT:    v_add_nc_u32_e32 v10, v3, v10
+; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s4
+; GFX10-NEXT:    v_mul_hi_u32 v6, v0, v6
+; GFX10-NEXT:    v_mul_lo_u32 v0, v0, v4
+; GFX10-NEXT:    v_add3_u32 v10, v10, v13, v7
+; GFX10-NEXT:    v_add3_u32 v4, v12, v14, v5
+; GFX10-NEXT:    v_add3_u32 v1, v10, v15, v1
+; GFX10-NEXT:    v_add3_u32 v3, v1, v6, v4
+; GFX10-NEXT:    v_mov_b32_e32 v1, v8
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = mul i128 %num, %den
   ret i128 %result
 }
 
 define amdgpu_ps <8 x i32> @s_mul_i256(i256 inreg %num, i256 inreg %den) {
 ; GFX7-LABEL: s_mul_i256:
 ; GFX7:       ; %bb.0:
 ; GFX7-NEXT:    v_mov_b32_e32 v0, s8

 ; GFX9-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX9-NEXT:    v_mov_b32_e32 v1, v16
 ; GFX9-NEXT:    v_mov_b32_e32 v2, v17
 ; GFX9-NEXT:    v_mov_b32_e32 v3, v18
 ; GFX9-NEXT:    v_mov_b32_e32 v4, v19
 ; GFX9-NEXT:    v_mov_b32_e32 v5, v20
 ; GFX9-NEXT:    v_mov_b32_e32 v6, v21
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_mul_i256:
+; GFX10:       ; %bb.0:
+; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
+; GFX10-NEXT:    v_mul_lo_u32 v16, v1, v8
+; GFX10-NEXT:    v_mul_lo_u32 v17, v0, v9
+; GFX10-NEXT:    v_mul_hi_u32 v18, v0, v8
+; GFX10-NEXT:    v_mul_lo_u32 v19, v2, v8
+; GFX10-NEXT:    v_mul_lo_u32 v20, v1, v9
+; GFX10-NEXT:    v_mul_hi_u32 v21, v1, v8
+; GFX10-NEXT:    v_mul_lo_u32 v22, v3, v8
+; GFX10-NEXT:    v_mul_lo_u32 v25, v1, v10
+; GFX10-NEXT:    v_mul_hi_u32 v23, v0, v9
+; GFX10-NEXT:    v_add_co_u32 v16, s4, v16, v17
+; GFX10-NEXT:    v_mul_hi_u32 v27, v0, v10
+; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, s4
+; GFX10-NEXT:    v_mul_lo_u32 v7, v7, v8
+; GFX10-NEXT:    v_mul_lo_u32 v15, v0, v15
+; GFX10-NEXT:    v_add_co_u32 v16, s4, v16, v18
+; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v19, s4, v19, v20
+; GFX10-NEXT:    v_mul_lo_u32 v20, v2, v9
+; GFX10-NEXT:    v_cndmask_b32_e64 v24, 0, 1, s4
+; GFX10-NEXT:    v_add_nc_u32_e32 v17, v17, v18
+; GFX10-NEXT:    v_mul_lo_u32 v18, v0, v10
+; GFX10-NEXT:    v_add_co_u32 v18, s4, v19, v18
+; GFX10-NEXT:    v_cndmask_b32_e64 v19, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v20, s4, v22, v20
+; GFX10-NEXT:    v_mul_lo_u32 v22, v0, v11
+; GFX10-NEXT:    v_add_co_u32 v18, s5, v18, v21
+; GFX10-NEXT:    v_cndmask_b32_e64 v26, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v21, 0, 1, s5
+; GFX10-NEXT:    v_add_co_u32 v20, s4, v20, v25
+; GFX10-NEXT:    v_add_co_u32 v18, s5, v18, v23
+; GFX10-NEXT:    v_mul_hi_u32 v23, v1, v9
+; GFX10-NEXT:    v_add3_u32 v19, v24, v19, v21
+; GFX10-NEXT:    v_mul_hi_u32 v21, v2, v8
+; GFX10-NEXT:    v_cndmask_b32_e64 v24, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v20, s4, v20, v22
+; GFX10-NEXT:    v_cndmask_b32_e64 v29, 0, 1, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v25, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v17, s5, v18, v17
+; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, 1, s5
+; GFX10-NEXT:    v_add_co_u32 v20, s4, v20, v21
+; GFX10-NEXT:    v_add3_u32 v21, v26, v24, v25
+; GFX10-NEXT:    v_cndmask_b32_e64 v24, 0, 1, s4
+; GFX10-NEXT:    v_mul_lo_u32 v25, v4, v8
+; GFX10-NEXT:    v_mul_lo_u32 v26, v3, v9
+; GFX10-NEXT:    v_add_co_u32 v20, s4, v20, v23
+; GFX10-NEXT:    v_add3_u32 v18, v19, v29, v18
+; GFX10-NEXT:    v_cndmask_b32_e64 v23, 0, 1, s4
+; GFX10-NEXT:    v_mul_hi_u32 v29, v3, v9
+; GFX10-NEXT:    v_add_co_u32 v20, s5, v20, v27
+; GFX10-NEXT:    v_add3_u32 v30, v21, v24, v23
+; GFX10-NEXT:    v_mul_lo_u32 v21, v2, v10
+; GFX10-NEXT:    v_add_co_u32 v22, s4, v25, v26
+; GFX10-NEXT:    v_mul_lo_u32 v24, v1, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v25, 0, 1, s4
+; GFX10-NEXT:    v_mul_hi_u32 v26, v3, v8
+; GFX10-NEXT:    v_cndmask_b32_e64 v23, 0, 1, s5
+; GFX10-NEXT:    v_add_co_u32 v21, s4, v22, v21
+; GFX10-NEXT:    v_mul_lo_u32 v22, v0, v12
+; GFX10-NEXT:    v_cndmask_b32_e64 v27, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v21, s4, v21, v24
+; GFX10-NEXT:    v_cndmask_b32_e64 v24, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v18, s4, v20, v18
+; GFX10-NEXT:    v_cndmask_b32_e64 v20, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v21, s4, v21, v22
+; GFX10-NEXT:    v_mul_hi_u32 v22, v2, v9
+; GFX10-NEXT:    v_add3_u32 v24, v25, v27, v24
+; GFX10-NEXT:    v_cndmask_b32_e64 v25, 0, 1, s4
+; GFX10-NEXT:    v_add3_u32 v19, v30, v23, v20
+; GFX10-NEXT:    v_add_co_u32 v21, s4, v21, v26
+; GFX10-NEXT:    v_mul_hi_u32 v20, v1, v10
+; GFX10-NEXT:    v_cndmask_b32_e64 v26, 0, 1, s4
+; GFX10-NEXT:    v_mul_hi_u32 v27, v0, v11
+; GFX10-NEXT:    v_add_co_u32 v21, s4, v21, v22
+; GFX10-NEXT:    v_mul_lo_u32 v22, v5, v8
+; GFX10-NEXT:    v_add3_u32 v23, v24, v25, v26
+; GFX10-NEXT:    v_mul_lo_u32 v24, v4, v9
+; GFX10-NEXT:    v_cndmask_b32_e64 v30, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v20, s4, v21, v20
+; GFX10-NEXT:    v_mul_lo_u32 v26, v3, v10
+; GFX10-NEXT:    v_cndmask_b32_e64 v21, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v20, s5, v20, v27
+; GFX10-NEXT:    v_add_co_u32 v31, s4, v22, v24
+; GFX10-NEXT:    v_add3_u32 v35, v23, v30, v21
+; GFX10-NEXT:    v_mul_lo_u32 v23, v2, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v34, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v25, 0, 1, s5
+; GFX10-NEXT:    v_add_co_u32 v22, s4, v31, v26
+; GFX10-NEXT:    v_mul_lo_u32 v26, v1, v12
+; GFX10-NEXT:    v_cndmask_b32_e64 v27, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v19, s5, v20, v19
+; GFX10-NEXT:    v_add_co_u32 v31, s4, v22, v23
+; GFX10-NEXT:    v_mul_lo_u32 v23, v0, v13
+; GFX10-NEXT:    v_cndmask_b32_e64 v28, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v20, 0, 1, s5
+; GFX10-NEXT:    v_add_co_u32 v22, s4, v31, v26
+; GFX10-NEXT:    v_mul_hi_u32 v26, v4, v8
+; GFX10-NEXT:    v_cndmask_b32_e64 v30, 0, 1, s4
+; GFX10-NEXT:    v_add3_u32 v20, v35, v25, v20
+; GFX10-NEXT:    v_add_co_u32 v31, s4, v22, v23
+; GFX10-NEXT:    v_add3_u32 v23, v34, v27, v28
+; GFX10-NEXT:    v_cndmask_b32_e64 v24, 0, 1, s4
+; GFX10-NEXT:    v_mul_hi_u32 v22, v2, v10
+; GFX10-NEXT:    v_mul_lo_u32 v28, v5, v9
+; GFX10-NEXT:    v_add_co_u32 v27, s4, v31, v26
+; GFX10-NEXT:    v_mul_hi_u32 v26, v1, v11
+; GFX10-NEXT:    v_add3_u32 v23, v23, v30, v24
+; GFX10-NEXT:    v_cndmask_b32_e64 v24, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v21, s4, v27, v29
+; GFX10-NEXT:    v_mul_lo_u32 v27, v6, v8
+; GFX10-NEXT:    v_cndmask_b32_e64 v25, 0, 1, s4
+; GFX10-NEXT:    v_mul_hi_u32 v29, v0, v12
+; GFX10-NEXT:    v_add_co_u32 v21, s4, v21, v22
+; GFX10-NEXT:    v_add3_u32 v23, v23, v24, v25
+; GFX10-NEXT:    v_mul_lo_u32 v24, v4, v10
+; GFX10-NEXT:    v_cndmask_b32_e64 v33, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v25, s4, v27, v28
+; GFX10-NEXT:    v_add_co_u32 v31, s5, v21, v26
+; GFX10-NEXT:    v_mul_lo_u32 v27, v3, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v26, 0, 1, s5
+; GFX10-NEXT:    v_cndmask_b32_e64 v28, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v24, s4, v25, v24
+; GFX10-NEXT:    v_add_co_u32 v21, s5, v31, v29
+; GFX10-NEXT:    v_add3_u32 v39, v23, v33, v26
+; GFX10-NEXT:    v_mul_lo_u32 v23, v2, v12
+; GFX10-NEXT:    v_cndmask_b32_e64 v35, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v24, s4, v24, v27
+; GFX10-NEXT:    v_mul_lo_u32 v27, v1, v13
+; GFX10-NEXT:    v_cndmask_b32_e64 v29, 0, 1, s4
+; GFX10-NEXT:    v_mul_hi_u32 v31, v4, v9
+; GFX10-NEXT:    v_mul_hi_u32 v25, v3, v10
+; GFX10-NEXT:    v_cndmask_b32_e64 v26, 0, 1, s5
+; GFX10-NEXT:    v_add_co_u32 v34, s4, v24, v23
+; GFX10-NEXT:    v_mul_lo_u32 v24, v0, v14
+; GFX10-NEXT:    v_cndmask_b32_e64 v30, 0, 1, s4
+; GFX10-NEXT:    v_add3_u32 v35, v28, v35, v29
+; GFX10-NEXT:    v_add_co_u32 v20, s5, v21, v20
+; GFX10-NEXT:    v_add_co_u32 v23, s4, v34, v27
+; GFX10-NEXT:    v_mul_hi_u32 v27, v5, v8
+; GFX10-NEXT:    v_cndmask_b32_e64 v32, 0, 1, s4
+; GFX10-NEXT:    v_cndmask_b32_e64 v21, 0, 1, s5
+; GFX10-NEXT:    v_mul_lo_u32 v29, v3, v12
+; GFX10-NEXT:    v_add_co_u32 v34, s4, v23, v24
+; GFX10-NEXT:    v_mul_hi_u32 v3, v3, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v28, 0, 1, s4
+; GFX10-NEXT:    v_add3_u32 v22, v35, v30, v32
+; GFX10-NEXT:    v_add3_u32 v21, v39, v26, v21
+; GFX10-NEXT:    v_add_co_u32 v34, s4, v34, v27
+; GFX10-NEXT:    v_mul_hi_u32 v26, v2, v11
+; GFX10-NEXT:    v_cndmask_b32_e64 v27, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v23, s4, v34, v31
+; GFX10-NEXT:    v_cndmask_b32_e64 v24, 0, 1, s4
+; GFX10-NEXT:    v_add3_u32 v22, v22, v28, v27
+; GFX10-NEXT:    v_mul_lo_u32 v28, v6, v9
+; GFX10-NEXT:    v_add_co_u32 v23, s4, v23, v25
+; GFX10-NEXT:    v_mul_hi_u32 v27, v1, v12
+; GFX10-NEXT:    v_cndmask_b32_e64 v25, 0, 1, s4
+; GFX10-NEXT:    v_mul_hi_u32 v6, v6, v8
+; GFX10-NEXT:    v_add_co_u32 v30, s4, v23, v26
+; GFX10-NEXT:    v_add3_u32 v33, v22, v24, v25
+; GFX10-NEXT:    v_mul_lo_u32 v24, v5, v10
+; GFX10-NEXT:    v_mul_lo_u32 v25, v4, v11
+; GFX10-NEXT:    v_add_nc_u32_e32 v7, v7, v28
+; GFX10-NEXT:    v_mul_lo_u32 v28, v2, v13
+; GFX10-NEXT:    v_cndmask_b32_e64 v26, 0, 1, s4
+; GFX10-NEXT:    v_add_co_u32 v23, s4, v30, v27
+; GFX10-NEXT:    v_mul_hi_u32 v5, v5, v9
+; GFX10-NEXT:    v_cndmask_b32_e64 v27, 0, 1, s4
+; GFX10-NEXT:    v_mul_hi_u32 v4, v4, v10
+; GFX10-NEXT:    v_add3_u32 v7, v7, v24, v25
+; GFX10-NEXT:    v_mul_lo_u32 v24, v1, v14
+; GFX10-NEXT:    v_mul_hi_u32 v25, v0, v13
+; GFX10-NEXT:    v_add3_u32 v33, v33, v26, v27
+; GFX10-NEXT:    v_mul_hi_u32 v2, v2, v12
+; GFX10-NEXT:    v_add3_u32 v26, v7, v29, v28
+; GFX10-NEXT:    v_mul_hi_u32 v1, v1, v13
+; GFX10-NEXT:    v_add3_u32 v7, v26, v24, v15
+; GFX10-NEXT:    v_add_co_u32 v11, s4, v23, v25
+; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s4
+; GFX10-NEXT:    v_add3_u32 v5, v7, v6, v5
+; GFX10-NEXT:    v_add_co_u32 v6, s4, v11, v21
+; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s4
+; GFX10-NEXT:    v_add3_u32 v3, v5, v4, v3
+; GFX10-NEXT:    v_mul_hi_u32 v4, v0, v14
+; GFX10-NEXT:    v_mul_lo_u32 v0, v0, v8
+; GFX10-NEXT:    v_add3_u32 v5, v33, v10, v7
+; GFX10-NEXT:    v_add3_u32 v3, v3, v2, v1
+; GFX10-NEXT:    v_mov_b32_e32 v1, v16
+; GFX10-NEXT:    v_mov_b32_e32 v2, v17
+; GFX10-NEXT:    v_add3_u32 v7, v3, v4, v5
+; GFX10-NEXT:    v_mov_b32_e32 v3, v18
+; GFX10-NEXT:    v_mov_b32_e32 v4, v19
+; GFX10-NEXT:    v_mov_b32_e32 v5, v20
+; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = mul i256 %num, %den
   ret i256 %result
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

 ; GFX9-NEXT:    v_add_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 9, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_saddsat_i7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 9, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 9, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 9, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 9, v1
 ; GFX10-NEXT:    v_add_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 9, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 9, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define amdgpu_ps i7 @s_saddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_i7:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_saddsat_i7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_bfe_u32 s2, 9, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX10-NEXT:    v_add_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 9, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 9, v0
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.sadd.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define i8 @v_saddsat_i8(i8 %lhs, i8 %rhs) {
 ; GFX6-LABEL: v_saddsat_i8:

 ; GFX9-NEXT:    v_add_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_saddsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 8, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
 ; GFX10-NEXT:    v_add_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_saddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_saddsat_i8:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_saddsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX10-NEXT:    v_add_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_saddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
 ; GFX6-LABEL: v_saddsat_v2i8:

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_saddsat_i64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v10, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_u32 v10, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 31, v11
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s5, v6, 0
+; GFX10-NEXT:    v_add_co_u32 v0, s5, v6, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s4
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }

 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, s[2:3], v0, v1, s[2:3]
 ; GFX9-NEXT:    s_xor_b64 vcc, s[0:1], vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: saddsat_i64_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, s0, v0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[0:1]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s1, v4, 0
+; GFX10-NEXT:    v_add_co_u32 v0, s1, v4, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast

 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, s[0:1], v0, v1, s[0:1]
 ; GFX9-NEXT:    s_xor_b64 vcc, s[2:3], vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: saddsat_i64_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v0, s0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s1, s[0:1], 0
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, v4, 0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, v4, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.sadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v14, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v15, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v17, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v18, v3
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s4, 0, v[4:5]
-; GFX10-NEXT:    v_add_co_u32_e64 v8, vcc_lo, v14, v4
+; GFX10-NEXT:    v_add_co_u32 v8, vcc_lo, v14, v4
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s6, 0, v[6:7]
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, v15, v5, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v19, vcc_lo, v17, v6
+; GFX10-NEXT:    v_add_co_u32 v19, vcc_lo, v17, v6
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v12, 31, v9
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[14:15]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
-; GFX10-NEXT:    v_add_co_u32_e64 v1, s5, v12, 0
+; GFX10-NEXT:    v_add_co_u32 v1, s5, v12, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v4, s5, 0x80000000, v12, s5
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
-; GFX10-NEXT:    v_add_co_u32_e64 v2, s7, v0, 0
+; GFX10-NEXT:    v_add_co_u32 v2, s7, v0, 0
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s7, 0x80000000, v0, s7
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: saddsat_i128_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v4, vcc_lo, s0, v0
+; GFX10-NEXT:    v_add_co_u32 v4, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
 ; GFX10-NEXT:    s_movk_i32 s0, 0x7f
 ; GFX10-NEXT:    s_sub_i32 s1, 64, s0
 ; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s0, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo

 ; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
 ; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v0, s0
 ; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v15, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, v2, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, v3, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v8, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v9, s0

 ;
 ; GFX10-LABEL: saddsat_i128_vs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_mov_b32_e32 v5, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v6, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v9, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v10, v3
 ; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT:    v_add_co_u32_e64 v15, vcc_lo, v5, s0
+; GFX10-NEXT:    v_add_co_u32 v15, vcc_lo, v5, s0
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s0, s[0:1], 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v16, vcc_lo, s1, v6, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v19, vcc_lo, s2, v9, vcc_lo
 ; GFX10-NEXT:    s_and_b32 s1, 1, s4
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, s3, v10, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[15:16], v[5:6]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0

 ; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
 ; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v15, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v16, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v7, v0, s0
 ; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v7, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v2, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v16, v3, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v19, v8, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v20, v9, s0

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v22, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v23, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v20, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v21, v3
 ; GFX10-NEXT:    s_movk_i32 s5, 0x7f
-; GFX10-NEXT:    v_add_co_u32_e64 v16, vcc_lo, v22, v8
+; GFX10-NEXT:    v_add_co_u32 v16, vcc_lo, v22, v8
 ; GFX10-NEXT:    s_sub_i32 s6, 64, s5
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v17, vcc_lo, v23, v9, vcc_lo
 ; GFX10-NEXT:    s_sub_i32 s7, s5, 64
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v18, vcc_lo, v20, v10, vcc_lo
 ; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v19, vcc_lo, v21, v11, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[22:23]
 ; GFX10-NEXT:    v_mov_b32_e32 v26, v4

 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s8
 ; GFX10-NEXT:    v_xor_b32_e32 v9, v10, v20
 ; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v16, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v17, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v11, v0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v11, v1, s4
 ; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX10-NEXT:    v_add_co_u32_e64 v8, s4, v26, v12
+; GFX10-NEXT:    v_add_co_u32 v8, s4, v26, v12
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v9, s4, v27, v13, s4
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v10, s4, v24, v14, s4
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v11, s4, v25, v15, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[8:9], v[26:27]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v20, vcc_lo
 ; GFX10-NEXT:    v_lshrrev_b64 v[3:4], s5, v[8:9]

 ; GFX10-NEXT:    v_xor_b32_e32 v7, v14, v7
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v18, 31, v11
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s6
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s4
 ; GFX10-NEXT:    v_and_b32_e32 v7, 1, v7
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v18, v3, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v18, v4, s5
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s4, v5, 0
+; GFX10-NEXT:    v_add_co_u32 v5, s4, v5, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s4, 0, v6, s4
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, v7
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s4, 0, v3, s4
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v21, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s5

llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll

 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    v_and_b32_e32 v0, 6, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX10-NEXT:    v_mul_u32_u24_e32 v0, 7, v0
 ; GFX10-NEXT:    v_lshlrev_b64 v[2:3], 2, v[0:1]
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v5, s1
 ; GFX10-NEXT:    v_mov_b32_e32 v4, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v4, v2
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v4, v2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo
 ; GFX10-NEXT:    global_store_dword v[2:3], v1, off
 ; GFX10-NEXT:    s_endpgm
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp1 = and i32 %tmp, 6
   %mulconv = mul nuw nsw i32 %tmp1, 7
   %tmp2 = zext i32 %mulconv to i64

 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 2, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_shl_i32_zext_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_and_b32_e32 v0, 0x3fff, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 2, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 2, v0
 ; GFX10-NEXT:    v_bfe_u32 v0, v0, 0, 16
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %and = and i16 %x, 16383
   %ext = zext i16 %and to i32
   %shl = shl i32 %ext, 2
   ret i32 %shl
 }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

 ; GFX9-NEXT:    v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_shl_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xff, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = shl i8 %value, %amount
   ret i8 %result
 }
 
 define i8 @v_shl_i8_7(i8 %value) {
 ; GFX6-LABEL: v_shl_i8_7:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 7, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_shl_i8_7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 7, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 7, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = shl i8 %value, 7
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_shl_i8(i8 inreg %value, i8 inreg %amount) {
 ; GFX6-LABEL: s_shl_i8:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, v1, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_shl_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, v1, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = shl i16 %value, %amount
   ret i16 %result
 }
 
 define i16 @v_shl_i16_31(i16 %value) {
 ; GCN-LABEL: v_shl_i16_31:
 ; GCN:       ; %bb.0:

 ;
 ; GFX9-LABEL: shl_i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: shl_i16_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v0, s0
+; GFX10-NEXT:    v_lshlrev_b16 v0, v0, s0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = shl i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define amdgpu_ps half @shl_i16_vs(i16 %value, i16 inreg %amount) {
 ; GFX6-LABEL: shl_i16_vs:

 ;
 ; GFX9-LABEL: shl_i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_lshlrev_b16_e32 v0, s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: shl_i16_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, s0, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = shl i16 %value, %amount
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) {
 ; GFX6-LABEL: v_shl_v2i16:

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

 ; GFX9-NEXT:    v_sub_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 9, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_ssubsat_i7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 9, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 9, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 9, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 9, v1
 ; GFX10-NEXT:    v_sub_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 9, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 9, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_i7:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_ssubsat_i7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_bfe_u32 s2, 9, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX10-NEXT:    v_sub_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 9, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 9, v0
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {
 ; GFX6-LABEL: v_ssubsat_i8:

 ; GFX9-NEXT:    v_sub_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_ssubsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 8, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
 ; GFX10-NEXT:    v_sub_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_ssubsat_i8:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_ssubsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
 ; GFX10-NEXT:    v_sub_nc_i16 v0, s0, s1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
 ; GFX6-LABEL: v_ssubsat_v2i8:

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_ssubsat_i64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_co_u32_e64 v10, vcc_lo, v0, v2
+; GFX10-NEXT:    v_sub_co_u32 v10, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v11, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 31, v11
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, v[10:11], v[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s5, v6, 0
+; GFX10-NEXT:    v_add_co_u32 v0, s5, v6, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s4
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v11, v1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }

 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, s[2:3], v0, v1, s[2:3]
 ; GFX9-NEXT:    s_xor_b64 vcc, s[0:1], vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: ssubsat_i64_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32_e64 v2, vcc_lo, s0, v0
+; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, 0, v[0:1]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s1, v4, 0
+; GFX10-NEXT:    v_add_co_u32 v0, s1, v4, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, vcc_lo, s0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast

 ; GFX9-NEXT:    v_addc_co_u32_e64 v1, s[0:1], v0, v1, s[0:1]
 ; GFX9-NEXT:    s_xor_b64 vcc, s[2:3], vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: ssubsat_i64_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32_e64 v2, vcc_lo, v0, s0
+; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s1, s[0:1], 0
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v3
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, v4, 0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, v4, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v14, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v15, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v17, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v18, v3
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, 0, v[4:5]
-; GFX10-NEXT:    v_sub_co_u32_e64 v8, vcc_lo, v14, v4
+; GFX10-NEXT:    v_sub_co_u32 v8, vcc_lo, v14, v4
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s6, 0, v[6:7]
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v9, vcc_lo, v15, v5, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32_e64 v19, vcc_lo, v17, v6
+; GFX10-NEXT:    v_sub_co_u32 v19, vcc_lo, v17, v6
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v12, 31, v9
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[14:15]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v20
-; GFX10-NEXT:    v_add_co_u32_e64 v1, s5, v12, 0
+; GFX10-NEXT:    v_add_co_u32 v1, s5, v12, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v4, s5, 0x80000000, v12, s5
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
-; GFX10-NEXT:    v_add_co_u32_e64 v2, s7, v0, 0
+; GFX10-NEXT:    v_add_co_u32 v2, s7, v0, 0
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s7, 0x80000000, v0, s7
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc_lo
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v19, v2, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v20, v3, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: ssubsat_i128_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32_e64 v4, vcc_lo, s0, v0
+; GFX10-NEXT:    v_sub_co_u32 v4, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
 ; GFX10-NEXT:    s_movk_i32 s0, 0x7f
 ; GFX10-NEXT:    s_sub_i32 s1, 64, s0
 ; GFX10-NEXT:    v_lshrrev_b64 v[15:16], s0, v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo

 ; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
 ; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v5, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v0, s0
 ; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v15, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, v2, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, v3, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v8, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v7, v9, s0

 ;
 ; GFX10-LABEL: ssubsat_i128_vs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_mov_b32_e32 v5, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v6, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v9, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v10, v3
 ; GFX10-NEXT:    s_cmp_eq_u64 s[2:3], 0
-; GFX10-NEXT:    v_sub_co_u32_e64 v15, vcc_lo, v5, s0
+; GFX10-NEXT:    v_sub_co_u32 v15, vcc_lo, v5, s0
 ; GFX10-NEXT:    v_cmp_gt_u64_e64 s0, s[0:1], 0
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v16, vcc_lo, s1, v6, vcc_lo
 ; GFX10-NEXT:    s_cselect_b32 s4, 1, 0
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v19, vcc_lo, s2, v9, vcc_lo
 ; GFX10-NEXT:    s_and_b32 s1, 1, s4
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v20, vcc_lo, s3, v10, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[15:16], v[5:6]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s0

 ; GFX10-NEXT:    v_cmp_ne_u32_e64 vcc_lo, 0, s0
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, s1
 ; GFX10-NEXT:    v_xor_b32_e32 v9, v11, v10
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v15, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v16, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v7, v0, s0
 ; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v7, v1, s0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v8
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, 0, v0, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v15, v2, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v16, v3, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v19, v8, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v20, v9, s0

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v22, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v23, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v20, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v21, v3
 ; GFX10-NEXT:    s_movk_i32 s5, 0x7f
-; GFX10-NEXT:    v_sub_co_u32_e64 v16, vcc_lo, v22, v8
+; GFX10-NEXT:    v_sub_co_u32 v16, vcc_lo, v22, v8
 ; GFX10-NEXT:    s_sub_i32 s6, 64, s5
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v17, vcc_lo, v23, v9, vcc_lo
 ; GFX10-NEXT:    s_sub_i32 s7, s5, 64
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v18, vcc_lo, v20, v10, vcc_lo
 ; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v19, vcc_lo, v21, v11, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[22:23]
 ; GFX10-NEXT:    v_mov_b32_e32 v26, v4

 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, s8
 ; GFX10-NEXT:    v_xor_b32_e32 v9, v10, v20
 ; GFX10-NEXT:    s_cmp_lt_u32 s5, 64
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v16, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v17, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v11, v0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v11, v1, s4
 ; GFX10-NEXT:    v_and_b32_e32 v8, 1, v9
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v2, 0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v2, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX10-NEXT:    v_sub_co_u32_e64 v8, s4, v26, v12
+; GFX10-NEXT:    v_sub_co_u32 v8, s4, v26, v12
 ; GFX10-NEXT:    v_sub_co_ci_u32_e64 v9, s4, v27, v13, s4
 ; GFX10-NEXT:    v_sub_co_ci_u32_e64 v10, s4, v24, v14, s4
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v2, vcc_lo
 ; GFX10-NEXT:    v_sub_co_ci_u32_e64 v11, s4, v25, v15, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[8:9], v[26:27]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v2, v18, v20, vcc_lo
 ; GFX10-NEXT:    v_lshrrev_b64 v[3:4], s5, v[8:9]

 ; GFX10-NEXT:    v_xor_b32_e32 v7, v14, v7
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v18, 31, v11
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, s6
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v8, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v9, s4
 ; GFX10-NEXT:    v_and_b32_e32 v7, 1, v7
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v18, v3, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v18, v4, s5
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s4, v5, 0
+; GFX10-NEXT:    v_add_co_u32 v5, s4, v5, 0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s4, 0, v6, s4
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, v7
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s4, 0, v3, s4
 ; GFX10-NEXT:    v_cndmask_b32_e32 v3, v19, v21, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, v8, v5, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, v9, v6, s5
 ; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v7, s5

llvm/test/CodeGen/AMDGPU/GlobalISel/uaddsat.ll

 ; GFX9-NEXT:    v_add_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_uaddsat_i7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 9, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 9, v1
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 9, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 9, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 9, v1
+; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1 clamp
+; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i7:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_uaddsat_i7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_bfe_u32 s2, 9, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 9, v0
+; GFX10-NEXT:    v_add_nc_u16 v0, s0, s1 clamp
+; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v0
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {
 ; GFX6-LABEL: v_uaddsat_i8:

 ; GFX9-NEXT:    v_add_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_uaddsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 8, v1
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 8, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1 clamp
+; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i8:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_uaddsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 8, v0
+; GFX10-NEXT:    v_add_nc_u16 v0, s0, s1 clamp
+; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
 ; GFX6-LABEL: v_uaddsat_v2i8:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_uaddsat_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, v0, v1 clamp
+; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1 clamp
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: s_uaddsat_i16:
 ; GFX6:       ; %bb.0:

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_uaddsat_i16:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, s0, s1 clamp
+; GFX10-NEXT:    v_add_nc_u16 v0, s0, s1 clamp
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps half @uaddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
 ; GFX6-LABEL: uaddsat_i16_sv:

 ;
 ; GFX9-LABEL: uaddsat_i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: uaddsat_i16_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, s0, v0 clamp
+; GFX10-NEXT:    v_add_nc_u16 v0, s0, v0 clamp
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define amdgpu_ps half @uaddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: uaddsat_i16_vs:

 ;
 ; GFX9-LABEL: uaddsat_i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_u16_e64 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: uaddsat_i16_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, v0, s0 clamp
+; GFX10-NEXT:    v_add_nc_u16 v0, v0, s0 clamp
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: v_uaddsat_v2i16:

 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_uaddsat_i64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }

 ; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u64_e32 vcc, v[2:3], v[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, -1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: uaddsat_i64_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, s0, v0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, -1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, -1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast

 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v2, vcc
 ; GFX9-NEXT:    v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: uaddsat_i64_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, s0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast

 ; GFX10-LABEL: v_uaddsat_v2i64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v10, v4
 ; GFX10-NEXT:    v_mov_b32_e32 v11, v5
 ; GFX10-NEXT:    v_mov_b32_e32 v15, v6
 ; GFX10-NEXT:    v_mov_b32_e32 v16, v7
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v10
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v10
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v11, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v5, vcc_lo, v2, v15
+; GFX10-NEXT:    v_add_co_u32 v5, vcc_lo, v2, v15
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, v3, v16, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[10:11]
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[5:6], v[15:16]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v5, -1, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v6, -1, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]

 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v4, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v5, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v6, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v7, -1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: uaddsat_i128_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v10, vcc_lo, s0, v0
+; GFX10-NEXT:    v_add_co_u32 v10, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[4:5], v[2:3]

 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: uaddsat_i128_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, s0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v18, v8
 ; GFX10-NEXT:    v_mov_b32_e32 v19, v9
 ; GFX10-NEXT:    v_mov_b32_e32 v16, v10
 ; GFX10-NEXT:    v_mov_b32_e32 v17, v11
 ; GFX10-NEXT:    v_mov_b32_e32 v10, v12
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, v18
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v18
 ; GFX10-NEXT:    v_mov_b32_e32 v11, v13
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v19, vcc_lo
 ; GFX10-NEXT:    v_mov_b32_e32 v20, v14
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v16, vcc_lo
 ; GFX10-NEXT:    v_mov_b32_e32 v21, v15
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v17, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[18:19]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v4, vcc_lo, v4, v10
+; GFX10-NEXT:    v_add_co_u32 v4, vcc_lo, v4, v10
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v5, vcc_lo, v5, v11, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, v6, v20, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, v7, v21, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[2:3], v[16:17]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[10:11]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[6:7], v[20:21]

llvm/test/CodeGen/AMDGPU/GlobalISel/usubsat.ll

 ; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 9, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_usubsat_i7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 9, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 9, v1
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 9, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 9, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 9, v1
+; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
+; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i7:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_usubsat_i7:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_bfe_u32 s2, 9, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 9, v0
+; GFX10-NEXT:    v_sub_nc_u16 v0, s0, s1 clamp
+; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v0
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)
   ret i7 %result
 }
 
 define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {
 ; GFX6-LABEL: v_usubsat_i8:

 ; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_usubsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 8, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 8, v1
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, v0, v1 clamp
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 8, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
+; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i8:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_usubsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_bfe_u32 s2, 8, 0x100000
 ; GFX10-NEXT:    s_lshl_b32 s0, s0, s2
 ; GFX10-NEXT:    s_lshl_b32 s1, s1, s2
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, s0, s1 clamp
-; GFX10-NEXT:    v_lshrrev_b16_e64 v0, 8, v0
+; GFX10-NEXT:    v_sub_nc_u16 v0, s0, s1 clamp
+; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
 ; GFX6-LABEL: v_usubsat_v2i8:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_usubsat_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, v0, v1 clamp
+; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: s_usubsat_i16:
 ; GFX6:       ; %bb.0:

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s1
 ; GFX9-NEXT:    v_sub_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: s_usubsat_i16:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, s0, s1 clamp
+; GFX10-NEXT:    v_sub_nc_u16 v0, s0, s1 clamp
 ; GFX10-NEXT:    v_readfirstlane_b32 s0, v0
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define amdgpu_ps half @usubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
 ; GFX6-LABEL: usubsat_i16_sv:

 ;
 ; GFX9-LABEL: usubsat_i16_sv:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_u16_e64 v0, s0, v0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: usubsat_i16_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, s0, v0 clamp
+; GFX10-NEXT:    v_sub_nc_u16 v0, s0, v0 clamp
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define amdgpu_ps half @usubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
 ; GFX6-LABEL: usubsat_i16_vs:

 ;
 ; GFX9-LABEL: usubsat_i16_vs:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_sub_u16_e64 v0, v0, s0 clamp
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: usubsat_i16_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, v0, s0 clamp
+; GFX10-NEXT:    v_sub_nc_u16 v0, v0, s0 clamp
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
   %cast = bitcast i16 %result to half
   ret half %cast
 }
 
 define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
 ; GFX6-LABEL: v_usubsat_v2i16:

 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v4, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v5, 0, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_usubsat_i64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_co_u32_e64 v4, vcc_lo, v0, v2
+; GFX10-NEXT:    v_sub_co_u32 v4, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[0:1], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v4, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v5, 0, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }

 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v1, vcc
 ; GFX9-NEXT:    v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v3, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v2, 0, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: usubsat_i64_sv:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32_e64 v2, vcc_lo, s0, v0
+; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast

 ; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v1, v2, vcc
 ; GFX9-NEXT:    v_cmp_gt_u64_e32 vcc, s[0:1], v[0:1]
 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v3, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v2, 0, vcc
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: usubsat_i64_vs:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_sub_co_u32_e64 v2, vcc_lo, v0, s0
+; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc_lo
 ; GFX10-NEXT:    ; return to shader part epilog
   %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
   %cast = bitcast i64 %result to <2 x float>
   ret <2 x float> %cast

 ; GFX10-LABEL: v_usubsat_v2i64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mov_b32_e32 v10, v0
 ; GFX10-NEXT:    v_mov_b32_e32 v11, v1
 ; GFX10-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v1, v3
-; GFX10-NEXT:    v_sub_co_u32_e64 v8, vcc_lo, v10, v4
+; GFX10-NEXT:    v_sub_co_u32 v8, vcc_lo, v10, v4
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v9, vcc_lo, v11, v5, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[10:11], v[4:5]
-; GFX10-NEXT:    v_sub_co_u32_e64 v4, s4, v0, v6
+; GFX10-NEXT:    v_sub_co_u32 v4, s4, v0, v6
 ; GFX10-NEXT:    v_sub_co_ci_u32_e64 v5, s4, v1, v7, s4
 ; GFX10-NEXT:    v_cmp_lt_u64_e64 s4, v[0:1], v[6:7]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v8, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v9, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v4, 0, s4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v5, 0, s4
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)

 ; GFX10-LABEL: usubsat_i128_sv:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[0:1], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, s0, v0
+; GFX10-NEXT:    v_sub_co_u32 v0, vcc_lo, s0, v0
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0

 ; GFX10-LABEL: usubsat_i128_vs:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[2:3]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, v0, s0
+; GFX10-NEXT:    v_sub_co_u32 v0, vcc_lo, v0, s0
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX10-NEXT:    v_and_b32_e32 v4, 1, v4
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v4
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s0

 ; GFX10-NEXT:    v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[10:11]
 ; GFX10-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[26:27], v[12:13]
 ; GFX10-NEXT:    v_and_b32_e32 v16, 1, v16
 ; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, 1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_u64_e32 vcc_lo, v[24:25], v[14:15]
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s4, 0, v16
 ; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, 1, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, v22, v8
+; GFX10-NEXT:    v_sub_co_u32 v0, vcc_lo, v22, v8
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, v23, v9, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v8, v18, v17, s5
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v2, vcc_lo, v20, v10, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, 0, s4
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v21, v11, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32_e64 v4, vcc_lo, v26, v12
+; GFX10-NEXT:    v_sub_co_u32 v4, vcc_lo, v26, v12
 ; GFX10-NEXT:    v_and_b32_e32 v8, 1, v8
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v5, vcc_lo, v27, v13, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, 0, s4
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v6, vcc_lo, v24, v14, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, 0, s4
 ; GFX10-NEXT:    v_cmp_ne_u32_e64 s5, 0, v8
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v7, vcc_lo, v25, v15, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, 0, s4

llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll

 ; GFX89-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX89-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: add_i32_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[6:7], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s7, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s7, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB0_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX1064-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1064-NEXT:    s_mul_i32 s6, s6, 5
 ; GFX1064-NEXT:    s_mov_b32 s10, -1

 ; GFX1064-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: add_i32_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s5, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s5, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s5, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s4, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB0_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s5, s5
 ; GFX1032-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1032-NEXT:    s_mul_i32 s5, s5, 5
 ; GFX1032-NEXT:    s_mov_b32 s10, -1

 ;
 ; GFX1064-LABEL: add_i32_uniform:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_clause 0x1
 ; GFX1064-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX1064-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX1064-NEXT:    s_mov_b64 s[8:9], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s8, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s9, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s8, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s9, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB1_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s3, s[8:9]
 ; GFX1064-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    s_mul_i32 s3, s2, s3

 ;
 ; GFX1032-LABEL: add_i32_uniform:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_clause 0x1
 ; GFX1032-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX1032-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX1032-NEXT:    s_mov_b32 s3, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s3, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB1_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s1, s3
 ; GFX1032-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    s_mul_i32 s1, s2, s1

 ; GFX1064-NEXT:    v_readlane_b32 s6, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s6, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_readlane_b32 s8, v1, 47
 ; GFX1064-NEXT:    v_readlane_b32 s9, v1, 63
 ; GFX1064-NEXT:    v_writelane_b32 v3, s7, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[6:7], -1
 ; GFX1064-NEXT:    s_mov_b32 s4, s9
 ; GFX1064-NEXT:    v_writelane_b32 v3, s8, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[6:7]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s6, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[8:9], vcc

 ; GFX1032-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s4, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s5, v1, 15
 ; GFX1032-NEXT:    v_readlane_b32 s6, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s4
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s4, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s5, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s4
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s4, s6
 ; GFX1032-NEXT:    s_mov_b32 s6, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s8, vcc_lo

 ; GFX89-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX89-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: add_i64_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[6:7], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s7, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s7, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB3_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1064-NEXT:    s_mul_i32 s6, s6, 5
 ; GFX1064-NEXT:    s_mov_b32 s11, 0x31016000

 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: add_i64_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s5, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s5, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s5, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s4, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB3_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s5, s5
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1032-NEXT:    s_mul_i32 s5, s5, 5
 ; GFX1032-NEXT:    s_mov_b32 s11, 0x31016000

 ;
 ; GFX1064-LABEL: add_i64_uniform:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_clause 0x1
 ; GFX1064-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX1064-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX1064-NEXT:    s_mov_b64 s[8:9], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s8, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s9, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s8, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s9, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB4_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s8, s[8:9]
 ; GFX1064-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    s_mul_i32 s9, s3, s8

 ; GFX1064-NEXT:    v_mul_lo_u32 v3, s3, v0
 ; GFX1064-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX1064-NEXT:    v_mul_lo_u32 v0, s2, v0
 ; GFX1064-NEXT:    v_readfirstlane_b32 s0, v1
 ; GFX1064-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX1064-NEXT:    s_mov_b32 s7, 0x31016000
 ; GFX1064-NEXT:    s_mov_b32 s6, -1
 ; GFX1064-NEXT:    v_add_nc_u32_e32 v1, v4, v3
-; GFX1064-NEXT:    v_add_co_u32_e64 v0, vcc, s0, v0
+; GFX1064-NEXT:    v_add_co_u32 v0, vcc, s0, v0
 ; GFX1064-NEXT:    v_add_co_ci_u32_e32 v1, vcc, s1, v1, vcc
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: add_i64_uniform:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_clause 0x1
 ; GFX1032-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX1032-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX1032-NEXT:    s_mov_b32 s8, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s8, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s8, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB4_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s1, s8
 ; GFX1032-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    s_mul_i32 s8, s3, s1

 ; GFX1032-NEXT:    v_mul_lo_u32 v3, s3, v0
 ; GFX1032-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX1032-NEXT:    v_mul_lo_u32 v0, s2, v0
 ; GFX1032-NEXT:    v_readfirstlane_b32 s0, v1
 ; GFX1032-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX1032-NEXT:    s_mov_b32 s7, 0x31016000
 ; GFX1032-NEXT:    s_mov_b32 s6, -1
 ; GFX1032-NEXT:    v_add_nc_u32_e32 v1, v4, v3
-; GFX1032-NEXT:    v_add_co_u32_e64 v0, vcc_lo, s0, v0
+; GFX1032-NEXT:    v_add_co_u32 v0, vcc_lo, s0, v0
 ; GFX1032-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX1032-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX1032-NEXT:    s_endpgm
 entry:
   %old = atomicrmw add i64 addrspace(1)* %inout, i64 %additive acq_rel
   store i64 %old, i64 addrspace(1)* %out
   ret void
 }

 ; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: sub_i32_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[6:7], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s7, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s7, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB6_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX1064-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1064-NEXT:    s_mul_i32 s6, s6, 5
 ; GFX1064-NEXT:    s_mov_b32 s10, -1

 ; GFX1064-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: sub_i32_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s5, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s5, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s5, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s4, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB6_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s5, s5
 ; GFX1032-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1032-NEXT:    s_mul_i32 s5, s5, 5
 ; GFX1032-NEXT:    s_mov_b32 s10, -1

 ;
 ; GFX1064-LABEL: sub_i32_uniform:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_clause 0x1
 ; GFX1064-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX1064-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX1064-NEXT:    s_mov_b64 s[8:9], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s8, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s9, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s8, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s9, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB7_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s3, s[8:9]
 ; GFX1064-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    s_mul_i32 s3, s2, s3

 ;
 ; GFX1032-LABEL: sub_i32_uniform:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_clause 0x1
 ; GFX1032-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX1032-NEXT:    s_load_dword s2, s[0:1], 0x34
 ; GFX1032-NEXT:    s_mov_b32 s3, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s3, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB7_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s1, s3
 ; GFX1032-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    s_mul_i32 s1, s2, s1

 ; GFX1064-NEXT:    v_readlane_b32 s6, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s6, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_readlane_b32 s8, v1, 47
 ; GFX1064-NEXT:    v_readlane_b32 s9, v1, 63
 ; GFX1064-NEXT:    v_writelane_b32 v3, s7, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[6:7], -1
 ; GFX1064-NEXT:    s_mov_b32 s4, s9
 ; GFX1064-NEXT:    v_writelane_b32 v3, s8, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[6:7]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s6, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[8:9], vcc

 ; GFX1032-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s4, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s5, v1, 15
 ; GFX1032-NEXT:    v_readlane_b32 s6, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s4
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s4, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s5, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s4
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s4, s6
 ; GFX1032-NEXT:    s_mov_b32 s6, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s8, vcc_lo

 ; GFX9-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: sub_i64_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[6:7], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s7, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s7, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB9_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1064-NEXT:    s_mul_i32 s6, s6, 5
 ; GFX1064-NEXT:    s_mov_b32 s11, 0x31016000

 ; GFX1064-NEXT:  BB9_2:
 ; GFX1064-NEXT:    s_waitcnt_depctr 0xffe3
 ; GFX1064-NEXT:    s_or_b64 exec, exec, s[4:5]
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX1064-NEXT:    v_mul_u32_u24_e32 v1, 5, v0
 ; GFX1064-NEXT:    v_readfirstlane_b32 s3, v2
 ; GFX1064-NEXT:    v_mul_hi_u32_u24_e32 v2, 5, v0
-; GFX1064-NEXT:    v_sub_co_u32_e64 v0, vcc, s2, v1
+; GFX1064-NEXT:    v_sub_co_u32 v0, vcc, s2, v1
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    v_sub_co_ci_u32_e32 v1, vcc, s3, v2, vcc
 ; GFX1064-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: sub_i64_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s5, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s5, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s5, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s4, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB9_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s5, s5
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1032-NEXT:    s_mul_i32 s5, s5, 5
 ; GFX1032-NEXT:    s_mov_b32 s11, 0x31016000

 ; GFX1032-NEXT:  BB9_2:
 ; GFX1032-NEXT:    s_waitcnt_depctr 0xffe3
 ; GFX1032-NEXT:    s_or_b32 exec_lo, exec_lo, s4
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX1032-NEXT:    v_mul_u32_u24_e32 v1, 5, v0
 ; GFX1032-NEXT:    v_readfirstlane_b32 s3, v2
 ; GFX1032-NEXT:    v_mul_hi_u32_u24_e32 v2, 5, v0
-; GFX1032-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, s2, v1
+; GFX1032-NEXT:    v_sub_co_u32 v0, vcc_lo, s2, v1
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
 ; GFX1032-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1032-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 entry:
   %old = atomicrmw sub i64 addrspace(1)* %inout, i64 5 acq_rel
   store i64 %old, i64 addrspace(1)* %out

 ;
 ; GFX1064-LABEL: sub_i64_uniform:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_clause 0x1
 ; GFX1064-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX1064-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX1064-NEXT:    s_mov_b64 s[8:9], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s8, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s9, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s8, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s9, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB10_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s8, s[8:9]
 ; GFX1064-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    s_mul_i32 s9, s3, s8

 ; GFX1064-NEXT:    v_mul_lo_u32 v3, s3, v0
 ; GFX1064-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX1064-NEXT:    v_mul_lo_u32 v0, s2, v0
 ; GFX1064-NEXT:    v_readfirstlane_b32 s0, v1
 ; GFX1064-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX1064-NEXT:    s_mov_b32 s7, 0x31016000
 ; GFX1064-NEXT:    s_mov_b32 s6, -1
 ; GFX1064-NEXT:    v_add_nc_u32_e32 v1, v4, v3
-; GFX1064-NEXT:    v_sub_co_u32_e64 v0, vcc, s0, v0
+; GFX1064-NEXT:    v_sub_co_u32 v0, vcc, s0, v0
 ; GFX1064-NEXT:    v_sub_co_ci_u32_e32 v1, vcc, s1, v1, vcc
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: sub_i64_uniform:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_clause 0x1
 ; GFX1032-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX1032-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x34
 ; GFX1032-NEXT:    s_mov_b32 s8, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s8, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s8, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB10_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s1, s8
 ; GFX1032-NEXT:    s_mov_b32 s11, 0x31016000
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    s_mul_i32 s8, s3, s1

 ; GFX1032-NEXT:    v_mul_lo_u32 v3, s3, v0
 ; GFX1032-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX1032-NEXT:    v_mul_lo_u32 v0, s2, v0
 ; GFX1032-NEXT:    v_readfirstlane_b32 s0, v1
 ; GFX1032-NEXT:    v_readfirstlane_b32 s1, v2
 ; GFX1032-NEXT:    s_mov_b32 s7, 0x31016000
 ; GFX1032-NEXT:    s_mov_b32 s6, -1
 ; GFX1032-NEXT:    v_add_nc_u32_e32 v1, v4, v3
-; GFX1032-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, s0, v0
+; GFX1032-NEXT:    v_sub_co_u32 v0, vcc_lo, s0, v0
 ; GFX1032-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo
 ; GFX1032-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX1032-NEXT:    s_endpgm
 entry:
   %old = atomicrmw sub i64 addrspace(1)* %inout, i64 %subitive acq_rel
   store i64 %old, i64 addrspace(1)* %out
   ret void
 }

llvm/test/CodeGen/AMDGPU/atomic_optimizations_local_pointer.ll

 ; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: add_i32_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s2, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s3, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s3, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB0_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s2, s[2:3]
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, local_var32@abs32@lo
 ; GFX1064-NEXT:    s_mul_i32 s2, s2, 5
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s2

 ; GFX1064-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: add_i32_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s3, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s3, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s2, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB0_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s3, s3
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, local_var32@abs32@lo
 ; GFX1032-NEXT:    s_mul_i32 s3, s3, 5
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, s3

 ;
 ; GFX1064-LABEL: add_i32_uniform:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_clause 0x1
 ; GFX1064-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX1064-NEXT:    s_load_dword s2, s[0:1], 0x2c
 ; GFX1064-NEXT:    s_mov_b64 s[6:7], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s7, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s7, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB1_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s3, s[6:7]
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, local_var32@abs32@lo
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    s_mul_i32 s3, s2, s3

 ;
 ; GFX1032-LABEL: add_i32_uniform:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_clause 0x1
 ; GFX1032-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX1032-NEXT:    s_load_dword s2, s[0:1], 0x2c
 ; GFX1032-NEXT:    s_mov_b32 s3, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s3, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB1_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s1, s3
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, local_var32@abs32@lo
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    s_mul_i32 s1, s2, s1

 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s5, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s4, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v1, 63
 ; GFX1064-NEXT:    v_readlane_b32 s6, v1, 47
 ; GFX1064-NEXT:    v_writelane_b32 v3, s5, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_writelane_b32 v3, s6, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB2_2

 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15
 ; GFX1032-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s3, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s3, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB2_2

 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_add_nc_u32_e32 v1, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 exec, s[0:1]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1064-NEXT:    v_readlane_b32 s2, v1, 0
 ; GFX1064-NEXT:    v_readlane_b32 s3, v1, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[0:1]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_add_i32 s0, s2, s3
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB3_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    v_mov_b32_e32 v0, local_var32@abs32@lo
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX1064-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)

 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    v_add_nc_u32_e32 v1, v1, v2
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s0
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v3, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v3, exec_lo, 0
 ; GFX1032-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v3
 ; GFX1032-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB3_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, local_var32@abs32@lo
 ; GFX1032-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX1032-NEXT:    s_waitcnt_vscnt null, 0x0

 ; GFX9-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: add_i64_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s4, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s5, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB4_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1064-NEXT:    s_mul_i32 s4, s4, 5
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo

 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: add_i64_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s3, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s3, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s2, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB4_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s3, s3
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1032-NEXT:    s_mul_i32 s3, s3, 5
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo

 ; GFX9-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: add_i64_uniform:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[6:7], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s7, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s7, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB5_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    s_mul_i32 s7, s3, s6

 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    v_mul_lo_u32 v3, s3, v0
 ; GFX1064-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX1064-NEXT:    v_mul_lo_u32 v0, s2, v0
 ; GFX1064-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX1064-NEXT:    v_readfirstlane_b32 s4, v2
 ; GFX1064-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1064-NEXT:    v_add_nc_u32_e32 v1, v4, v3
-; GFX1064-NEXT:    v_add_co_u32_e64 v0, vcc, s2, v0
+; GFX1064-NEXT:    v_add_co_u32 v0, vcc, s2, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    v_add_co_ci_u32_e32 v1, vcc, s4, v1, vcc
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: add_i64_uniform:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s5, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s5, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s5, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s4, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB5_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s5, s5
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    s_mul_i32 s6, s3, s5

 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    v_mul_lo_u32 v3, s3, v0
 ; GFX1032-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX1032-NEXT:    v_mul_lo_u32 v0, s2, v0
 ; GFX1032-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX1032-NEXT:    v_readfirstlane_b32 s4, v2
 ; GFX1032-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1032-NEXT:    v_add_nc_u32_e32 v1, v4, v3
-; GFX1032-NEXT:    v_add_co_u32_e64 v0, vcc_lo, s2, v0
+; GFX1032-NEXT:    v_add_co_u32 v0, vcc_lo, s2, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo
 ; GFX1032-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 entry:
   %old = atomicrmw add i64 addrspace(3)* @local_var64, i64 %additive acq_rel
   store i64 %old, i64 addrspace(1)* %out
   ret void

 ; GFX9-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: sub_i32_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[2:3], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s2, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s3, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s2, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s3, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB7_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s2, s[2:3]
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, local_var32@abs32@lo
 ; GFX1064-NEXT:    s_mul_i32 s2, s2, 5
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s2

 ; GFX1064-NEXT:    buffer_store_dword v0, off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: sub_i32_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s3, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s3, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s2, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB7_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s3, s3
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, local_var32@abs32@lo
 ; GFX1032-NEXT:    s_mul_i32 s3, s3, 5
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, s3

 ;
 ; GFX1064-LABEL: sub_i32_uniform:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_clause 0x1
 ; GFX1064-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX1064-NEXT:    s_load_dword s2, s[0:1], 0x2c
 ; GFX1064-NEXT:    s_mov_b64 s[6:7], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s7, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s7, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[0:1], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB8_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s3, s[6:7]
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, local_var32@abs32@lo
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    s_mul_i32 s3, s2, s3

 ;
 ; GFX1032-LABEL: sub_i32_uniform:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_clause 0x1
 ; GFX1032-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x24
 ; GFX1032-NEXT:    s_load_dword s2, s[0:1], 0x2c
 ; GFX1032-NEXT:    s_mov_b32 s3, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s3, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB8_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s1, s3
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, local_var32@abs32@lo
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    s_mul_i32 s1, s2, s1

 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s5, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s4, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v1, 63
 ; GFX1064-NEXT:    v_readlane_b32 s6, v1, 47
 ; GFX1064-NEXT:    v_writelane_b32 v3, s5, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_writelane_b32 v3, s6, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB9_2

 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15
 ; GFX1032-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s3, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s3, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB9_2

 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1064-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1064-NEXT:    v_add_nc_u32_e32 v1, v1, v2
 ; GFX1064-NEXT:    s_mov_b64 exec, s[0:1]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[0:1], -1
 ; GFX1064-NEXT:    v_readlane_b32 s2, v1, 0
 ; GFX1064-NEXT:    v_readlane_b32 s3, v1, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[0:1]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_add_i32 s0, s2, s3
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB10_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    v_mov_b32_e32 v0, local_var32@abs32@lo
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, s0
 ; GFX1064-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)

 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:1 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:2 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:4 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_xmask:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    v_add_nc_u32_e32 v1, v1, v2
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s0
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v3, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v3, exec_lo, 0
 ; GFX1032-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v3
 ; GFX1032-NEXT:    s_and_saveexec_b32 s0, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB10_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, local_var32@abs32@lo
 ; GFX1032-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX1032-NEXT:    s_waitcnt_vscnt null, 0x0

 ; GFX9-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: sub_i64_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[4:5], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s4, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s5, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s4, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s5, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB11_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s4, s[4:5]
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1064-NEXT:    s_mul_i32 s4, s4, 5
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, s4
 ; GFX1064-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX1064-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX1064-NEXT:    ds_sub_rtn_u64 v[1:2], v3, v[1:2]
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    buffer_gl0_inv
 ; GFX1064-NEXT:  BB11_2:
 ; GFX1064-NEXT:    s_waitcnt_depctr 0xffe3
 ; GFX1064-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX1064-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX1064-NEXT:    v_mul_u32_u24_e32 v1, 5, v0
 ; GFX1064-NEXT:    v_readfirstlane_b32 s3, v2
 ; GFX1064-NEXT:    v_mul_hi_u32_u24_e32 v2, 5, v0
-; GFX1064-NEXT:    v_sub_co_u32_e64 v0, vcc, s2, v1
+; GFX1064-NEXT:    v_sub_co_u32 v0, vcc, s2, v1
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    v_sub_co_ci_u32_e32 v1, vcc, s3, v2, vcc
 ; GFX1064-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: sub_i64_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s3, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s3, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s3, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s2, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB11_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s3, s3
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX1032-NEXT:    s_mul_i32 s3, s3, 5
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX1032-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX1032-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX1032-NEXT:    ds_sub_rtn_u64 v[1:2], v3, v[1:2]
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    buffer_gl0_inv
 ; GFX1032-NEXT:  BB11_2:
 ; GFX1032-NEXT:    s_waitcnt_depctr 0xffe3
 ; GFX1032-NEXT:    s_or_b32 exec_lo, exec_lo, s2
 ; GFX1032-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX1032-NEXT:    v_mul_u32_u24_e32 v1, 5, v0
 ; GFX1032-NEXT:    v_readfirstlane_b32 s3, v2
 ; GFX1032-NEXT:    v_mul_hi_u32_u24_e32 v2, 5, v0
-; GFX1032-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, s2, v1
+; GFX1032-NEXT:    v_sub_co_u32 v0, vcc_lo, s2, v1
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s3, v2, vcc_lo
 ; GFX1032-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 entry:
   %old = atomicrmw sub i64 addrspace(3)* @local_var64, i64 5 acq_rel

 ; GFX9-NEXT:    buffer_store_dwordx2 v[0:1], off, s[4:7], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: sub_i64_uniform:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1064-NEXT:    s_mov_b64 s[6:7], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s6, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s7, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s6, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s7, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB12_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s6, s[6:7]
 ; GFX1064-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    s_mul_i32 s7, s3, s6

 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    v_mul_lo_u32 v3, s3, v0
 ; GFX1064-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX1064-NEXT:    v_mul_lo_u32 v0, s2, v0
 ; GFX1064-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX1064-NEXT:    v_readfirstlane_b32 s4, v2
 ; GFX1064-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1064-NEXT:    v_add_nc_u32_e32 v1, v4, v3
-; GFX1064-NEXT:    v_sub_co_u32_e64 v0, vcc, s2, v0
+; GFX1064-NEXT:    v_sub_co_u32 v0, vcc, s2, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    v_sub_co_ci_u32_e32 v1, vcc, s4, v1, vcc
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: sub_i64_uniform:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX1032-NEXT:    s_mov_b32 s5, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1_vgpr2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s5, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s5, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s4, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB12_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s5, s5
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, local_var64@abs32@lo
 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    s_mul_i32 s6, s3, s5

 ; GFX1032-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1032-NEXT:    v_mul_lo_u32 v3, s3, v0
 ; GFX1032-NEXT:    v_mul_hi_u32 v4, s2, v0
 ; GFX1032-NEXT:    v_mul_lo_u32 v0, s2, v0
 ; GFX1032-NEXT:    v_readfirstlane_b32 s2, v1
 ; GFX1032-NEXT:    v_readfirstlane_b32 s4, v2
 ; GFX1032-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1032-NEXT:    v_add_nc_u32_e32 v1, v4, v3
-; GFX1032-NEXT:    v_sub_co_u32_e64 v0, vcc_lo, s2, v0
+; GFX1032-NEXT:    v_sub_co_u32 v0, vcc_lo, s2, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    v_sub_co_ci_u32_e32 v1, vcc_lo, s4, v1, vcc_lo
 ; GFX1032-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1032-NEXT:    s_endpgm
 entry:
   %old = atomicrmw sub i64 addrspace(3)* @local_var64, i64 %subitive acq_rel
   store i64 %old, i64 addrspace(1)* %out
   ret void

 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s5, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s4, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v1, 63
 ; GFX1064-NEXT:    v_readlane_b32 s6, v1, 47
 ; GFX1064-NEXT:    v_writelane_b32 v3, s5, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_writelane_b32 v3, s6, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB14_2

 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_and_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, -1
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15
 ; GFX1032-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s3, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s3, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB14_2

 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s5, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s4, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v1, 63
 ; GFX1064-NEXT:    v_readlane_b32 s6, v1, 47
 ; GFX1064-NEXT:    v_writelane_b32 v3, s5, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_writelane_b32 v3, s6, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB15_2

 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_or_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15
 ; GFX1032-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s3, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s3, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB15_2

 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s5, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s4, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v1, 63
 ; GFX1064-NEXT:    v_readlane_b32 s6, v1, 47
 ; GFX1064-NEXT:    v_writelane_b32 v3, s5, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_writelane_b32 v3, s6, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB16_2

 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_xor_b32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15
 ; GFX1032-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s3, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s3, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB16_2

 ; GFX1064-NEXT:    v_readlane_b32 s4, v2, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s5, v2, 31
 ; GFX1064-NEXT:    v_writelane_b32 v1, s4, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v2, 63
 ; GFX1064-NEXT:    v_readlane_b32 s6, v2, 47
 ; GFX1064-NEXT:    v_writelane_b32 v1, s5, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_writelane_b32 v1, s6, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB17_2

 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_max_i32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_readlane_b32 s3, v2, 15
 ; GFX1032-NEXT:    v_readlane_b32 s4, v2, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_writelane_b32 v1, s3, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s3, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB17_2

 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s2, -1
 ; GFX9-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: max_i64_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB18_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    v_mov_b32_e32 v0, 5
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, local_var64@abs32@lo
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0

 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: max_i64_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; GFX1032-NEXT:    s_and_saveexec_b32 s2, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB18_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    v_mov_b32_e32 v0, 5
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, local_var64@abs32@lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0

 ; GFX1064-NEXT:    v_readlane_b32 s4, v2, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s5, v2, 31
 ; GFX1064-NEXT:    v_writelane_b32 v1, s4, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v2, 63
 ; GFX1064-NEXT:    v_readlane_b32 s6, v2, 47
 ; GFX1064-NEXT:    v_writelane_b32 v1, s5, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_writelane_b32 v1, s6, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB19_2

 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_min_i32_dpp v2, v3, v2 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_readlane_b32 s3, v2, 15
 ; GFX1032-NEXT:    v_readlane_b32 s4, v2, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v1, v2 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_writelane_b32 v1, s3, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s3, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB19_2

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: min_i64_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB20_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    v_mov_b32_e32 v0, 5
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, local_var64@abs32@lo
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0

 ; GFX1064-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: min_i64_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; GFX1032-NEXT:    s_and_saveexec_b32 s2, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB20_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    v_mov_b32_e32 v0, 5
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, local_var64@abs32@lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0

 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s5, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s4, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v1, 63
 ; GFX1064-NEXT:    v_readlane_b32 s6, v1, 47
 ; GFX1064-NEXT:    v_writelane_b32 v3, s5, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_writelane_b32 v3, s6, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB21_2

 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_max_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, 0
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15
 ; GFX1032-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s3, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s3, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB21_2

 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    s_mov_b32 s2, -1
 ; GFX9-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: umax_i64_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB22_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    v_mov_b32_e32 v0, 5
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, local_var64@abs32@lo
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0

 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: umax_i64_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; GFX1032-NEXT:    s_and_saveexec_b32 s2, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB22_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    v_mov_b32_e32 v0, 5
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, local_var64@abs32@lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0

 ; GFX1064-NEXT:    v_readlane_b32 s4, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s5, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s4, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[2:3], -1
 ; GFX1064-NEXT:    v_readlane_b32 s7, v1, 63
 ; GFX1064-NEXT:    v_readlane_b32 s6, v1, 47
 ; GFX1064-NEXT:    v_writelane_b32 v3, s5, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[2:3]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[4:5], -1
 ; GFX1064-NEXT:    v_writelane_b32 v3, s6, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_mov_b32 s2, -1
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[4:5], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB23_2

 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_min_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_mov_b32_e32 v3, -1
 ; GFX1032-NEXT:    v_readlane_b32 s3, v1, 15
 ; GFX1032-NEXT:    v_readlane_b32 s4, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s3, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s2
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_mov_b32 s2, -1
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s3, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB23_2

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
 ; GFX9-NEXT:    s_mov_b32 s3, 0xf000
 ; GFX9-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX1064-LABEL: umin_i64_constant:
 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[2:3], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB24_2
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    v_mov_b32_e32 v0, 5
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, local_var64@abs32@lo
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, 0

 ; GFX1064-NEXT:    s_mov_b32 s3, 0x31016000
 ; GFX1064-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX1064-NEXT:    buffer_store_dwordx2 v[0:1], off, s[0:3], 0
 ; GFX1064-NEXT:    s_endpgm
 ;
 ; GFX1032-LABEL: umin_i64_constant:
 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0_vgpr1
 ; GFX1032-NEXT:    s_and_saveexec_b32 s2, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB24_2
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    v_mov_b32_e32 v0, 5
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, local_var64@abs32@lo
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, 0

llvm/test/CodeGen/AMDGPU/atomic_optimizations_pixelshader.ll

 ; GFX1064:       ; %bb.0: ; %entry
 ; GFX1064-NEXT:    s_mov_b64 s[10:11], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[8:9], s[10:11]
 ; GFX1064-NEXT:    s_cbranch_execz BB0_4
 ; GFX1064-NEXT:  ; %bb.1:
 ; GFX1064-NEXT:    s_mov_b64 s[12:13], exec
 ; GFX1064-NEXT:    ; implicit-def: $vgpr1
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s12, 0
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, s13, v0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, s12, 0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, s13, v0
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[28:29], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB0_3
 ; GFX1064-NEXT:  ; %bb.2:
 ; GFX1064-NEXT:    s_bcnt1_i32_b64 s12, s[12:13]
 ; GFX1064-NEXT:    s_mul_i32 s12, s12, 5
 ; GFX1064-NEXT:    v_mov_b32_e32 v1, s12
 ; GFX1064-NEXT:    buffer_atomic_add v1, off, s[4:7], 0 glc

 ; GFX1032:       ; %bb.0: ; %entry
 ; GFX1032-NEXT:    s_mov_b32 s9, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s8, s9
 ; GFX1032-NEXT:    s_cbranch_execz BB0_4
 ; GFX1032-NEXT:  ; %bb.1:
 ; GFX1032-NEXT:    s_mov_b32 s10, exec_lo
 ; GFX1032-NEXT:    ; implicit-def: $vgpr1
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, s10, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, s10, 0
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s9, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB0_3
 ; GFX1032-NEXT:  ; %bb.2:
 ; GFX1032-NEXT:    s_bcnt1_i32_b32 s10, s10
 ; GFX1032-NEXT:    s_mul_i32 s10, s10, 5
 ; GFX1032-NEXT:    v_mov_b32_e32 v1, s10
 ; GFX1032-NEXT:    buffer_atomic_add v1, off, s[4:7], 0 glc

 ; GFX1064-NEXT:    v_readlane_b32 s12, v1, 31
 ; GFX1064-NEXT:    v_mov_b32_e32 v2, s12
 ; GFX1064-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xc bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s12, v1, 15
 ; GFX1064-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1064-NEXT:    v_readlane_b32 s13, v1, 31
 ; GFX1064-NEXT:    v_writelane_b32 v3, s12, 16
 ; GFX1064-NEXT:    s_mov_b64 exec, s[10:11]
-; GFX1064-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1064-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[10:11], -1
 ; GFX1064-NEXT:    v_readlane_b32 s12, v1, 63
 ; GFX1064-NEXT:    v_readlane_b32 s14, v1, 47
 ; GFX1064-NEXT:    v_writelane_b32 v3, s13, 32
 ; GFX1064-NEXT:    s_mov_b64 exec, s[10:11]
-; GFX1064-NEXT:    v_mbcnt_hi_u32_b32_e64 v0, exec_hi, v0
+; GFX1064-NEXT:    v_mbcnt_hi_u32_b32 v0, exec_hi, v0
 ; GFX1064-NEXT:    s_or_saveexec_b64 s[10:11], -1
 ; GFX1064-NEXT:    v_writelane_b32 v3, s14, 48
 ; GFX1064-NEXT:    s_mov_b64 exec, s[10:11]
 ; GFX1064-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
 ; GFX1064-NEXT:    ; implicit-def: $vgpr0
 ; GFX1064-NEXT:    s_and_saveexec_b64 s[28:29], vcc
 ; GFX1064-NEXT:    s_cbranch_execz BB1_3
 ; GFX1064-NEXT:  ; %bb.2:

 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v1, v1 row_shr:8 row_mask:0xf bank_mask:0xf bound_ctrl:1
 ; GFX1032-NEXT:    v_mov_b32_e32 v2, v1
 ; GFX1032-NEXT:    v_permlanex16_b32 v2, v2, -1, -1
 ; GFX1032-NEXT:    v_add_nc_u32_dpp v1, v2, v1 quad_perm:[0,1,2,3] row_mask:0xa bank_mask:0xf
 ; GFX1032-NEXT:    v_readlane_b32 s11, v1, 31
 ; GFX1032-NEXT:    v_mov_b32_dpp v3, v1 row_shr:1 row_mask:0xf bank_mask:0xf
 ; GFX1032-NEXT:    v_readlane_b32 s10, v1, 15
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s9
-; GFX1032-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, exec_lo, 0
+; GFX1032-NEXT:    v_mbcnt_lo_u32_b32 v0, exec_lo, 0
 ; GFX1032-NEXT:    s_or_saveexec_b32 s9, -1
 ; GFX1032-NEXT:    v_writelane_b32 v3, s10, 16
 ; GFX1032-NEXT:    s_mov_b32 exec_lo, s9
 ; GFX1032-NEXT:    v_cmp_eq_u32_e32 vcc_lo, 0, v0
 ; GFX1032-NEXT:    ; implicit-def: $vgpr0
 ; GFX1032-NEXT:    s_and_saveexec_b32 s9, vcc_lo
 ; GFX1032-NEXT:    s_cbranch_execz BB1_3
 ; GFX1032-NEXT:  ; %bb.2:

llvm/test/CodeGen/AMDGPU/carryout-selection.ll

 ; CISI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
 ; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
 ; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
 ; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
-; GFX1010: v_add_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}
+; GFX1010: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX1010: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]]
 define amdgpu_kernel void @vadd64rr(i64 addrspace(1)* %out, i64 %a) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %add = add i64 %a, %tid.ext
   store i64 %add, i64 addrspace(1)* %out
   ret void

 ; VI: v_add_u32_e32 v0, vcc, 0x56789876, v0
 ; VI: v_mov_b32_e32 v1, 0x1234
 ; VI: v_addc_u32_e32 v1, vcc, 0, v1, vcc
 ;
 ; GFX9: v_add_co_u32_e32 v0, vcc, 0x56789876, v0
 ; GFX9: v_mov_b32_e32 v1, 0x1234
 ; GFX9: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ;
-; GFX1010: v_add_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], 0x56789876, v{{[0-9]+}}
+; GFX1010: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], 0x56789876, v{{[0-9]+}}
 ; GFX1010: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], 0, 0x1234, [[CARRY]]
 define amdgpu_kernel void @vadd64ri(i64 addrspace(1)* %out) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %add = add i64 20015998343286, %tid.ext
   store i64 %add, i64 addrspace(1)* %out
   ret void

 ; CISI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
 ;
 ; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
 ; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
 ;
 ; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX9: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
 ;
-; GFX1010: v_add_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
+; GFX1010: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
 ; GFX1010: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[CARRY]]
 define amdgpu_kernel void @uaddo32_vcc_user(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 {
   %uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
   %val = extractvalue { i32, i1 } %uadd, 0
   %carry = extractvalue { i32, i1 } %uadd, 1
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i1 %carry, i1 addrspace(1)* %carryout
   ret void

 ; CISI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
 ; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
 ; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
 ; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
 ; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
-; GFX1010: v_add_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0
+; GFX1010: v_add_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0
 ; GFX1010: v_add_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]]
 define amdgpu_kernel void @vuaddo64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a) #0 {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %tid.ext)
   %val = extractvalue { i64, i1 } %uadd, 0
   %carry = extractvalue { i64, i1 } %uadd, 1
   store i64 %val, i64 addrspace(1)* %out, align 8

 ; CISI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
 ; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
 ; VI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
 ; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX9: v_subbrev_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
-; GFX1010: v_sub_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}
+; GFX1010: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX1010: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]]
 define amdgpu_kernel void @vsub64rr(i64 addrspace(1)* %out, i64 %a) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %sub = sub i64 %a, %tid.ext
   store i64 %sub, i64 addrspace(1)* %out
   ret void

 ; VI: v_sub_u32_e32 v0, vcc, 0x56789876, v0
 ; VI: v_mov_b32_e32 v1, 0x1234
 ; VI: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
 ;
 ; GFX9: v_sub_co_u32_e32 v0, vcc, 0x56789876, v0
 ; GFX9: v_mov_b32_e32 v1, 0x1234
 ; GFX9: v_subbrev_co_u32_e32 v1, vcc, 0, v1, vcc
 ;
-; GFX1010: v_sub_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], 0x56789876, v{{[0-9]+}}
+; GFX1010: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], 0x56789876, v{{[0-9]+}}
 ; GFX1010: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], 0x1234, 0, [[CARRY]]
 define amdgpu_kernel void @vsub64ri(i64 addrspace(1)* %out) {
 entry:
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %sub = sub i64 20015998343286, %tid.ext
   store i64 %sub, i64 addrspace(1)* %out
   ret void

 ; CISI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
 ;
 ; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
 ; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
 ;
 ; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX9: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
 ;
-; GFX1010: v_sub_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
+; GFX1010: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, s{{[0-9]+}}
 ; GFX1010: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, [[CARRY]]
 define amdgpu_kernel void @usubo32_vcc_user(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 {
   %usub = call { i32, i1 } @llvm.usub.with.overflow.i32(i32 %a, i32 %b)
   %val = extractvalue { i32, i1 } %usub, 0
   %carry = extractvalue { i32, i1 } %usub, 1
   store i32 %val, i32 addrspace(1)* %out, align 4
   store i1 %carry, i1 addrspace(1)* %carryout
   ret void

 ; CISI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
 ; VI: v_sub_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
 ; VI: v_subbrev_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
 ; GFX9: v_sub_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v0
 ; GFX9: v_subbrev_co_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc
 ;
-; GFX1010: v_sub_co_u32_e64 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0
+; GFX1010: v_sub_co_u32 v{{[0-9]+}}, [[CARRY:s[0-9]+]], s{{[0-9]+}}, v0
 ; GFX1010: v_sub_co_ci_u32_e64 v{{[0-9]+}}, [[CARRY]], s{{[0-9]+}}, 0, [[CARRY]]
 define amdgpu_kernel void @vusubo64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a) #0 {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %usub = call { i64, i1 } @llvm.usub.with.overflow.i64(i64 %a, i64 %tid.ext)
   %val = extractvalue { i64, i1 } %usub, 0
   %carry = extractvalue { i64, i1 } %usub, 1
   store i64 %val, i64 addrspace(1)* %out, align 8

llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx1030.ll

 ; OPT:       endif:
 ; OPT-NEXT:    [[X:%.*]] = phi i32 [ [[VAL]], [[IF]] ], [ 0, [[ENTRY:%.*]] ]
 ; OPT-NEXT:    store i32 [[X]], i32 addrspace(1)* [[OUT_GEP]], align 4
 ; OPT-NEXT:    ret void
 ;
 ; GCN-LABEL: test_sink_small_offset_global_atomic_csub_i32:
 ; GCN:       ; %bb.0: ; %entry
 ; GCN-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
-; GCN-NEXT:    v_mbcnt_lo_u32_b32_e64 v0, -1, 0
+; GCN-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
 ; GCN-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v0
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
 ; GCN-NEXT:    s_and_saveexec_b32 s4, vcc_lo
 ; GCN-NEXT:    s_cbranch_execz BB0_2
 ; GCN-NEXT:  ; %bb.1: ; %if
 ; GCN-NEXT:    v_mov_b32_e32 v0, 0
 ; GCN-NEXT:    v_mov_b32_e32 v1, 2
 ; GCN-NEXT:    s_waitcnt lgkmcnt(0)

llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll

 ; GCN-NEXT:    v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
 ; GCN-NEXT:    v_bfi_b32 v0, v1, v2, v0
 ; GCN-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: chain_hi_to_lo_flat_other_dep:
 ; GFX10:       ; %bb.0: ; %bb
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc_lo, v0, 2
+; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v0, 2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ushort v2, v[2:3] glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    flat_load_short_d16_hi v0, v[0:1] glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
 ; GFX10-NEXT:    v_bfi_b32 v0, 0xffff, v2, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]

llvm/test/CodeGen/AMDGPU/ctlz.ll

 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    global_load_ubyte v1, v0, s[2:3]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_ffbh_u32_sdwa v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0
 ; GFX10-NEXT:    v_cmp_ne_u16_e32 vcc_lo, 0, v1
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, 32, v2, vcc_lo
 ; GFX10-NEXT:    v_add_nc_u32_e32 v1, -16, v1
-; GFX10-NEXT:    v_add_nc_u16_e64 v1, v1, -8
+; GFX10-NEXT:    v_add_nc_u16 v1, v1, -8
 ; GFX10-NEXT:    global_store_byte v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
   %val = load i8, i8 addrspace(1)* %valptr
   %ctlz = call i8 @llvm.ctlz.i8(i8 %val, i1 false) nounwind readnone
   store i8 %ctlz, i8 addrspace(1)* %out
   ret void
 }
 

llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

 ; GFX10-NEXT:    s_waitcnt_depctr 0xffe3
 ; GFX10-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x24
 ; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x2c
 ; GFX10-NEXT:    s_movk_i32 s0, 0x900
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 16, v0
 ; GFX10-NEXT:    v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
 ; GFX10-NEXT:    v_and_b32_e32 v3, 0xffffff00, v0
-; GFX10-NEXT:    v_add_nc_u16_e64 v4, v0, 9
-; GFX10-NEXT:    v_add_nc_u16_e64 v2, v2, 9
+; GFX10-NEXT:    v_add_nc_u16 v4, v0, 9
+; GFX10-NEXT:    v_add_nc_u16 v2, v2, 9
 ; GFX10-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX10-NEXT:    v_or_b32_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    v_cvt_f32_ubyte3_e32 v3, v0
-; GFX10-NEXT:    v_add_nc_u16_e64 v1, v1, s0
-; GFX10-NEXT:    v_add_nc_u16_e64 v5, v2, s0
+; GFX10-NEXT:    v_add_nc_u16 v1, v1, s0
+; GFX10-NEXT:    v_add_nc_u16 v5, v2, s0
 ; GFX10-NEXT:    v_cvt_f32_ubyte2_e32 v2, v0
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v6, 16, v1
 ; GFX10-NEXT:    v_cvt_f32_ubyte1_e32 v1, v0
 ; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, v0
 ; GFX10-NEXT:    v_or_b32_sdwa v5, v5, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    global_store_dwordx4 v4, v[0:3], s[2:3]
 ; GFX10-NEXT:    global_store_dword v4, v5, s[4:5]

llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll

 ;
 ; GFX10-LABEL: s_add_co_select_user:
 ; GFX10:       ; %bb.0: ; %bb
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_mov_b64 s[4:5], 0
 ; GFX10-NEXT:    s_load_dword s4, s[4:5], 0x0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s5, s4, s4
+; GFX10-NEXT:    v_add_co_u32 v0, s5, s4, s4
 ; GFX10-NEXT:    s_cmpk_lg_u32 s5, 0x0
 ; GFX10-NEXT:    s_addc_u32 s5, s4, 0
 ; GFX10-NEXT:    s_cselect_b32 s6, 1, 0
 ; GFX10-NEXT:    s_cmp_gt_u32 s4, 31
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, s5, s6
 ; GFX10-NEXT:    s_cselect_b32 vcc_lo, -1, 0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]

llvm/test/CodeGen/AMDGPU/fshr.ll

 ; R600-NEXT:    PAD
 ;
 ; GFX10-LABEL: v_fshr_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_xor_b32_e32 v3, -1, v2
 ; GFX10-NEXT:    v_and_b32_e32 v2, 15, v2
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
 ; GFX10-NEXT:    v_and_b32_e32 v3, 15, v3
-; GFX10-NEXT:    v_lshrrev_b16_e64 v1, v2, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v3, v0
+; GFX10-NEXT:    v_lshrrev_b16 v1, v2, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v3, v0
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v1
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %ret = call i16 @llvm.fshr.i16(i16 %src0, i16 %src1, i16 %src2)
   ret i16 %ret
 }
 
 define <2 x i16> @v_fshr_v2i16(<2 x i16> %src0, <2 x i16> %src1, <2 x i16> %src2) {
 ; SI-LABEL: v_fshr_v2i16:

 ;
 ; GFX10-LABEL: v_fshr_v3i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v4
 ; GFX10-NEXT:    v_xor_b32_e32 v8, -1, v4
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 16, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
 ; GFX10-NEXT:    v_and_b32_e32 v4, 15, v4
 ; GFX10-NEXT:    v_and_b32_e32 v9, 15, v6
 ; GFX10-NEXT:    v_xor_b32_e32 v6, -1, v6
 ; GFX10-NEXT:    v_and_b32_e32 v15, 15, v8
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX10-NEXT:    v_lshrrev_b16_e64 v2, v4, v2
-; GFX10-NEXT:    v_lshlrev_b16_e64 v10, 1, v10
+; GFX10-NEXT:    v_lshrrev_b16 v2, v4, v2
+; GFX10-NEXT:    v_lshlrev_b16 v10, 1, v10
 ; GFX10-NEXT:    v_and_b32_e32 v19, 15, v6
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v15, v0
+; GFX10-NEXT:    v_lshlrev_b16 v0, v15, v0
 ; GFX10-NEXT:    v_xor_b32_e32 v11, -1, v5
-; GFX10-NEXT:    v_lshrrev_b16_e64 v4, v9, v7
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 1, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v6, v19, v10
+; GFX10-NEXT:    v_lshrrev_b16 v4, v9, v7
+; GFX10-NEXT:    v_lshlrev_b16 v1, 1, v1
+; GFX10-NEXT:    v_lshlrev_b16 v6, v19, v10
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_and_b32_e32 v7, 15, v11
 ; GFX10-NEXT:    v_and_b32_e32 v2, 15, v5
 ; GFX10-NEXT:    v_or_b32_e32 v11, v6, v4
 ; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, v7, v1
-; GFX10-NEXT:    v_lshrrev_b16_e64 v2, v2, v3
+; GFX10-NEXT:    v_lshlrev_b16 v1, v7, v1
+; GFX10-NEXT:    v_lshrrev_b16 v2, v2, v3
 ; GFX10-NEXT:    v_lshl_or_b32 v0, v11, 16, v0
 ; GFX10-NEXT:    v_or_b32_e32 v1, v1, v2
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %ret = call <3 x i16> @llvm.fshr.v3i16(<3 x i16> %src0, <3 x i16> %src1, <3 x i16> %src2)
   ret <3 x i16> %ret
 }
 
 define <4 x i16> @v_fshr_v4i16(<4 x i16> %src0, <4 x i16> %src1, <4 x i16> %src2) {

 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v6, 16, v5
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v8, 16, v1
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v10, 16, v4
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 16, v3
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v11, 16, v0
 ; GFX10-NEXT:    v_xor_b32_e32 v9, -1, v6
 ; GFX10-NEXT:    v_and_b32_e32 v6, 15, v6
-; GFX10-NEXT:    v_lshlrev_b16_e64 v8, 1, v8
+; GFX10-NEXT:    v_lshlrev_b16 v8, 1, v8
 ; GFX10-NEXT:    v_and_b32_e32 v13, 15, v10
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 1, v1
+; GFX10-NEXT:    v_lshlrev_b16 v1, 1, v1
 ; GFX10-NEXT:    v_and_b32_e32 v9, 15, v9
-; GFX10-NEXT:    v_lshrrev_b16_e64 v6, v6, v7
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 1, v0
+; GFX10-NEXT:    v_lshrrev_b16 v6, v6, v7
+; GFX10-NEXT:    v_lshlrev_b16 v0, 1, v0
 ; GFX10-NEXT:    v_lshrrev_b32_e32 v12, 16, v2
-; GFX10-NEXT:    v_lshlrev_b16_e64 v11, 1, v11
-; GFX10-NEXT:    v_lshlrev_b16_e64 v7, v9, v8
+; GFX10-NEXT:    v_lshlrev_b16 v11, 1, v11
+; GFX10-NEXT:    v_lshlrev_b16 v7, v9, v8
 ; GFX10-NEXT:    v_xor_b32_e32 v9, -1, v10
 ; GFX10-NEXT:    v_xor_b32_e32 v10, -1, v5
 ; GFX10-NEXT:    v_xor_b32_e32 v8, -1, v4
 ; GFX10-NEXT:    v_and_b32_e32 v4, 15, v4
 ; GFX10-NEXT:    v_and_b32_e32 v5, 15, v5
 ; GFX10-NEXT:    v_and_b32_e32 v9, 15, v9
 ; GFX10-NEXT:    v_and_b32_e32 v10, 15, v10
 ; GFX10-NEXT:    v_and_b32_e32 v15, 15, v8
-; GFX10-NEXT:    v_lshrrev_b16_e64 v2, v4, v2
-; GFX10-NEXT:    v_lshrrev_b16_e64 v3, v5, v3
-; GFX10-NEXT:    v_lshrrev_b16_e64 v4, v13, v12
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, v10, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, v15, v0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v5, v9, v11
+; GFX10-NEXT:    v_lshrrev_b16 v2, v4, v2
+; GFX10-NEXT:    v_lshrrev_b16 v3, v5, v3
+; GFX10-NEXT:    v_lshrrev_b16 v4, v13, v12
+; GFX10-NEXT:    v_lshlrev_b16 v1, v10, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, v15, v0
+; GFX10-NEXT:    v_lshlrev_b16 v5, v9, v11
 ; GFX10-NEXT:    v_or_b32_e32 v1, v1, v3
 ; GFX10-NEXT:    v_or_b32_e32 v0, v0, v2
 ; GFX10-NEXT:    v_mov_b32_e32 v2, 0xffff
 ; GFX10-NEXT:    v_or_b32_e32 v3, v7, v6
 ; GFX10-NEXT:    v_or_b32_e32 v7, v5, v4
 ; GFX10-NEXT:    v_and_b32_e32 v0, v2, v0
 ; GFX10-NEXT:    v_and_b32_e32 v1, v2, v1
 ; GFX10-NEXT:    v_lshl_or_b32 v0, v7, 16, v0

llvm/test/CodeGen/AMDGPU/gfx10-vop-literal.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
 
 ; GCN-LABEL: {{^}}test_add_lit:
-; GFX10: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, 0x80992bff, v{{[0-9]+}}
+; GFX10: v_add_co_u32 v{{[0-9]+}}, vcc_lo, 0x80992bff, v{{[0-9]+}}
 ; GFX10: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0xe7, v{{[0-9]+}}, vcc_lo
 ; GFX9:  v_mov_b32_e32 [[C2:v[0-9]+]], 0xe7
 ; GFX9:  v_add_co_u32_e32 v{{[0-9]+}}, vcc, 0x80992bff, v{{[0-9]+}}
 ; GFX9:  v_addc_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, [[C2]], vcc
 define amdgpu_kernel void @test_add_lit(i64 addrspace(1)* %p) {
   %id = tail call i32 @llvm.amdgcn.workitem.id.x()
   %ptr = getelementptr inbounds i64, i64 addrspace(1)* %p, i32 %id
   %load = load i64, i64 addrspace(1)* %ptr, align 8

llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    global_atomic_swap v0, v0, v1, s[2:3] offset:2048 glc
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    buffer_wbinvl1
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_xchg_saddr_i32_rtn_2048:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s[0:1], s3, 0, s[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v2, vcc, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v2, vcc, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc, 0, v3, vcc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    global_atomic_swap v0, v[2:3], v1, off glc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    buffer_gl0_inv
 ; GFX10-NEXT:    buffer_gl1_inv
 ; GFX10-NEXT:    ; return to shader part epilog

llvm/test/CodeGen/AMDGPU/global-saddr-load.ll

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3] offset:-4096
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_neg4096:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0xfffff000, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0xfffff000, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4096
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float

 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_neg4097:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0xfffff000, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0xfffff000, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4097
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float

 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-2
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_neg4098:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0xfffff000, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0xfffff000, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-2
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4098
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float

 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3] offset:-2049
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_neg2049:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0xfffff800, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0xfffff800, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -2049
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 ; SGPR base with maximum negative gfx10 immediate offset - 1
 define amdgpu_ps float @global_load_saddr_i8_offset_neg2050(i8 addrspace(1)* inreg %sbase) {
 ; GFX9-LABEL: global_load_saddr_i8_offset_neg2050:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3] offset:-2050
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_neg2050:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0xfffff800, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0xfffff800, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-2
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -2050
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float

 ; GFX9-NEXT:    v_add_co_u32_e64 v0, vcc, 0, s2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_4294967296:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4294967296
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 define amdgpu_ps float @global_load_saddr_i8_offset_4294967297(i8 addrspace(1)* inreg %sbase) {
 ; GFX9-LABEL: global_load_saddr_i8_offset_4294967297:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, vcc, 0, s2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:1
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_4294967297:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4294967297
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 define amdgpu_ps float @global_load_saddr_i8_offset_4294971391(i8 addrspace(1)* inreg %sbase) {
 ; GFX9-LABEL: global_load_saddr_i8_offset_4294971391:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, vcc, 0, s2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_4294971391:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0x800, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0x800, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4294971391
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 define amdgpu_ps float @global_load_saddr_i8_offset_4294971392(i8 addrspace(1)* inreg %sbase) {
 ; GFX9-LABEL: global_load_saddr_i8_offset_4294971392:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_4294971392:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0x1000, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0x1000, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], 1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4294971392
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 define amdgpu_ps float @global_load_saddr_i8_offset_neg4294967295(i8 addrspace(1)* inreg %sbase) {
 ; GFX9-LABEL: global_load_saddr_i8_offset_neg4294967295:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_neg4294967295:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0x800, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0x800, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4294967295
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 define amdgpu_ps float @global_load_saddr_i8_offset_neg4294967296(i8 addrspace(1)* inreg %sbase) {
 ; GFX9-LABEL: global_load_saddr_i8_offset_neg4294967296:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, vcc, 0, s2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_neg4294967296:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4294967296
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 define amdgpu_ps float @global_load_saddr_i8_offset_neg4294967297(i8 addrspace(1)* inreg %sbase) {
 ; GFX9-LABEL: global_load_saddr_i8_offset_neg4294967297:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX9-NEXT:    v_add_co_u32_e64 v0, vcc, 0, s2
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_offset_neg4294967297:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], 0, s2
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], 0, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], -1, s3, s[0:1]
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 -4294967297
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float

 ; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3] offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 4095
   %load = load i8, i8 addrspace(1)* %gep1

 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_4096:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, 0x1000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, 0x1000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 4096
   %load = load i8, i8 addrspace(1)* %gep1
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 ; Maximum negative offset on gfx9
 define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg4096(i8 addrspace(1)* inreg %sbase, i32 %voffset) {
 ; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4096:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3] offset:-4096
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4096:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, 0xfffff000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, 0xfffff000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -4096
   %load = load i8, i8 addrspace(1)* %gep1

 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xfffff000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4097:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, 0xfffff000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, 0xfffff000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -4097
   %load = load i8, i8 addrspace(1)* %gep1

 ; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_2048:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3] offset:2048
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_2048:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 2048
   %load = load i8, i8 addrspace(1)* %gep1

 ; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2049:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3] offset:-2049
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2049:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, 0xfffff800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, 0xfffff800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 -2049
   %load = load i8, i8 addrspace(1)* %gep1
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 ; Maximum positive offset on gfx9, and immediate needs to be moved lower.
 define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4095_gep_order(i8 addrspace(1)* inreg %sbase, i32 %voffset) {
 ; GFX9-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095_gep_order:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    global_load_ubyte v0, v0, s[2:3] offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095_gep_order:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s[0:1], s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, s[0:1], s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s[0:1], s3, 0, s[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %voffset to i64
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %sbase, i64 4095
   %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 %zext.offset
   %load = load i8, i8 addrspace(1)* %gep1

 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s2, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_i8_vgpr64_sgpr32:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, v0, s2
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, v0, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %soffset to i64
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %vbase, i64 %zext.offset
   %load = load i8, i8 addrspace(1)* %gep0
   %zext = zext i8 %load to i32
   %to.vgpr = bitcast i32 %zext to float
   ret float %to.vgpr
 }
 
 ; divergent 64-bit base, 32-bit scalar offset, with imm offset
 define amdgpu_ps float @global_load_i8_vgpr64_sgpr32_offset_4095(i8 addrspace(1)* %vbase, i32 inreg %soffset) {
 ; GFX9-LABEL: global_load_i8_vgpr64_sgpr32_offset_4095:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s2, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_i8_vgpr64_sgpr32_offset_4095:
 ; GFX10:       ; %bb.0:
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, v0, s2
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, v0, s2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %zext.offset = zext i32 %soffset to i64
   %gep0 = getelementptr inbounds i8, i8 addrspace(1)* %vbase, i64 %zext.offset
   %gep1 = getelementptr inbounds i8, i8 addrspace(1)* %gep0, i64 4095
   %load = load i8, i8 addrspace(1)* %gep1

 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_saddr_f32_natural_addressing:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    global_load_dword v0, v[0:1], off
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, s3, v1, vcc
 ; GFX10-NEXT:    global_load_dword v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %voffset = load i32, i32 addrspace(1)* %voffset.ptr
   %zext.offset = zext i32 %voffset to i64
   %gep = getelementptr inbounds float, float addrspace(1)* %sbase, i64 %zext.offset
   %load = load float, float addrspace(1)* %gep

 ; GFX9-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-LABEL: global_load_f32_saddr_zext_vgpr_range_too_large:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    global_load_dword v0, v[0:1], off
 ; GFX10-NEXT:    v_mov_b32_e32 v1, 0
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    v_lshlrev_b64 v[0:1], 2, v[0:1]
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc, s2, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc, s2, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc, s3, v1, vcc
 ; GFX10-NEXT:    global_load_dword v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    ; return to shader part epilog
   %voffset = load i32, i32 addrspace(1)* %voffset.ptr, !range !1
   %zext.offset = zext i32 %voffset to i64
   %gep = getelementptr inbounds float, float addrspace(1)* %sbase, i64 %zext.offset
   %load = load float, float addrspace(1)* %gep

llvm/test/CodeGen/AMDGPU/idiv-licm.ll

 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_and_b32 s0, s1, s4
 ; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s0
 ; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v0
 ; GFX10-NEXT:  BB4_1: ; %bb3
 ; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX10-NEXT:    v_and_b32_e32 v2, s1, v4
-; GFX10-NEXT:    v_add_nc_u16_e64 v4, v4, 1
+; GFX10-NEXT:    v_add_nc_u16 v4, v4, 1
 ; GFX10-NEXT:    v_cvt_f32_u32_e32 v7, v2
 ; GFX10-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
 ; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
 ; GFX10-NEXT:    v_mul_f32_e32 v2, v7, v1
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s0, s2, v5
+; GFX10-NEXT:    v_add_co_u32 v5, s0, s2, v5
 ; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
 ; GFX10-NEXT:    v_trunc_f32_e32 v2, v2
 ; GFX10-NEXT:    v_mad_f32 v7, -v2, v0, v7
 ; GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v2
 ; GFX10-NEXT:    v_cmp_ge_f32_e64 s0, |v7|, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s0, 0, v2, s0
 ; GFX10-NEXT:    global_store_short v[5:6], v7, off

 ; GFX10-NEXT:    v_mov_b32_e32 v4, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_and_b32 s4, s1, s4
 ; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s4
 ; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v0
 ; GFX10-NEXT:  BB5_1: ; %bb3
 ; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX10-NEXT:    v_and_b32_e32 v2, s1, v4
-; GFX10-NEXT:    v_add_nc_u16_e64 v4, v4, 1
+; GFX10-NEXT:    v_add_nc_u16 v4, v4, 1
 ; GFX10-NEXT:    v_cvt_f32_u32_e32 v7, v2
 ; GFX10-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
 ; GFX10-NEXT:    v_mul_f32_e32 v8, v7, v1
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s0, s2, v5
+; GFX10-NEXT:    v_add_co_u32 v5, s0, s2, v5
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
 ; GFX10-NEXT:    v_trunc_f32_e32 v10, v8
 ; GFX10-NEXT:    v_mad_f32 v7, -v10, v0, v7
 ; GFX10-NEXT:    v_cvt_u32_f32_e32 v8, v10
 ; GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v7|, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v8, vcc_lo
 ; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
 ; GFX10-NEXT:    v_mul_lo_u32 v7, v7, s4

 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_sext_i32_i16 s4, s4
 ; GFX10-NEXT:    v_cvt_f32_i32_e32 v0, s4
 ; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v0
 ; GFX10-NEXT:  BB6_1: ; %bb3
 ; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX10-NEXT:    v_bfe_i32 v5, v4, 0, 16
 ; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v4
-; GFX10-NEXT:    v_add_nc_u16_e64 v4, v4, 1
+; GFX10-NEXT:    v_add_nc_u16 v4, v4, 1
 ; GFX10-NEXT:    v_cvt_f32_i32_e32 v7, v5
 ; GFX10-NEXT:    v_xor_b32_e32 v8, s4, v5
 ; GFX10-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
 ; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
 ; GFX10-NEXT:    v_mul_f32_e32 v2, v7, v1
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v8, 30, v8
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s0, s2, v5
+; GFX10-NEXT:    v_add_co_u32 v5, s0, s2, v5
 ; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, vcc_lo
 ; GFX10-NEXT:    v_trunc_f32_e32 v2, v2
 ; GFX10-NEXT:    v_or_b32_e32 v8, 1, v8
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
 ; GFX10-NEXT:    v_mad_f32 v7, -v2, v0, v7
 ; GFX10-NEXT:    v_cvt_i32_f32_e32 v2, v2
 ; GFX10-NEXT:    v_cmp_ge_f32_e64 s1, |v7|, |v0|
 ; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, v8, s1

 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_sext_i32_i16 s1, s4
 ; GFX10-NEXT:    v_cvt_f32_i32_e32 v0, s1
 ; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v0
 ; GFX10-NEXT:  BB7_1: ; %bb3
 ; GFX10-NEXT:    ; =>This Inner Loop Header: Depth=1
 ; GFX10-NEXT:    v_bfe_i32 v7, v4, 0, 16
 ; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v4
-; GFX10-NEXT:    v_add_nc_u16_e64 v4, v4, 1
+; GFX10-NEXT:    v_add_nc_u16 v4, v4, 1
 ; GFX10-NEXT:    v_cvt_f32_i32_e32 v11, v7
 ; GFX10-NEXT:    v_xor_b32_e32 v6, s1, v7
 ; GFX10-NEXT:    v_mul_f32_e32 v8, v11, v1
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v6, 30, v6
 ; GFX10-NEXT:    v_trunc_f32_e32 v10, v8
 ; GFX10-NEXT:    v_or_b32_e32 v6, 1, v6
 ; GFX10-NEXT:    v_mad_f32 v5, -v10, v0, v11
 ; GFX10-NEXT:    v_cvt_i32_f32_e32 v8, v10
 ; GFX10-NEXT:    v_cmp_ge_f32_e64 vcc_lo, |v5|, |v0|
 ; GFX10-NEXT:    v_cndmask_b32_e32 v9, 0, v6, vcc_lo
 ; GFX10-NEXT:    v_lshlrev_b64 v[5:6], 1, v[2:3]
 ; GFX10-NEXT:    v_cmp_eq_u16_e32 vcc_lo, 0x400, v4
 ; GFX10-NEXT:    v_add_nc_u32_e32 v2, v8, v9
-; GFX10-NEXT:    v_add_co_u32_e64 v5, s0, s2, v5
+; GFX10-NEXT:    v_add_co_u32 v5, s0, s2, v5
 ; GFX10-NEXT:    s_and_b32 vcc_lo, exec_lo, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s0, s3, v6, s0
 ; GFX10-NEXT:    v_mul_lo_u32 v2, v2, s1
 ; GFX10-NEXT:    v_sub_nc_u32_e32 v7, v7, v2
 ; GFX10-NEXT:    global_store_short v[5:6], v7, off
 ; GFX10-NEXT:    s_cbranch_vccz BB7_1
 ; GFX10-NEXT:  ; %bb.2: ; %bb2
 ; GFX10-NEXT:    s_endpgm

llvm/test/CodeGen/AMDGPU/idot2.ll

 ; GFX10-DL-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
 ; GFX10-DL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX10-DL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-DL-NEXT:    s_clause 0x1
 ; GFX10-DL-NEXT:    global_load_ushort v1, v0, s[4:5]
 ; GFX10-DL-NEXT:    global_load_ushort v2, v0, s[6:7]
 ; GFX10-DL-NEXT:    s_load_dword s2, s[0:1], 0x0
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT:    v_lshrrev_b16_e64 v0, 8, v1
+; GFX10-DL-NEXT:    v_lshrrev_b16 v0, 8, v1
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT:    v_lshrrev_b16_e64 v3, 8, v2
+; GFX10-DL-NEXT:    v_lshrrev_b16 v3, 8, v2
 ; GFX10-DL-NEXT:    v_mul_i32_i24_sdwa v1, sext(v2), sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
 ; GFX10-DL-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-DL-NEXT:    v_mul_i32_i24_sdwa v0, sext(v3), sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
 ; GFX10-DL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-DL-NEXT:    v_add3_u32 v0, v0, s2, v1
 ; GFX10-DL-NEXT:    global_store_dword v2, v0, s[0:1]
 ; GFX10-DL-NEXT:    s_endpgm
                                           <2 x i8> addrspace(1)* %src2,

llvm/test/CodeGen/AMDGPU/idot4s.ll

 ; GFX10-DL-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-DL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34
 ; GFX10-DL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-DL-NEXT:    s_clause 0x1
 ; GFX10-DL-NEXT:    global_load_dword v1, v0, s[4:5]
 ; GFX10-DL-NEXT:    global_load_dword v2, v0, s[6:7]
 ; GFX10-DL-NEXT:    s_load_dword s2, s[0:1], 0x0
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT:    v_lshrrev_b16_e64 v0, 8, v1
+; GFX10-DL-NEXT:    v_lshrrev_b16 v0, 8, v1
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT:    v_lshrrev_b16_e64 v3, 8, v2
+; GFX10-DL-NEXT:    v_lshrrev_b16 v3, 8, v2
 ; GFX10-DL-NEXT:    v_mul_i32_i24_sdwa v7, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
 ; GFX10-DL-NEXT:    v_mul_i32_i24_sdwa v0, sext(v0), sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0
 ; GFX10-DL-NEXT:    v_mul_i32_i24_sdwa v3, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2
 ; GFX10-DL-NEXT:    v_mul_i32_i24_sdwa v1, sext(v1), sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3
 ; GFX10-DL-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-DL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-DL-NEXT:    v_add3_u32 v0, v7, s2, v0
 ; GFX10-DL-NEXT:    v_add3_u32 v0, v0, v3, v1

 ; GFX10-DL-NEXT:    v_mov_b32_e32 v4, 0xffff
 ; GFX10-DL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-DL-NEXT:    s_clause 0x1
 ; GFX10-DL-NEXT:    global_load_dword v1, v0, s[4:5]
 ; GFX10-DL-NEXT:    global_load_dword v2, v0, s[6:7]
 ; GFX10-DL-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-DL-NEXT:    global_load_ushort v3, v0, s[0:1]
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(2)
-; GFX10-DL-NEXT:    v_ashrrev_i16_e64 v5, 8, v1
+; GFX10-DL-NEXT:    v_ashrrev_i16 v5, 8, v1
 ; GFX10-DL-NEXT:    v_and_b32_sdwa v8, v4, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT:    v_ashrrev_i16_e64 v6, 8, v2
+; GFX10-DL-NEXT:    v_ashrrev_i16 v6, 8, v2
 ; GFX10-DL-NEXT:    v_and_b32_sdwa v7, v4, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v1, 16, v1
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v2, 16, v2
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v5, v5, 16, v8
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v6, v6, 16, v7
-; GFX10-DL-NEXT:    v_ashrrev_i16_e64 v7, 8, v1
+; GFX10-DL-NEXT:    v_ashrrev_i16 v7, 8, v1
 ; GFX10-DL-NEXT:    v_and_b32_sdwa v1, v4, sext(v1) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
-; GFX10-DL-NEXT:    v_ashrrev_i16_e64 v8, 8, v2
+; GFX10-DL-NEXT:    v_ashrrev_i16 v8, 8, v2
 ; GFX10-DL-NEXT:    v_and_b32_sdwa v2, v4, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX10-DL-NEXT:    v_pk_mul_lo_u16 v4, v5, v6
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v1, v7, 16, v1
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v2, v8, 16, v2
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v4, v3
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v4, v3
 ; GFX10-DL-NEXT:    v_pk_mul_lo_u16 v1, v1, v2
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v2, v3, v5
+; GFX10-DL-NEXT:    v_add_nc_u16 v2, v3, v5
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v2, v1
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v1, v3
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v2, v1
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v1, v3
 ; GFX10-DL-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-DL-NEXT:    s_endpgm
                                               <4 x i8> addrspace(1)* %src2,
                                               i16 addrspace(1)* nocapture %dst) {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gep1 = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %src1, i32 %idx
   %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %gep1

llvm/test/CodeGen/AMDGPU/idot4u.ll

 ; GFX10-DL-NEXT:    s_movk_i32 s2, 0xff
 ; GFX10-DL-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-DL-NEXT:    s_clause 0x1
 ; GFX10-DL-NEXT:    global_load_dword v1, v0, s[4:5]
 ; GFX10-DL-NEXT:    global_load_dword v2, v0, s[6:7]
 ; GFX10-DL-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-DL-NEXT:    global_load_ushort v3, v0, s[0:1]
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(2)
-; GFX10-DL-NEXT:    v_lshrrev_b16_e64 v5, 8, v1
+; GFX10-DL-NEXT:    v_lshrrev_b16 v5, 8, v1
 ; GFX10-DL-NEXT:    v_and_b32_sdwa v8, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(1)
-; GFX10-DL-NEXT:    v_lshrrev_b16_e64 v6, 8, v2
+; GFX10-DL-NEXT:    v_lshrrev_b16 v6, 8, v2
 ; GFX10-DL-NEXT:    v_and_b32_sdwa v7, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
 ; GFX10-DL-NEXT:    v_and_b32_sdwa v9, v1, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-DL-NEXT:    v_and_b32_sdwa v10, v2, s2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v5, v5, 16, v8
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v1, 24, v1
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v6, v6, 16, v7
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v2, 24, v2
 ; GFX10-DL-NEXT:    v_and_b32_e32 v7, v4, v10
 ; GFX10-DL-NEXT:    v_and_b32_e32 v4, v4, v9
 ; GFX10-DL-NEXT:    v_pk_mul_lo_u16 v5, v5, v6
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v2, v2, 16, v7
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v1, v1, 16, v4
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v4, 16, v5
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v5, v3
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v5, v3
 ; GFX10-DL-NEXT:    v_pk_mul_lo_u16 v1, v1, v2
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v2, v3, v4
+; GFX10-DL-NEXT:    v_add_nc_u16 v2, v3, v4
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v2, v1
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v1, v3
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v2, v1
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v1, v3
 ; GFX10-DL-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-DL-NEXT:    s_endpgm
                                               <4 x i8> addrspace(1)* %src2,
                                               i16 addrspace(1)* nocapture %dst) {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gep1 = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %src1, i32 %idx
   %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %gep1

 ; GFX10-DL-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-DL-NEXT:    global_load_ubyte v3, v0, s[0:1]
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(2)
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v4, 24, v1
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v5, 24, v2
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v6, 16, v1
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v7, 16, v2
-; GFX10-DL-NEXT:    v_lshrrev_b16_e64 v8, 8, v2
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v4, v4, v5
-; GFX10-DL-NEXT:    v_lshrrev_b16_e64 v5, 8, v1
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v9, v6, v7
+; GFX10-DL-NEXT:    v_lshrrev_b16 v8, 8, v2
+; GFX10-DL-NEXT:    v_mul_lo_u16 v4, v4, v5
+; GFX10-DL-NEXT:    v_lshrrev_b16 v5, 8, v1
+; GFX10-DL-NEXT:    v_mul_lo_u16 v9, v6, v7
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-DL-NEXT:    v_mad_u16 v3, v1, v2, v3
-; GFX10-DL-NEXT:    v_lshlrev_b16_e64 v4, 8, v4
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v5, v5, v8
+; GFX10-DL-NEXT:    v_lshlrev_b16 v4, 8, v4
+; GFX10-DL-NEXT:    v_mul_lo_u16 v5, v5, v8
 ; GFX10-DL-NEXT:    v_or_b32_sdwa v4, v9, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-NEXT:    v_lshlrev_b16_e64 v5, 8, v5
+; GFX10-DL-NEXT:    v_lshlrev_b16 v5, 8, v5
 ; GFX10-DL-NEXT:    v_lshlrev_b32_e32 v8, 16, v4
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v2, 8, v4
 ; GFX10-DL-NEXT:    v_or_b32_sdwa v5, v5, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v5, 8, v5
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v3, v5
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v3, v5
 ; GFX10-DL-NEXT:    v_mad_u16 v1, v6, v7, v1
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v1, v2
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v1, v2
 ; GFX10-DL-NEXT:    global_store_byte v0, v1, s[0:1]
 ; GFX10-DL-NEXT:    s_endpgm
                                              <4 x i8> addrspace(1)* %src2,
                                              i8 addrspace(1)* nocapture %dst) {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gep1 = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %src1, i32 %idx
   %vec1 = load <4 x i8>, <4 x i8> addrspace(1)* %gep1

llvm/test/CodeGen/AMDGPU/idot8s.ll

 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v5, 24, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v6, 20, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v8, 12, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v9, 8, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v10, 4, v1
 ; GFX10-DL-XNACK-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v16, 4, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v17, 12, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v1, 12, v1
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v17, 12, v2
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v1, 12, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v11, 28, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v10
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v16, 12, v16
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v10, 12, v10
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v16, 12, v16
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v12, 24, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v13, 20, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v14, 16, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v15, 12, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v18, 12, v1
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v17, 12, v17
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v9
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v10, 12, v10
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v2, 12, v2
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v16, 12, v16
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v18, 12, v1
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v17, 12, v17
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v9, 12, v9
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v10, 12, v10
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v2, 12, v2
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v16, 12, v16
 ; GFX10-DL-XNACK-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v18, v17, v3
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v8
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v9
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v15
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v2, 12, v2
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v8, 12, v8
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v3, 12, v9
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v9, 12, v15
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v2, 12, v2
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v10, v16, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v7
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v14
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v8, 12, v8
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v15, 12, v9
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v7, 12, v7
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v10, 12, v14
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v8, 12, v8
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v15, 12, v9
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v3, v2, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v6, 12, v6
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v2, 12, v7
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v13
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v10
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v6, 12, v6
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v2, 12, v7
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v7, 12, v13
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v3, 12, v10
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v8, v15, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v5
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v12
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v6, 12, v6
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v7
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v5, 12, v5
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v8, 12, v12
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v6, 12, v6
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v7, 12, v7
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v2, v3, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v4, 12, v4
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v2, 12, v5
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v8
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v11
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v4, 12, v4
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v2, 12, v5
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v3, 12, v8
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v5, 12, v11
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v6, v7, v1
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v4, 12, v4
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v5
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v4, 12, v4
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v7, 12, v5
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v2, v3, v1
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v4, v7, v1
 ; GFX10-DL-XNACK-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-DL-XNACK-NEXT:    s_endpgm
 ;
 ; GFX10-DL-NOXNACK-LABEL: idot8_acc16:
 ; GFX10-DL-NOXNACK:       ; %bb.0: ; %entry
 ; GFX10-DL-NOXNACK-NEXT:    s_clause 0x1

 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v5, 24, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v6, 20, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v8, 12, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v9, 8, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v10, 4, v1
 ; GFX10-DL-NOXNACK-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v16, 4, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v17, 12, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v1, 12, v1
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v17, 12, v0
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v1, 12, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v10
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v16, 12, v16
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v10, 12, v10
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v16, 12, v16
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v12, 24, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v13, 20, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v14, 16, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v15, 12, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v18, 12, v1
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v17, 12, v17
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v9
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v10, 12, v10
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v0, 12, v0
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v16, 12, v16
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v18, 12, v1
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v17, 12, v17
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v9, 12, v9
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v10, 12, v10
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v0, 12, v0
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v16, 12, v16
 ; GFX10-DL-NOXNACK-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v1, v18, v17, v3
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v9
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v15
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v8
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v0, 12, v0
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v3, 12, v9
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v9, 12, v15
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v8, 12, v8
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v0, 12, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v1, v10, v16, v1
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v7
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v14
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v15, 12, v8
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v9, 12, v9
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v7, 12, v7
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v10, 12, v14
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v15, 12, v8
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v9, 12, v9
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v3, v0, v1
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v6, 12, v6
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v1, 12, v7
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v13
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v10
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v1, 12, v7
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v7, 12, v13
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v3, 12, v10
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v15, v9, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v5
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v12
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v6, 12, v6
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v7
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v5, 12, v5
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v8, 12, v12
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v7, 12, v7
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v1, v3, v0
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v1, 12, v5
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v11
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v8
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v4, 12, v4
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v1, 12, v5
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v5, 12, v11
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v3, 12, v8
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v4, 12, v4
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v6, v7, v0
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v5, 12, v5
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v4
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v5, 12, v5
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v7, 12, v4
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v1, v3, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v7, v5, v0
 ; GFX10-DL-NOXNACK-NEXT:    global_store_short v2, v0, s[0:1]
 ; GFX10-DL-NOXNACK-NEXT:    s_endpgm
 ; GFX10-DL-LABEL: idot8_acc16:
 ; GFX10-DL:       ; %bb.0: ; %entry
 ; GFX10-DL-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
 ; GFX10-DL-NEXT:    v_mov_b32_e32 v0, 0

 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v5, 24, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v6, 20, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v8, 12, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v9, 8, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v10, 4, v1
 ; GFX10-DL-XNACK-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v16, 4, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v17, 12, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v1, 12, v1
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v17, 12, v2
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v1, 12, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v11, 28, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v10
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v16, 12, v16
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v10, 12, v10
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v16, 12, v16
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v12, 24, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v13, 20, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v14, 16, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v15, 12, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v2, 8, v2
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v18, 12, v1
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v17, 12, v17
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v9
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v10, 12, v10
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v2, 12, v2
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v16, 12, v16
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v18, 12, v1
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v17, 12, v17
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v9, 12, v9
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v10, 12, v10
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v2, 12, v2
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v16, 12, v16
 ; GFX10-DL-XNACK-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v18, v17, v3
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v8
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v9
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v15
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v2, 12, v2
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v8, 12, v8
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v3, 12, v9
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v9, 12, v15
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v2, 12, v2
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v10, v16, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v7
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v14
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v8, 12, v8
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v15, 12, v9
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v7, 12, v7
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v10, 12, v14
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v8, 12, v8
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v15, 12, v9
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v3, v2, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v6, 12, v6
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v2, 12, v7
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v13
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v10
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v6, 12, v6
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v2, 12, v7
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v7, 12, v13
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v3, 12, v10
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v8, v15, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v5
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v12
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v6, 12, v6
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v7
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v5, 12, v5
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v8, 12, v12
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v6, 12, v6
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v7, 12, v7
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v2, v3, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v4, 12, v4
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v2, 12, v5
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v8
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v11
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v4, 12, v4
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v2, 12, v5
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v3, 12, v8
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v5, 12, v11
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v6, v7, v1
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v4, 12, v4
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v5
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v4, 12, v4
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v7, 12, v5
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v2, v3, v1
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v1, v4, v7, v1
 ; GFX10-DL-XNACK-NEXT:    global_store_byte v0, v1, s[0:1]
 ; GFX10-DL-XNACK-NEXT:    s_endpgm
 ;
 ; GFX10-DL-NOXNACK-LABEL: idot8_acc8:
 ; GFX10-DL-NOXNACK:       ; %bb.0: ; %entry
 ; GFX10-DL-NOXNACK-NEXT:    s_clause 0x1

 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v5, 24, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v6, 20, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v7, 16, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v8, 12, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v9, 8, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v10, 4, v1
 ; GFX10-DL-NOXNACK-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v16, 4, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v17, 12, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v1, 12, v1
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v17, 12, v0
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v1, 12, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v11, 28, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v10
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v16, 12, v16
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v10, 12, v10
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v16, 12, v16
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v12, 24, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v13, 20, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v14, 16, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v15, 12, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v0, 8, v0
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v18, 12, v1
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v17, 12, v17
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v9
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v10, 12, v10
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v0, 12, v0
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v16, 12, v16
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v18, 12, v1
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v17, 12, v17
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v9, 12, v9
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v10, 12, v10
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v0, 12, v0
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v16, 12, v16
 ; GFX10-DL-NOXNACK-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v1, v18, v17, v3
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v9
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v15
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v8
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v0, 12, v0
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v3, 12, v9
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v9, 12, v15
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v8, 12, v8
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v0, 12, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v1, v10, v16, v1
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v7
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v14
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v15, 12, v8
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v9, 12, v9
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v7, 12, v7
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v10, 12, v14
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v15, 12, v8
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v9, 12, v9
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v3, v0, v1
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v6, 12, v6
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v1, 12, v7
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v13
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v10
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v1, 12, v7
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v7, 12, v13
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v3, 12, v10
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v15, v9, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v5
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v12
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v6, 12, v6
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v7
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v5, 12, v5
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v8, 12, v12
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v7, 12, v7
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v1, v3, v0
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v1, 12, v5
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v11
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v8
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v4, 12, v4
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v1, 12, v5
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v5, 12, v11
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v3, 12, v8
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v4, 12, v4
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v6, v7, v0
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v5, 12, v5
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v4
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v5, 12, v5
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v7, 12, v4
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v1, v3, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v7, v5, v0
 ; GFX10-DL-NOXNACK-NEXT:    global_store_byte v2, v0, s[0:1]
 ; GFX10-DL-NOXNACK-NEXT:    s_endpgm
 ; GFX10-DL-LABEL: idot8_acc8:
 ; GFX10-DL:       ; %bb.0: ; %entry
 ; GFX10-DL-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
 ; GFX10-DL-NEXT:    v_mov_b32_e32 v0, 0

 ; GFX10-DL-XNACK-NEXT:    v_pk_lshlrev_b16 v2, 12, v2 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_pk_mul_lo_u16 v1, v1, v8
 ; GFX10-DL-XNACK-NEXT:    v_pk_ashrrev_i16 v9, 12, v9 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_lshl_or_b32 v8, v17, 16, v10
 ; GFX10-DL-XNACK-NEXT:    v_pk_ashrrev_i16 v7, 12, v7 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_pk_ashrrev_i16 v2, 12, v2 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v10, 16, v1
 ; GFX10-DL-XNACK-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v1, v1, v3
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v1, v1, v3
 ; GFX10-DL-XNACK-NEXT:    v_and_b32_e32 v3, v4, v5
 ; GFX10-DL-XNACK-NEXT:    v_pk_lshlrev_b16 v5, 12, v8 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_and_b32_e32 v4, v4, v19
 ; GFX10-DL-XNACK-NEXT:    v_pk_mul_lo_u16 v2, v9, v2
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v1, v1, v10
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v1, v1, v10
 ; GFX10-DL-XNACK-NEXT:    v_lshl_or_b32 v3, v6, 16, v3
 ; GFX10-DL-XNACK-NEXT:    v_pk_ashrrev_i16 v5, 12, v5 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_lshl_or_b32 v4, v14, 16, v4
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v6, 16, v2
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v1, v1, v2
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v1, v1, v2
 ; GFX10-DL-XNACK-NEXT:    v_pk_lshlrev_b16 v2, 12, v3 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_pk_lshlrev_b16 v3, 12, v4 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_pk_mul_lo_u16 v4, v7, v5
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v1, v1, v6
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v1, v1, v6
 ; GFX10-DL-XNACK-NEXT:    v_pk_ashrrev_i16 v2, 12, v2 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_pk_ashrrev_i16 v3, 12, v3 op_sel_hi:[0,1]
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v7, v1, v4
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v7, v1, v4
 ; GFX10-DL-XNACK-NEXT:    v_pk_mul_lo_u16 v2, v2, v3
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v1, v7, v5
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v1, v7, v5
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v1, v1, v2
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v1, v1, v3
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v1, v1, v2
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v1, v1, v3
 ; GFX10-DL-XNACK-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-DL-XNACK-NEXT:    s_endpgm
 ;
 ; GFX10-DL-NOXNACK-LABEL: idot8_acc16_vecMul:
 ; GFX10-DL-NOXNACK:       ; %bb.0: ; %entry
 ; GFX10-DL-NOXNACK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-DL-NOXNACK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

 ; GFX10-DL-NOXNACK-NEXT:    v_pk_lshlrev_b16 v0, 12, v0 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_mul_lo_u16 v1, v1, v8
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_ashrrev_i16 v9, 12, v9 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_lshl_or_b32 v8, v17, 16, v10
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_ashrrev_i16 v7, 12, v7 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_ashrrev_i16 v0, 12, v0 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v10, 16, v1
 ; GFX10-DL-NOXNACK-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v1, v1, v3
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v1, v1, v3
 ; GFX10-DL-NOXNACK-NEXT:    v_and_b32_e32 v3, v4, v5
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_lshlrev_b16 v5, 12, v8 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_and_b32_e32 v4, v4, v19
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_mul_lo_u16 v0, v9, v0
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v1, v1, v10
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v1, v1, v10
 ; GFX10-DL-NOXNACK-NEXT:    v_lshl_or_b32 v3, v6, 16, v3
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_ashrrev_i16 v5, 12, v5 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_lshl_or_b32 v4, v14, 16, v4
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v6, 16, v0
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v0, v1, v0
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v0, v1, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_lshlrev_b16 v1, 12, v3 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_lshlrev_b16 v3, 12, v4 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_mul_lo_u16 v4, v7, v5
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v7, v0, v6
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v7, v0, v6
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_ashrrev_i16 v1, 12, v1 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_ashrrev_i16 v3, 12, v3 op_sel_hi:[0,1]
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v5, 16, v4
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v0, v7, v4
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v0, v7, v4
 ; GFX10-DL-NOXNACK-NEXT:    v_pk_mul_lo_u16 v1, v1, v3
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v0, v0, v5
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v0, v0, v5
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v3, 16, v1
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v0, v0, v1
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v0, v0, v3
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v0, v0, v1
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v0, v0, v3
 ; GFX10-DL-NOXNACK-NEXT:    global_store_short v2, v0, s[0:1]
 ; GFX10-DL-NOXNACK-NEXT:    s_endpgm
 ; GFX10-DL-LABEL: idot8_acc16_vecMul:
 ; GFX10-DL:       ; %bb.0: ; %entry
 ; GFX10-DL-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
 ; GFX10-DL-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-DL-NEXT:    s_mov_b32 s12, SCRATCH_RSRC_DWORD0
 ; GFX10-DL-NEXT:    s_mov_b32 s13, SCRATCH_RSRC_DWORD1

 ; GFX10-DL-XNACK-NEXT:    global_load_ubyte v3, v19, s[0:1]
 ; GFX10-DL-XNACK-NEXT:    s_waitcnt vmcnt(2)
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v8, 12, v1
 ; GFX10-DL-XNACK-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v15, 12, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v9, 8, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v16, 8, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v6, 28, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v8
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v15, 12, v15
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v8, 12, v8
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v15, 12, v15
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v13, 28, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v10, 4, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v17, 4, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v9
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v16, 12, v16
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v8, 12, v8
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v15, 12, v15
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v9, 12, v9
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v16, 12, v16
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v8, 12, v8
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v15, 12, v15
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v0, 20, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v11, 20, v2
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v14, 24, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v6, 12, v6
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v13, 12, v13
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v10
-; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16_e64 v8, v8, v15
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v17, 12, v17
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v9, 12, v9
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v16, 12, v16
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v6, 12, v6
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v13, 12, v13
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v10, 12, v10
+; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16 v8, v8, v15
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v17, 12, v17
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v9, 12, v9
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v16, 12, v16
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v12, 16, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v7
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v0, 12, v0
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v14, 12, v14
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v11, 12, v11
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v6, 12, v6
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v13, 12, v13
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v1, 12, v1
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v2, 12, v2
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v10, 12, v10
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v15, 12, v17
-; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16_e64 v9, v9, v16
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v8, 8, v8
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v5
-; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16_e64 v6, v6, v13
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v12, 12, v12
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v7
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v0, 12, v0
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v14, 12, v14
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v11, 12, v11
-; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16_e64 v10, v10, v15
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v7, 12, v7
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v0, 12, v0
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v14, 12, v14
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v11, 12, v11
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v6, 12, v6
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v13, 12, v13
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v1, 12, v1
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v2, 12, v2
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v10, 12, v10
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v15, 12, v17
+; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16 v9, v9, v16
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v8, 8, v8
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v5, 12, v5
+; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16 v6, v6, v13
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v12, 12, v12
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v7, 12, v7
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v0, 12, v0
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v14, 12, v14
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v11, 12, v11
+; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16 v10, v10, v15
 ; GFX10-DL-XNACK-NEXT:    v_or_b32_sdwa v8, v9, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v1, 12, v1
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v2, 12, v2
-; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16_e64 v9, v0, v11
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v5, 12, v5
-; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16_e64 v23, 12, v12
-; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16_e64 v11, v7, v14
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v6, 8, v6
-; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16_e64 v1, v1, v2
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v10, 8, v10
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v1, 12, v1
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v2, 12, v2
+; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16 v9, v0, v11
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v5, 12, v5
+; GFX10-DL-XNACK-NEXT:    v_ashrrev_i16 v23, 12, v12
+; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16 v11, v7, v14
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v6, 8, v6
+; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16 v1, v1, v2
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v10, 8, v10
 ; GFX10-DL-XNACK-NEXT:    v_lshlrev_b32_e32 v0, 16, v8
-; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16_e64 v2, v5, v23
-; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16_e64 v9, 8, v9
+; GFX10-DL-XNACK-NEXT:    v_mul_lo_u16 v2, v5, v23
+; GFX10-DL-XNACK-NEXT:    v_lshlrev_b16 v9, 8, v9
 ; GFX10-DL-XNACK-NEXT:    v_or_b32_sdwa v6, v11, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-DL-XNACK-NEXT:    v_or_b32_sdwa v1, v1, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-DL-XNACK-NEXT:    v_or_b32_sdwa v11, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX10-DL-XNACK-NEXT:    v_or_b32_sdwa v2, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-DL-XNACK-NEXT:    v_lshlrev_b32_e32 v9, 16, v6
 ; GFX10-DL-XNACK-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v3, v1, v3
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v3, v1, v3
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v10, 8, v11
 ; GFX10-DL-XNACK-NEXT:    v_or_b32_sdwa v1, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v9, v3, v10
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v9, v3, v10
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b64 v[2:3], 24, v[0:1]
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v0, v9, v8
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v0, v0, v2
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v0, v9, v8
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v0, v0, v2
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v0, v5, v23, v0
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v0, v0, v1
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v0, v0, v1
 ; GFX10-DL-XNACK-NEXT:    v_lshrrev_b32_e32 v1, 8, v6
 ; GFX10-DL-XNACK-NEXT:    v_mad_u16 v0, v7, v14, v0
-; GFX10-DL-XNACK-NEXT:    v_add_nc_u16_e64 v0, v0, v1
+; GFX10-DL-XNACK-NEXT:    v_add_nc_u16 v0, v0, v1
 ; GFX10-DL-XNACK-NEXT:    global_store_byte v19, v0, s[0:1]
 ; GFX10-DL-XNACK-NEXT:    s_endpgm
 ;
 ; GFX10-DL-NOXNACK-LABEL: idot8_acc8_vecMul:
 ; GFX10-DL-NOXNACK:       ; %bb.0: ; %entry
 ; GFX10-DL-NOXNACK-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24
 ; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-DL-NOXNACK-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

 ; GFX10-DL-NOXNACK-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v15, 12, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v9, 8, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v11, 20, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v12, 16, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v13, 28, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v14, 24, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v17, 4, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v8, 12, v8
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v15, 12, v15
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v8, 12, v8
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v15, 12, v15
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v16, 8, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v0, 12, v0
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v0, 12, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v6, 28, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v10, 4, v1
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v9, 12, v9
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v8, 12, v8
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v18, 12, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v0, 12, v16
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v15, 12, v15
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v9, 12, v9
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v8, 12, v8
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v18, 12, v0
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v0, 12, v16
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v15, 12, v15
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v3, 20, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v7, 24, v1
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v6, 12, v6
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v13, 12, v13
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v10, 12, v10
-; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16_e64 v8, v8, v15
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v17, 12, v17
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v9, 12, v9
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v0, 12, v0
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v13, 12, v13
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v10, 12, v10
+; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16 v8, v8, v15
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v17, 12, v17
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v9, 12, v9
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v0, 12, v0
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v7, 12, v7
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v3, 12, v3
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v14, 12, v14
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v11, 12, v11
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v6, 12, v6
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v13, 12, v13
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v1, 12, v1
-; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16_e64 v23, v9, v0
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v8, 8, v8
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v10, 12, v10
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v15, 12, v17
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v5, 12, v5
-; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16_e64 v6, v6, v13
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v12, 12, v12
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v9, 12, v11
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v3, 12, v3
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v7, 12, v7
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v14, 12, v14
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v1, 12, v1
-; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16_e64 v10, v10, v15
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v7, 12, v7
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v3, 12, v3
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v14, 12, v14
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v11, 12, v11
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v6, 12, v6
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v13, 12, v13
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v1, 12, v1
+; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16 v23, v9, v0
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v8, 8, v8
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v10, 12, v10
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v15, 12, v17
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v5, 12, v5
+; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16 v6, v6, v13
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v12, 12, v12
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v9, 12, v11
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v3, 12, v3
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v7, 12, v7
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v14, 12, v14
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v1, 12, v1
+; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16 v10, v10, v15
 ; GFX10-DL-NOXNACK-NEXT:    v_or_b32_sdwa v8, v23, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
-; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16_e64 v3, v3, v9
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v5, 12, v5
-; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16_e64 v11, 12, v12
-; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16_e64 v9, v7, v14
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v6, 8, v6
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v10, 8, v10
-; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16_e64 v1, v1, v18
+; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16 v3, v3, v9
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v5, 12, v5
+; GFX10-DL-NOXNACK-NEXT:    v_ashrrev_i16 v11, 12, v12
+; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16 v9, v7, v14
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v6, 8, v6
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v10, 8, v10
+; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16 v1, v1, v18
 ; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b32_e32 v0, 16, v8
-; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16_e64 v12, v5, v11
-; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16_e64 v3, 8, v3
+; GFX10-DL-NOXNACK-NEXT:    v_mul_lo_u16 v12, v5, v11
+; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b16 v3, 8, v3
 ; GFX10-DL-NOXNACK-NEXT:    v_or_b32_sdwa v6, v9, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-DL-NOXNACK-NEXT:    v_or_b32_sdwa v1, v1, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-DL-NOXNACK-NEXT:    v_or_b32_sdwa v9, v10, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX10-DL-NOXNACK-NEXT:    v_or_b32_sdwa v3, v12, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 ; GFX10-DL-NOXNACK-NEXT:    v_lshlrev_b32_e32 v10, 16, v6
 ; GFX10-DL-NOXNACK-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v2, v1, v2
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v2, v1, v2
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v9, 8, v9
 ; GFX10-DL-NOXNACK-NEXT:    v_or_b32_sdwa v1, v3, v10 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v9, v2, v9
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v9, v2, v9
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b64 v[2:3], 24, v[0:1]
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v0, v9, v8
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v0, v0, v2
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v0, v9, v8
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v0, v0, v2
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v5, v11, v0
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v0, v0, v1
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v0, v0, v1
 ; GFX10-DL-NOXNACK-NEXT:    v_lshrrev_b32_e32 v1, 8, v6
 ; GFX10-DL-NOXNACK-NEXT:    v_mad_u16 v0, v7, v14, v0
-; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16_e64 v0, v0, v1
+; GFX10-DL-NOXNACK-NEXT:    v_add_nc_u16 v0, v0, v1
 ; GFX10-DL-NOXNACK-NEXT:    global_store_byte v19, v0, s[0:1]
 ; GFX10-DL-NOXNACK-NEXT:    s_endpgm
 ; GFX10-DL-LABEL: idot8_acc8_vecMul:
 ; GFX10-DL:       ; %bb.0: ; %entry
 ; GFX10-DL-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0x34
 ; GFX10-DL-NEXT:    v_mov_b32_e32 v0, 0
 ; GFX10-DL-NEXT:    s_mov_b32 s20, SCRATCH_RSRC_DWORD0
 ; GFX10-DL-NEXT:    s_mov_b32 s21, SCRATCH_RSRC_DWORD1

llvm/test/CodeGen/AMDGPU/idot8u.ll

 ; GFX10-DL-NEXT:    v_lshl_or_b32 v10, v10, 16, v13
 ; GFX10-DL-NEXT:    v_pk_mul_lo_u16 v6, v7, v6
 ; GFX10-DL-NEXT:    v_bfe_u32 v7, v2, 16, 4
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v9, v9, 16, v12
 ; GFX10-DL-NEXT:    v_bfe_u32 v5, v1, 24, 4
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v23, 28, v1
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v12, 16, v6
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v6, v3
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v6, v3
 ; GFX10-DL-NEXT:    v_pk_mul_lo_u16 v9, v9, v10
 ; GFX10-DL-NEXT:    v_bfe_u32 v1, v1, 20, 4
 ; GFX10-DL-NEXT:    v_and_b32_e32 v11, v4, v11
 ; GFX10-DL-NEXT:    v_bfe_u32 v6, v2, 20, 4
 ; GFX10-DL-NEXT:    v_and_b32_e32 v7, v4, v7
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v3, v12
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v3, v12
 ; GFX10-DL-NEXT:    v_bfe_u32 v10, v2, 24, 4
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v1, v1, 16, v11
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v2, 28, v2
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v6, v6, 16, v7
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v7, 16, v9
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v14, v3, v9
+; GFX10-DL-NEXT:    v_add_nc_u16 v14, v3, v9
 ; GFX10-DL-NEXT:    v_and_b32_e32 v9, v4, v10
 ; GFX10-DL-NEXT:    v_and_b32_e32 v4, v4, v5
 ; GFX10-DL-NEXT:    v_pk_mul_lo_u16 v1, v1, v6
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v14, v7
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v14, v7
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v2, v2, 16, v9
 ; GFX10-DL-NEXT:    v_lshl_or_b32 v4, v23, 16, v4
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v5, 16, v1
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v3, v1
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v3, v1
 ; GFX10-DL-NEXT:    v_pk_mul_lo_u16 v2, v4, v2
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v3, v5
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v3, v5
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v3, 16, v2
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v1, v2
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v1, v3
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v1, v2
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v1, v3
 ; GFX10-DL-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-DL-NEXT:    s_endpgm
                                               <8 x i4> addrspace(1)* %src2,
                                               i16 addrspace(1)* nocapture %dst) {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gep1 = getelementptr <8 x i4>, <8 x i4> addrspace(1)* %src1, i32 %idx
   %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %gep1

 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(2)
 ; GFX10-DL-NEXT:    v_bfe_u32 v9, v1, 12, 4
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(1)
 ; GFX10-DL-NEXT:    v_bfe_u32 v10, v2, 12, 4
 ; GFX10-DL-NEXT:    v_bfe_u32 v8, v1, 8, 4
 ; GFX10-DL-NEXT:    v_bfe_u32 v13, v2, 8, 4
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v7, 28, v1
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v14, 28, v2
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v9, v9, v10
+; GFX10-DL-NEXT:    v_mul_lo_u16 v9, v9, v10
 ; GFX10-DL-NEXT:    v_bfe_u32 v5, v1, 16, 4
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v8, v8, v13
+; GFX10-DL-NEXT:    v_mul_lo_u16 v8, v8, v13
 ; GFX10-DL-NEXT:    v_bfe_u32 v0, v1, 20, 4
 ; GFX10-DL-NEXT:    v_bfe_u32 v6, v1, 24, 4
 ; GFX10-DL-NEXT:    v_and_b32_e32 v11, 15, v1
-; GFX10-DL-NEXT:    v_lshlrev_b16_e64 v9, 8, v9
+; GFX10-DL-NEXT:    v_lshlrev_b16 v9, 8, v9
 ; GFX10-DL-NEXT:    v_bfe_u32 v1, v1, 4, 4
 ; GFX10-DL-NEXT:    v_bfe_u32 v15, v2, 4, 4
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v7, v7, v14
+; GFX10-DL-NEXT:    v_mul_lo_u16 v7, v7, v14
 ; GFX10-DL-NEXT:    v_bfe_u32 v10, v2, 20, 4
 ; GFX10-DL-NEXT:    v_bfe_u32 v13, v2, 24, 4
 ; GFX10-DL-NEXT:    v_bfe_u32 v23, v2, 16, 4
 ; GFX10-DL-NEXT:    v_and_b32_e32 v2, 15, v2
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v1, v1, v15
+; GFX10-DL-NEXT:    v_mul_lo_u16 v1, v1, v15
 ; GFX10-DL-NEXT:    v_or_b32_e32 v8, v8, v9
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v9, v0, v10
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v10, v6, v13
-; GFX10-DL-NEXT:    v_lshlrev_b16_e64 v7, 8, v7
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v2, v11, v2
-; GFX10-DL-NEXT:    v_lshlrev_b16_e64 v1, 8, v1
+; GFX10-DL-NEXT:    v_mul_lo_u16 v9, v0, v10
+; GFX10-DL-NEXT:    v_mul_lo_u16 v10, v6, v13
+; GFX10-DL-NEXT:    v_lshlrev_b16 v7, 8, v7
+; GFX10-DL-NEXT:    v_mul_lo_u16 v2, v11, v2
+; GFX10-DL-NEXT:    v_lshlrev_b16 v1, 8, v1
 ; GFX10-DL-NEXT:    v_lshlrev_b32_e32 v0, 16, v8
-; GFX10-DL-NEXT:    v_mul_lo_u16_e64 v11, v5, v23
+; GFX10-DL-NEXT:    v_mul_lo_u16 v11, v5, v23
 ; GFX10-DL-NEXT:    v_or_b32_e32 v7, v10, v7
-; GFX10-DL-NEXT:    v_lshlrev_b16_e64 v9, 8, v9
+; GFX10-DL-NEXT:    v_lshlrev_b16 v9, 8, v9
 ; GFX10-DL-NEXT:    v_or_b32_sdwa v10, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
 ; GFX10-DL-NEXT:    v_or_b32_e32 v1, v2, v1
 ; GFX10-DL-NEXT:    v_or_b32_e32 v2, v11, v9
 ; GFX10-DL-NEXT:    v_lshlrev_b32_e32 v9, 16, v7
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v10, 8, v10
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v1, v3
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v1, v3
 ; GFX10-DL-NEXT:    v_or_b32_sdwa v1, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v9, v3, v10
+; GFX10-DL-NEXT:    v_add_nc_u16 v9, v3, v10
 ; GFX10-DL-NEXT:    v_lshrrev_b64 v[2:3], 24, v[0:1]
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v1, 8, v1
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v0, v9, v8
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v0, v0, v2
+; GFX10-DL-NEXT:    v_add_nc_u16 v0, v9, v8
+; GFX10-DL-NEXT:    v_add_nc_u16 v0, v0, v2
 ; GFX10-DL-NEXT:    v_mad_u16 v0, v5, v23, v0
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v0, v0, v1
+; GFX10-DL-NEXT:    v_add_nc_u16 v0, v0, v1
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v1, 8, v7
 ; GFX10-DL-NEXT:    v_mad_u16 v0, v6, v13, v0
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v0, v0, v1
+; GFX10-DL-NEXT:    v_add_nc_u16 v0, v0, v1
 ; GFX10-DL-NEXT:    global_store_byte v19, v0, s[0:1]
 ; GFX10-DL-NEXT:    s_endpgm
                                              <8 x i4> addrspace(1)* %src2,
                                              i8 addrspace(1)* nocapture %dst) {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gep1 = getelementptr <8 x i4>, <8 x i4> addrspace(1)* %src1, i32 %idx
   %vec1 = load <8 x i4>, <8 x i4> addrspace(1)* %gep1

 ; GFX10-DL-NEXT:    v_bfe_u32 v7, v2, 4, 4
 ; GFX10-DL-NEXT:    v_bfe_u32 v8, v2, 8, 4
 ; GFX10-DL-NEXT:    v_bfe_u32 v11, v1, 24, 4
 ; GFX10-DL-NEXT:    v_mul_u32_u24_e32 v4, v4, v5
 ; GFX10-DL-NEXT:    v_bfe_u32 v5, v1, 8, 4
 ; GFX10-DL-NEXT:    v_mul_u32_u24_e32 v6, v6, v7
 ; GFX10-DL-NEXT:    v_bfe_u32 v7, v2, 12, 4
 ; GFX10-DL-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v4, v3
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v4, v3
 ; GFX10-DL-NEXT:    v_bfe_u32 v4, v1, 12, 4
 ; GFX10-DL-NEXT:    v_mul_u32_u24_e32 v5, v5, v8
 ; GFX10-DL-NEXT:    v_bfe_u32 v8, v2, 16, 4
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v3, v6
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v3, v6
 ; GFX10-DL-NEXT:    v_bfe_u32 v6, v1, 16, 4
 ; GFX10-DL-NEXT:    v_mul_u32_u24_e32 v4, v4, v7
 ; GFX10-DL-NEXT:    v_bfe_u32 v7, v2, 20, 4
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v3, v5
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v3, v5
 ; GFX10-DL-NEXT:    v_bfe_u32 v5, v1, 20, 4
 ; GFX10-DL-NEXT:    v_mul_u32_u24_e32 v6, v6, v8
 ; GFX10-DL-NEXT:    v_bfe_u32 v8, v2, 24, 4
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v1, 28, v1
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v3, v4
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v3, v4
 ; GFX10-DL-NEXT:    v_mul_u32_u24_e32 v5, v5, v7
 ; GFX10-DL-NEXT:    v_lshrrev_b32_e32 v2, 28, v2
 ; GFX10-DL-NEXT:    v_mul_u32_u24_e32 v4, v11, v8
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v3, v6
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v3, v6
 ; GFX10-DL-NEXT:    v_mul_u32_u24_e32 v1, v1, v2
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v3, v3, v5
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v2, v3, v4
-; GFX10-DL-NEXT:    v_add_nc_u16_e64 v1, v2, v1
+; GFX10-DL-NEXT:    v_add_nc_u16 v3, v3, v5
+; GFX10-DL-NEXT:    v_add_nc_u16 v2, v3, v4
+; GFX10-DL-NEXT:    v_add_nc_u16 v1, v2, v1
 ; GFX10-DL-NEXT:    v_and_b32_e32 v1, 15, v1
 ; GFX10-DL-NEXT:    global_store_byte v0, v1, s[2:3]
 ; GFX10-DL-NEXT:    s_endpgm
                                              <8 x i4> addrspace(1)* %src2,
                                              i4 addrspace(1)* nocapture %dst) {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gep1 = getelementptr <8 x i4>, <8 x i4> addrspace(1)* %src1, i32 %idx

llvm/test/CodeGen/AMDGPU/imm16.ll

 ; GFX10-NEXT:    s_mov_b32 s11, s7 ; encoding: [0x07,0x03,0x8b,0xbe]
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf]
 ; GFX10-NEXT:    s_mov_b32 s8, s2 ; encoding: [0x02,0x03,0x88,0xbe]
 ; GFX10-NEXT:    s_mov_b32 s9, s3 ; encoding: [0x03,0x03,0x89,0xbe]
 ; GFX10-NEXT:    s_mov_b32 s4, s0 ; encoding: [0x00,0x03,0x84,0xbe]
 ; GFX10-NEXT:    buffer_load_ushort v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x00,0x02,0x80]
 ; GFX10-NEXT:    s_mov_b32 s5, s1 ; encoding: [0x01,0x03,0x85,0xbe]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, v0, -1 ; encoding: [0x00,0x00,0x03,0xd7,0x00,0x83,0x01,0x00]
+; GFX10-NEXT:    v_add_nc_u16 v0, v0, -1 ; encoding: [0x00,0x00,0x03,0xd7,0x00,0x83,0x01,0x00]
 ; GFX10-NEXT:    buffer_store_short v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x01,0x80]
 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
 ;
 ; VI-LABEL: add_inline_imm_neg_1_f16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0 ; encoding: [0x02,0x01,0x0a,0xc0,0x00,0x00,0x00,0x00]
 ; VI-NEXT:    s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11]
 ; VI-NEXT:    s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe]

 ; GFX10-NEXT:    s_mov_b32 s11, s7 ; encoding: [0x07,0x03,0x8b,0xbe]
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf]
 ; GFX10-NEXT:    s_mov_b32 s8, s2 ; encoding: [0x02,0x03,0x88,0xbe]
 ; GFX10-NEXT:    s_mov_b32 s9, s3 ; encoding: [0x03,0x03,0x89,0xbe]
 ; GFX10-NEXT:    s_mov_b32 s4, s0 ; encoding: [0x00,0x03,0x84,0xbe]
 ; GFX10-NEXT:    buffer_load_ushort v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x00,0x02,0x80]
 ; GFX10-NEXT:    s_mov_b32 s5, s1 ; encoding: [0x01,0x03,0x85,0xbe]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, v0, -2 ; encoding: [0x00,0x00,0x03,0xd7,0x00,0x85,0x01,0x00]
+; GFX10-NEXT:    v_add_nc_u16 v0, v0, -2 ; encoding: [0x00,0x00,0x03,0xd7,0x00,0x85,0x01,0x00]
 ; GFX10-NEXT:    buffer_store_short v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x01,0x80]
 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
 ;
 ; VI-LABEL: add_inline_imm_neg_2_f16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0 ; encoding: [0x02,0x01,0x0a,0xc0,0x00,0x00,0x00,0x00]
 ; VI-NEXT:    s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11]
 ; VI-NEXT:    s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe]

 ; GFX10-NEXT:    s_mov_b32 s11, s7 ; encoding: [0x07,0x03,0x8b,0xbe]
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf]
 ; GFX10-NEXT:    s_mov_b32 s8, s2 ; encoding: [0x02,0x03,0x88,0xbe]
 ; GFX10-NEXT:    s_mov_b32 s9, s3 ; encoding: [0x03,0x03,0x89,0xbe]
 ; GFX10-NEXT:    s_mov_b32 s4, s0 ; encoding: [0x00,0x03,0x84,0xbe]
 ; GFX10-NEXT:    buffer_load_ushort v0, off, s[8:11], 0 ; encoding: [0x00,0x00,0x28,0xe0,0x00,0x00,0x02,0x80]
 ; GFX10-NEXT:    s_mov_b32 s5, s1 ; encoding: [0x01,0x03,0x85,0xbe]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
-; GFX10-NEXT:    v_add_nc_u16_e64 v0, v0, -16 ; encoding: [0x00,0x00,0x03,0xd7,0x00,0xa1,0x01,0x00]
+; GFX10-NEXT:    v_add_nc_u16 v0, v0, -16 ; encoding: [0x00,0x00,0x03,0xd7,0x00,0xa1,0x01,0x00]
 ; GFX10-NEXT:    buffer_store_short v0, off, s[4:7], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x01,0x80]
 ; GFX10-NEXT:    s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
 ;
 ; VI-LABEL: add_inline_imm_neg_16_f16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_load_dwordx4 s[4:7], s[4:5], 0x0 ; encoding: [0x02,0x01,0x0a,0xc0,0x00,0x00,0x00,0x00]
 ; VI-NEXT:    s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11]
 ; VI-NEXT:    s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe]

 
 ; This needs to be emitted as a literal constant since the 16-bit
 ; float values do not work for 16-bit integer operations.
 define void @mul_inline_imm_0.5_i16(i16 addrspace(1)* %out, i16 %x) {
 ; GFX10-LABEL: mul_inline_imm_0.5_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
-; GFX10-NEXT:    v_mul_lo_u16_e64 v2, 0x3800, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+; GFX10-NEXT:    v_mul_lo_u16 v2, 0x3800, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
 ;
 ; VI-LABEL: mul_inline_imm_0.5_i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; VI-NEXT:    v_mul_lo_u16_e32 v2, 0x3800, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0x38,0x00,0x00]
; SI-NEXT:    s_setpc_b64 s[30:31]
   ret void
 }
 
 define void @mul_inline_imm_neg_0.5_i16(i16 addrspace(1)* %out, i16 %x) {
 ; GFX10-LABEL: mul_inline_imm_neg_0.5_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
-; GFX10-NEXT:    v_mul_lo_u16_e64 v2, 0xb800, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xb8,0xff,0xff]
+; GFX10-NEXT:    v_mul_lo_u16 v2, 0xb800, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xb8,0xff,0xff]
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
 ;
 ; VI-LABEL: mul_inline_imm_neg_0.5_i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; VI-NEXT:    v_mul_lo_u16_e32 v2, 0xb800, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0xb8,0xff,0xff]
; SI-NEXT:    s_setpc_b64 s[30:31]
   ret void
 }
 
 define void @mul_inline_imm_1.0_i16(i16 addrspace(1)* %out, i16 %x) {
 ; GFX10-LABEL: mul_inline_imm_1.0_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
-; GFX10-NEXT:    v_mul_lo_u16_e64 v2, 0x3c00, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x3c,0x00,0x00]
+; GFX10-NEXT:    v_mul_lo_u16 v2, 0x3c00, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x3c,0x00,0x00]
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
 ;
 ; VI-LABEL: mul_inline_imm_1.0_i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; VI-NEXT:    v_mul_lo_u16_e32 v2, 0x3c00, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0x3c,0x00,0x00]
; SI-NEXT:    s_setpc_b64 s[30:31]
   ret void
 }
 
 define void @mul_inline_imm_neg_1.0_i16(i16 addrspace(1)* %out, i16 %x) {
 ; GFX10-LABEL: mul_inline_imm_neg_1.0_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
-; GFX10-NEXT:    v_mul_lo_u16_e64 v2, 0xbc00, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xbc,0xff,0xff]
+; GFX10-NEXT:    v_mul_lo_u16 v2, 0xbc00, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xbc,0xff,0xff]
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
 ;
 ; VI-LABEL: mul_inline_imm_neg_1.0_i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; VI-NEXT:    v_mul_lo_u16_e32 v2, 0xbc00, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0xbc,0xff,0xff]
; SI-NEXT:    s_setpc_b64 s[30:31]
   ret void
 }
 
 define void @shl_inline_imm_2.0_i16(i16 addrspace(1)* %out, i16 %x) {
 ; GFX10-LABEL: shl_inline_imm_2.0_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
-; GFX10-NEXT:    v_lshlrev_b16_e64 v2, v2, 0x4000 ; encoding: [0x02,0x00,0x14,0xd7,0x02,0xff,0x01,0x00,0x00,0x40,0x00,0x00]
+; GFX10-NEXT:    v_lshlrev_b16 v2, v2, 0x4000 ; encoding: [0x02,0x00,0x14,0xd7,0x02,0xff,0x01,0x00,0x00,0x40,0x00,0x00]
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
 ;
 ; VI-LABEL: shl_inline_imm_2.0_i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; VI-NEXT:    s_movk_i32 s4, 0x4000 ; encoding: [0x00,0x40,0x04,0xb0]
; SI-NEXT:    s_setpc_b64 s[30:31]
   ret void
 }
 
 define void @shl_inline_imm_neg_2.0_i16(i16 addrspace(1)* %out, i16 %x) {
 ; GFX10-LABEL: shl_inline_imm_neg_2.0_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
-; GFX10-NEXT:    v_lshlrev_b16_e64 v2, v2, 0xc000 ; encoding: [0x02,0x00,0x14,0xd7,0x02,0xff,0x01,0x00,0x00,0xc0,0xff,0xff]
+; GFX10-NEXT:    v_lshlrev_b16 v2, v2, 0xc000 ; encoding: [0x02,0x00,0x14,0xd7,0x02,0xff,0x01,0x00,0x00,0xc0,0xff,0xff]
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
 ;
 ; VI-LABEL: shl_inline_imm_neg_2.0_i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; VI-NEXT:    s_movk_i32 s4, 0xc000 ; encoding: [0x00,0xc0,0x04,0xb0]
; SI-NEXT:    s_setpc_b64 s[30:31]
   ret void
 }
 
 define void @mul_inline_imm_4.0_i16(i16 addrspace(1)* %out, i16 %x) {
 ; GFX10-LABEL: mul_inline_imm_4.0_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
-; GFX10-NEXT:    v_mul_lo_u16_e64 v2, 0x4400, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x44,0x00,0x00]
+; GFX10-NEXT:    v_mul_lo_u16 v2, 0x4400, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x44,0x00,0x00]
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
 ;
 ; VI-LABEL: mul_inline_imm_4.0_i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; VI-NEXT:    v_mul_lo_u16_e32 v2, 0x4400, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0x44,0x00,0x00]
; SI-NEXT:    s_setpc_b64 s[30:31]
   ret void
 }
 
 define void @mul_inline_imm_neg_4.0_i16(i16 addrspace(1)* %out, i16 %x) {
 ; GFX10-LABEL: mul_inline_imm_neg_4.0_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
-; GFX10-NEXT:    v_mul_lo_u16_e64 v2, 0xc400, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0xff,0xff]
+; GFX10-NEXT:    v_mul_lo_u16 v2, 0xc400, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0xff,0xff]
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
 ;
 ; VI-LABEL: mul_inline_imm_neg_4.0_i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; VI-NEXT:    v_mul_lo_u16_e32 v2, 0xc400, v2 ; encoding: [0xff,0x04,0x04,0x52,0x00,0xc4,0xff,0xff]
; SI-NEXT:    s_setpc_b64 s[30:31]
   ret void
 }
 
 define void @mul_inline_imm_inv2pi_i16(i16 addrspace(1)* %out, i16 %x) {
 ; GFX10-LABEL: mul_inline_imm_inv2pi_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
-; GFX10-NEXT:    v_mul_lo_u16_e64 v2, 0x3118, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x18,0x31,0x00,0x00]
+; GFX10-NEXT:    v_mul_lo_u16 v2, 0x3118, v2 ; encoding: [0x02,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x18,0x31,0x00,0x00]
 ; GFX10-NEXT:    global_store_short v[0:1], v2, off ; encoding: [0x00,0x80,0x68,0xdc,0x00,0x02,0x7d,0x00]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
 ; GFX10-NEXT:    s_setpc_b64 s[30:31] ; encoding: [0x1e,0x20,0x80,0xbe]
 ;
 ; VI-LABEL: mul_inline_imm_inv2pi_i16:
 ; VI:       ; %bb.0:
 ; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
 ; VI-NEXT:    v_mul_lo_u16_e32 v2, 0x3118, v2 ; encoding: [0xff,0x04,0x04,0x52,0x18,0x31,0x00,0x00]

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmul.legacy.ll

 ; RUN: llc -march=amdgcn -mcpu=tahiti  -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX6 %s
 ; RUN: llc -march=amdgcn -mcpu=tonga   -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX8 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx900  -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX9 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx90a  -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX9 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MADMACF32,GFX101 %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,NOMADMACF32,GFX103 %s
 
 ; GCN-LABEL: {{^}}test_mul_legacy_f32:
-; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
+; GCN: v_mul_legacy_f32{{[_e3264]*}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
 define amdgpu_kernel void @test_mul_legacy_f32(float addrspace(1)* %out, float %a, float %b) #0 {
   %result = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_mul_legacy_undef0_f32:
-; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
+; GCN: v_mul_legacy_f32{{[_e3264]*}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
 define amdgpu_kernel void @test_mul_legacy_undef0_f32(float addrspace(1)* %out, float %a) #0 {
   %result = call float @llvm.amdgcn.fmul.legacy(float undef, float %a)
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_mul_legacy_undef1_f32:
-; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
+; GCN: v_mul_legacy_f32{{[_e3264]*}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
 define amdgpu_kernel void @test_mul_legacy_undef1_f32(float addrspace(1)* %out, float %a) #0 {
   %result = call float @llvm.amdgcn.fmul.legacy(float %a, float undef)
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_mul_legacy_fabs_f32:
-; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, |s{{[0-9]+}}|, |{{[sv][0-9]+}}|
+; GCN: v_mul_legacy_f32{{[_e3264]*}} v{{[0-9]+}}, |s{{[0-9]+}}|, |{{[sv][0-9]+}}|
 define amdgpu_kernel void @test_mul_legacy_fabs_f32(float addrspace(1)* %out, float %a, float %b) #0 {
   %a.fabs = call float @llvm.fabs.f32(float %a)
   %b.fabs = call float @llvm.fabs.f32(float %b)
   %result = call float @llvm.amdgcn.fmul.legacy(float %a.fabs, float %b.fabs)
   store float %result, float addrspace(1)* %out, align 4
   ret void
 }
 
 ; Don't form mad/mac instructions because they don't support denormals.
 ; GCN-LABEL: {{^}}test_add_mul_legacy_f32:
-; GCN: v_mul_legacy_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
+; GCN: v_mul_legacy_f32{{[_e3264]*}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
 ; GCN: v_add_f32_e{{(32|64)}} v{{[0-9]+}}, s{{[0-9]+}}, {{[sv][0-9]+}}
 define amdgpu_kernel void @test_add_mul_legacy_f32(float addrspace(1)* %out, float %a, float %b, float %c) #0 {
   %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
   %add = fadd float %mul, %c
   store float %add, float addrspace(1)* %out, align 4
   ret void
 }
 

llvm/test/CodeGen/AMDGPU/llvm.mulo.ll

 ; GFX10-NEXT:    v_mul_lo_u32 v5, v0, v3
 ; GFX10-NEXT:    v_mul_hi_u32 v6, v0, v2
 ; GFX10-NEXT:    v_mul_hi_u32 v4, v0, v3
 ; GFX10-NEXT:    v_mul_lo_u32 v8, v1, v2
 ; GFX10-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX10-NEXT:    v_mul_hi_u32 v9, v1, v3
 ; GFX10-NEXT:    v_mul_lo_u32 v1, v1, v3
 ; GFX10-NEXT:    v_mul_lo_u32 v0, v0, v2
-; GFX10-NEXT:    v_add_co_u32_e64 v10, vcc_lo, v6, v5
+; GFX10-NEXT:    v_add_co_u32 v10, vcc_lo, v6, v5
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v3, vcc_lo, v10, v8
+; GFX10-NEXT:    v_add_co_u32 v3, vcc_lo, v10, v8
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v4, v7, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, 0, v9, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v3, vcc_lo, v3, v1
+; GFX10-NEXT:    v_add_co_u32 v3, vcc_lo, v3, v1
 ; GFX10-NEXT:    v_add3_u32 v1, v6, v5, v8
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, 0, v4, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u64_e32 vcc_lo, 0, v[3:4]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
 bb:
   %umulo = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %x, i64 %y)
   ret { i64, i1 } %umulo

 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    v_mul_lo_u32 v15, v0, v3
 ; GFX10-NEXT:    v_mul_hi_u32 v5, v0, v2
 ; GFX10-NEXT:    v_mul_hi_u32 v6, v0, v3
 ; GFX10-NEXT:    v_mul_lo_u32 v8, v1, v2
 ; GFX10-NEXT:    v_mul_hi_u32 v7, v1, v2
 ; GFX10-NEXT:    v_mul_hi_i32 v9, v1, v3
 ; GFX10-NEXT:    v_mul_lo_u32 v11, v1, v3
-; GFX10-NEXT:    v_add_co_u32_e64 v10, vcc_lo, v5, v15
+; GFX10-NEXT:    v_add_co_u32 v10, vcc_lo, v5, v15
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, 0, v6, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v10, vcc_lo, v10, v8
+; GFX10-NEXT:    v_add_co_u32 v10, vcc_lo, v10, v8
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v6, vcc_lo, v6, v7, vcc_lo
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v9, vcc_lo
-; GFX10-NEXT:    v_add_co_u32_e64 v11, vcc_lo, v6, v11
+; GFX10-NEXT:    v_add_co_u32 v11, vcc_lo, v6, v11
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v7, vcc_lo
-; GFX10-NEXT:    v_sub_co_u32_e64 v9, vcc_lo, v11, v2
+; GFX10-NEXT:    v_sub_co_u32 v9, vcc_lo, v11, v2
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v10, vcc_lo, 0, v7, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0, v1
 ; GFX10-NEXT:    v_add3_u32 v1, v5, v15, v8
 ; GFX10-NEXT:    v_cndmask_b32_e32 v6, v11, v9, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v10, vcc_lo
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v4, 31, v1
-; GFX10-NEXT:    v_sub_co_u32_e64 v8, vcc_lo, v6, v0
+; GFX10-NEXT:    v_sub_co_u32 v8, vcc_lo, v6, v0
 ; GFX10-NEXT:    v_mul_lo_u32 v0, v0, v2
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v9, vcc_lo, 0, v7, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i32_e32 vcc_lo, 0, v3
 ; GFX10-NEXT:    v_mov_b32_e32 v5, v4
 ; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v9, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v8, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u64_e32 vcc_lo, v[6:7], v[4:5]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc_lo

 ; GFX10-NEXT:    v_mov_b32_e32 v0, s9
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s10
 ; GFX10-NEXT:    s_add_i32 s1, s8, s7
 ; GFX10-NEXT:    s_add_i32 s1, s1, s5
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, s4, v0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, s6, v1, vcc_lo
 ; GFX10-NEXT:    s_ashr_i32 s4, s1, 31
 ; GFX10-NEXT:    s_mov_b32 s5, s4
-; GFX10-NEXT:    v_sub_co_u32_e64 v2, vcc_lo, v0, s0
+; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, s0
 ; GFX10-NEXT:    s_mul_i32 s0, s0, s2
 ; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i32_e64 vcc_lo, s3, 0
 ; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
 ; GFX10-NEXT:    v_cmp_ne_u64_e32 vcc_lo, s[4:5], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, s1, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, s0, 0, vcc_lo

llvm/test/CodeGen/AMDGPU/llvm.pow-gfx9.ll

 ; RUN: llc < %s -march=amdgcn -mcpu=gfx908 | FileCheck %s --check-prefixes=GCN,GFX908
 ; RUN: llc < %s -march=amdgcn -mcpu=gfx90a | FileCheck %s --check-prefixes=GCN,GFX90A
 
 ; GCN-LABEL: {{^}}mul_legacy
 ; GFX908: v_mul_legacy_f32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
-; GFX90A: v_mul_legacy_f32_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
+; GFX90A: v_mul_legacy_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}{{$}}
 define amdgpu_kernel void @mul_legacy(
     float addrspace(1)* %r,
     float addrspace(1)* %a,
     float addrspace(1)* %b) {
 entry:
   %a.val = load volatile float, float addrspace(1)* %a
   %b.val = load volatile float, float addrspace(1)* %b
   %r.val = call float @llvm.pow.f32(float %a.val, float %b.val)
   store float %r.val, float addrspace(1)* %r
   ret void
 }
 
 declare float @llvm.pow.f32(float ,float ) readonly

llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-nontemporal.ll

 ; GFX7-NEXT:    flat_store_dword v[0:1], v2
 ; GFX7-NEXT:    s_endpgm
 ;
 ; GFX10-WGP-LABEL: flat_nontemporal_load_1:
 ; GFX10-WGP:       ; %bb.0: ; %entry
 ; GFX10-WGP-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-WGP-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-WGP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-WGP-NEXT:    v_add_co_u32_e64 v0, s0, s0, v0
+; GFX10-WGP-NEXT:    v_add_co_u32 v0, s0, s0, v0
 ; GFX10-WGP-NEXT:    v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
 ; GFX10-WGP-NEXT:    flat_load_dword v2, v[0:1] slc
 ; GFX10-WGP-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX10-WGP-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX10-WGP-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-WGP-NEXT:    flat_store_dword v[0:1], v2
 ; GFX10-WGP-NEXT:    s_endpgm
 ;
 ; GFX10-CU-LABEL: flat_nontemporal_load_1:
 ; GFX10-CU:       ; %bb.0: ; %entry
 ; GFX10-CU-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-CU-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-CU-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-CU-NEXT:    v_add_co_u32_e64 v0, s0, s0, v0
+; GFX10-CU-NEXT:    v_add_co_u32 v0, s0, s0, v0
 ; GFX10-CU-NEXT:    v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
 ; GFX10-CU-NEXT:    flat_load_dword v2, v[0:1] slc
 ; GFX10-CU-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX10-CU-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX10-CU-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-CU-NEXT:    flat_store_dword v[0:1], v2
 ; GFX10-CU-NEXT:    s_endpgm
 ;

 ;
 ; GFX10-WGP-LABEL: flat_nontemporal_store_1:
 ; GFX10-WGP:       ; %bb.0: ; %entry
 ; GFX10-WGP-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-WGP-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-WGP-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-WGP-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-WGP-NEXT:    v_mov_b32_e32 v2, s1
-; GFX10-WGP-NEXT:    v_add_co_u32_e64 v0, s0, s2, v0
+; GFX10-WGP-NEXT:    v_add_co_u32 v0, s0, s2, v0
 ; GFX10-WGP-NEXT:    flat_load_dword v2, v[1:2]
 ; GFX10-WGP-NEXT:    v_add_co_ci_u32_e64 v1, s0, s3, 0, s0
 ; GFX10-WGP-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-WGP-NEXT:    flat_store_dword v[0:1], v2 slc
 ; GFX10-WGP-NEXT:    s_endpgm
 ;
 ; GFX10-CU-LABEL: flat_nontemporal_store_1:
 ; GFX10-CU:       ; %bb.0: ; %entry
 ; GFX10-CU-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-CU-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-CU-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-CU-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-CU-NEXT:    v_mov_b32_e32 v2, s1
-; GFX10-CU-NEXT:    v_add_co_u32_e64 v0, s0, s2, v0
+; GFX10-CU-NEXT:    v_add_co_u32 v0, s0, s2, v0
 ; GFX10-CU-NEXT:    flat_load_dword v2, v[1:2]
 ; GFX10-CU-NEXT:    v_add_co_ci_u32_e64 v1, s0, s3, 0, s0
 ; GFX10-CU-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-CU-NEXT:    flat_store_dword v[0:1], v2 slc
 ; GFX10-CU-NEXT:    s_endpgm
 ;
 ; SKIP-CACHE-INV-LABEL: flat_nontemporal_store_1:
 ; SKIP-CACHE-INV:       ; %bb.0: ; %entry

llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll

 ; GFX7-NEXT:    flat_store_dword v[0:1], v2
 ; GFX7-NEXT:    s_endpgm
 ;
 ; GFX10-WGP-LABEL: flat_nontemporal_load_1:
 ; GFX10-WGP:       ; %bb.0: ; %entry
 ; GFX10-WGP-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-WGP-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-WGP-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-WGP-NEXT:    v_add_co_u32_e64 v0, s0, s0, v0
+; GFX10-WGP-NEXT:    v_add_co_u32 v0, s0, s0, v0
 ; GFX10-WGP-NEXT:    v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
 ; GFX10-WGP-NEXT:    flat_load_dword v2, v[0:1] glc dlc
 ; GFX10-WGP-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-WGP-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX10-WGP-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX10-WGP-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-WGP-NEXT:    flat_store_dword v[0:1], v2
 ; GFX10-WGP-NEXT:    s_endpgm
 ;
 ; GFX10-CU-LABEL: flat_nontemporal_load_1:
 ; GFX10-CU:       ; %bb.0: ; %entry
 ; GFX10-CU-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-CU-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-CU-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-CU-NEXT:    v_add_co_u32_e64 v0, s0, s0, v0
+; GFX10-CU-NEXT:    v_add_co_u32 v0, s0, s0, v0
 ; GFX10-CU-NEXT:    v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
 ; GFX10-CU-NEXT:    flat_load_dword v2, v[0:1] glc dlc
 ; GFX10-CU-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-CU-NEXT:    v_mov_b32_e32 v0, s2
 ; GFX10-CU-NEXT:    v_mov_b32_e32 v1, s3
 ; GFX10-CU-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-CU-NEXT:    flat_store_dword v[0:1], v2
 ; GFX10-CU-NEXT:    s_endpgm

 ;
 ; GFX10-WGP-LABEL: flat_nontemporal_store_1:
 ; GFX10-WGP:       ; %bb.0: ; %entry
 ; GFX10-WGP-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-WGP-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-WGP-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-WGP-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-WGP-NEXT:    v_mov_b32_e32 v2, s1
-; GFX10-WGP-NEXT:    v_add_co_u32_e64 v0, s0, s2, v0
+; GFX10-WGP-NEXT:    v_add_co_u32 v0, s0, s2, v0
 ; GFX10-WGP-NEXT:    flat_load_dword v2, v[1:2]
 ; GFX10-WGP-NEXT:    v_add_co_ci_u32_e64 v1, s0, s3, 0, s0
 ; GFX10-WGP-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-WGP-NEXT:    flat_store_dword v[0:1], v2
 ; GFX10-WGP-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-WGP-NEXT:    s_endpgm
 ;
 ; GFX10-CU-LABEL: flat_nontemporal_store_1:
 ; GFX10-CU:       ; %bb.0: ; %entry
 ; GFX10-CU-NEXT:    s_load_dwordx4 s[0:3], s[4:5], 0x0
 ; GFX10-CU-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-CU-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-CU-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-CU-NEXT:    v_mov_b32_e32 v2, s1
-; GFX10-CU-NEXT:    v_add_co_u32_e64 v0, s0, s2, v0
+; GFX10-CU-NEXT:    v_add_co_u32 v0, s0, s2, v0
 ; GFX10-CU-NEXT:    flat_load_dword v2, v[1:2]
 ; GFX10-CU-NEXT:    v_add_co_ci_u32_e64 v1, s0, s3, 0, s0
 ; GFX10-CU-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-CU-NEXT:    flat_store_dword v[0:1], v2
 ; GFX10-CU-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-CU-NEXT:    s_endpgm
 ;
 ; SKIP-CACHE-INV-LABEL: flat_nontemporal_store_1:

llvm/test/CodeGen/AMDGPU/min.ll

define amdgpu_kernel void @v_test_imin_slt_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %aptr, i32 addrspace(1)* %bptr) #0 {
   store i32 %val, i32 addrspace(1)* %out.gep, align 4
   ret void
 }
 
 ; FUNC-LABEL: @v_test_imin_slt_i16
 ; SI: v_min_i32_e32
 
 ; GFX8_9: v_min_i16_e32
-; GFX10:  v_min_i16_e64
+; GFX10:  v_min_i16
 
 ; EG: MIN_INT
 define amdgpu_kernel void @v_test_imin_slt_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %aptr, i16 addrspace(1)* %bptr) #0 {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %a.gep = getelementptr inbounds i16, i16 addrspace(1)* %aptr, i32 %tid
   %b.gep = getelementptr inbounds i16, i16 addrspace(1)* %bptr, i32 %tid
   %out.gep = getelementptr inbounds i16, i16 addrspace(1)* %out, i32 %tid
 

 ; FUNC-LABEL: {{^}}v_test_umin_ult_i8:
 ; SI: {{buffer|flat|global}}_load_ubyte
 ; SI: {{buffer|flat|global}}_load_ubyte
 ; SI: v_min_u32_e32
 
 ; GFX8_9_10: {{flat|global}}_load_ubyte
 ; GFX8_9_10: {{flat|global}}_load_ubyte
 ; GFX8_9:    v_min_u16_e32
-; GFX10:     v_min_u16_e64
+; GFX10:     v_min_u16
 
 ; EG: MIN_UINT
 define amdgpu_kernel void @v_test_umin_ult_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %a.ptr, i8 addrspace(1)* %b.ptr) #0 {
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %a.gep = getelementptr inbounds i8, i8 addrspace(1)* %a.ptr, i32 %tid
   %b.gep = getelementptr inbounds i8, i8 addrspace(1)* %b.ptr, i32 %tid
   %out.gep = getelementptr inbounds i8, i8 addrspace(1)* %out, i32 %tid
 

llvm/test/CodeGen/AMDGPU/offset-split-flat.ll

 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:1
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, v0, 1
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, 1
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 1
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_11bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_11bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:2047
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_11bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x7ff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 2047
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_12bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_12bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xfff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 4095
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_13bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_13bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1fff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 8191
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_neg_11bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_neg_11bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xfffff800, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_neg_11bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xfffff800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -2048
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_neg_12bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_neg_12bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xfffff000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_neg_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xfffff000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -4096
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_neg_13bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_neg_13bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xffffe000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_neg_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xffffe000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -8192
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_2x_11bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_2x_11bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_2x_11bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xfff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 4095
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_2x_12bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_2x_12bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_2x_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1fff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 8191
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_2x_13bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_2x_13bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x3000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_2x_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x3fff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x3fff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 16383
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_2x_neg_11bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xfffff000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_2x_neg_11bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xfffff000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -4096
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_2x_neg_12bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xffffe000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_2x_neg_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xffffe000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -8192
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 define i8 @flat_inst_valu_offset_2x_neg_13bit_max(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xffffc000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_2x_neg_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xffffc000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -16384
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 11-bit low-bits (1ull << 33) | 2047
 define i8 @flat_inst_valu_offset_64bit_11bit_split0(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_64bit_11bit_split0:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:2047
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_11bit_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x7ff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 8589936639
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 11-bit low-bits (1ull << 33) | 2048
 define i8 @flat_inst_valu_offset_64bit_11bit_split1(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_64bit_11bit_split1:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:2048
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_11bit_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 8589936640
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 12-bit low-bits (1ull << 33) | 4095
 define i8 @flat_inst_valu_offset_64bit_12bit_split0(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_64bit_12bit_split0:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_12bit_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xfff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 8589938687
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 12-bit low-bits (1ull << 33) | 4096
 define i8 @flat_inst_valu_offset_64bit_12bit_split1(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_12bit_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 8589938688
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 13-bit low-bits (1ull << 33) | 8191
 define i8 @flat_inst_valu_offset_64bit_13bit_split0(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_64bit_13bit_split0:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1] offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_13bit_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1fff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 8589942783
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 13-bit low-bits (1ull << 33) | 8192
 define i8 @flat_inst_valu_offset_64bit_13bit_split1(i8* %p) {
 ; GFX9-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x2000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_13bit_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x2000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 8589942784
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x7ff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x7ff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -9223372036854773761
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -9223372036854773760
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xfff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -9223372036854771713
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -9223372036854771712
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1fff, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1fff, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -9223372036854767617
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x2000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    flat_load_ubyte v0, v[0:1]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8* %p, i64 -9223372036854767616
   %load = load i8, i8* %gep, align 4
   ret i8 %load
 }

llvm/test/CodeGen/AMDGPU/offset-split-global.ll

 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 4095
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 define i8 @global_inst_valu_offset_13bit_max(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_13bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8191
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-4096
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_neg_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xfffff000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -4096
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 define i8 @global_inst_valu_offset_neg_13bit_max(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_neg_13bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xffffe000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_neg_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xffffe000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -8192
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 define i8 @global_inst_valu_offset_2x_11bit_max(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_2x_11bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_2x_11bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 4095
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 define i8 @global_inst_valu_offset_2x_12bit_max(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_2x_12bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_2x_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8191
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 define i8 @global_inst_valu_offset_2x_13bit_max(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_2x_13bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x3000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_2x_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x3800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x3800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 16383
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 define i8 @global_inst_valu_offset_2x_neg_11bit_max(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-4096
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_2x_neg_11bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xfffff000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xfffff000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -4096
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 define i8 @global_inst_valu_offset_2x_neg_12bit_max(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xffffe000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_2x_neg_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xffffe000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffe000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -8192
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 define i8 @global_inst_valu_offset_2x_neg_13bit_max(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0xffffc000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, -1, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_2x_neg_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0xffffc000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0xffffc000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -16384
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 11-bit low-bits (1ull << 33) | 2047
 define i8 @global_inst_valu_offset_64bit_11bit_split0(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_64bit_11bit_split0:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_11bit_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589936639
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 11-bit low-bits (1ull << 33) | 2048
 define i8 @global_inst_valu_offset_64bit_11bit_split1(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_64bit_11bit_split1:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:2048
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_11bit_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589936640
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 12-bit low-bits (1ull << 33) | 4095
 define i8 @global_inst_valu_offset_64bit_12bit_split0(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_64bit_12bit_split0:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_12bit_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589938687
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 12-bit low-bits (1ull << 33) | 4096
 define i8 @global_inst_valu_offset_64bit_12bit_split1(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_64bit_12bit_split1:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_12bit_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589938688
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 13-bit low-bits (1ull << 33) | 8191
 define i8 @global_inst_valu_offset_64bit_13bit_split0(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_64bit_13bit_split0:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x1000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:4095
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_13bit_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589942783
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }
 
 ; Fill 13-bit low-bits (1ull << 33) | 8192
 define i8 @global_inst_valu_offset_64bit_13bit_split1(i8 addrspace(1)* %p) {
 ; GFX9-LABEL: global_inst_valu_offset_64bit_13bit_split1:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, 0x2000, v0
 ; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, 2, v1, vcc
 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_13bit_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x2000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589942784
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-2049
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854773761
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-2048
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854773760
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854771713
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854771712
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x2000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854767617
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x2000, v0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854767616
   %load = load i8, i8 addrspace(1)* %gep, align 4
   ret i8 %load
 }

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_neg_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0xfffff000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0xfffff000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, -1, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -4096
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_neg_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0xffffe000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, -1, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -8192
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_2x_neg_11bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0xfffff000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0xfffff000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, -1, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -4096
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_2x_neg_12bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0xffffe000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0xffffe000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, -1, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -8192
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_2x_neg_13bit_max:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0xffffc000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0xffffc000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, -1, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -16384
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_11bit_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 2, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047 glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589936639
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_11bit_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0x800, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0x800, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 2, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589936640
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_12bit_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0x800, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0x800, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 2, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047 glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589938687
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_12bit_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0x1000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0x1000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 2, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589938688
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_13bit_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0x1800, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0x1800, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 2, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:2047 glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589942783
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    s_waitcnt vmcnt(0)
 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_13bit_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, 0x2000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, 0x2000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, 2, s1, s0
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 8589942784
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s1
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, s0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1 glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854773761
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_11bit_neg_high_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s1
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x800, s0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x800, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854773760
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s1
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1 glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854771713
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_12bit_neg_high_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s1
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x1000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x1000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854771712
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split0:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s1
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x2000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off offset:-1 glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854767617
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef

 ; GFX9-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX9-NEXT:    s_endpgm
 ;
 ; GFX10-LABEL: global_inst_salu_offset_64bit_13bit_neg_high_split1:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    v_mov_b32_e32 v1, s1
-; GFX10-NEXT:    v_add_co_u32_e64 v0, vcc_lo, 0x2000, s0
+; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, 0x2000, s0
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo
 ; GFX10-NEXT:    global_load_ubyte v0, v[0:1], off glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_store_byte v[0:1], v0, off
 ; GFX10-NEXT:    s_endpgm
   %gep = getelementptr i8, i8 addrspace(1)* %p, i64 -9223372036854767616
   %load = load volatile i8, i8 addrspace(1)* %gep, align 1
   store i8 %load, i8 addrspace(1)* undef
   ret void
 }

llvm/test/CodeGen/AMDGPU/preserve-hi16.ll

 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
 ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10 %s
 
 ; GCN-LABEL: {{^}}shl_i16:
-; GCN: v_lshlrev_b16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_lshlrev_b16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @shl_i16(i16 %x, i16 %y) {
   %res = shl i16 %x, %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}lshr_i16:
-; GCN: v_lshrrev_b16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_lshrrev_b16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @lshr_i16(i16 %x, i16 %y) {
   %res = lshr i16 %x, %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}ashr_i16:
-; GCN: v_ashrrev_i16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_ashrrev_i16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @ashr_i16(i16 %x, i16 %y) {
   %res = ashr i16 %x, %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}add_u16:
-; GCN: v_add_{{(nc_)*}}u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_add_{{(nc_)*}}u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @add_u16(i16 %x, i16 %y) {
   %res = add i16 %x, %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}sub_u16:
-; GCN: v_sub_{{(nc_)*}}u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_sub_{{(nc_)*}}u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @sub_u16(i16 %x, i16 %y) {
   %res = sub i16 %x, %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}mul_lo_u16:
-; GCN: v_mul_lo_u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_mul_lo_u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @mul_lo_u16(i16 %x, i16 %y) {
   %res = mul i16 %x, %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}min_u16:
-; GCN: v_min_u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_min_u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @min_u16(i16 %x, i16 %y) {
   %cmp = icmp ule i16 %x, %y
   %res = select i1 %cmp, i16 %x, i16 %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}min_i16:
-; GCN: v_min_i16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_min_i16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @min_i16(i16 %x, i16 %y) {
   %cmp = icmp sle i16 %x, %y
   %res = select i1 %cmp, i16 %x, i16 %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}max_u16:
-; GCN: v_max_u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_max_u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @max_u16(i16 %x, i16 %y) {
   %cmp = icmp uge i16 %x, %y
   %res = select i1 %cmp, i16 %x, i16 %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}max_i16:
-; GCN: v_max_i16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_max_i16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GCN-NEXT: s_setpc_b64
 define i16 @max_i16(i16 %x, i16 %y) {
   %cmp = icmp sge i16 %x, %y
   %res = select i1 %cmp, i16 %x, i16 %y
   ret i16 %res
 }
 
 ; GCN-LABEL: {{^}}shl_i16_zext_i32:
-; GCN: v_lshlrev_b16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_lshlrev_b16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @shl_i16_zext_i32(i16 %x, i16 %y) {
   %res = shl i16 %x, %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }
 
 ; GCN-LABEL: {{^}}lshr_i16_zext_i32:
-; GCN: v_lshrrev_b16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_lshrrev_b16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @lshr_i16_zext_i32(i16 %x, i16 %y) {
   %res = lshr i16 %x, %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }
 
 ; GCN-LABEL: {{^}}ashr_i16_zext_i32:
-; GCN: v_ashrrev_i16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_ashrrev_i16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @ashr_i16_zext_i32(i16 %x, i16 %y) {
   %res = ashr i16 %x, %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }
 
 ; GCN-LABEL: {{^}}add_u16_zext_i32:
-; GCN: v_add_{{(nc_)*}}u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_add_{{(nc_)*}}u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @add_u16_zext_i32(i16 %x, i16 %y) {
   %res = add i16 %x, %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }
 
 ; GCN-LABEL: {{^}}sub_u16_zext_i32:
-; GCN: v_sub_{{(nc_)*}}u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_sub_{{(nc_)*}}u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @sub_u16_zext_i32(i16 %x, i16 %y) {
   %res = sub i16 %x, %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }
 
 ; GCN-LABEL: {{^}}mul_lo_u16_zext_i32:
-; GCN: v_mul_lo_u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_mul_lo_u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @mul_lo_u16_zext_i32(i16 %x, i16 %y) {
   %res = mul i16 %x, %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }
 
 ; GCN-LABEL: {{^}}min_u16_zext_i32:
-; GCN: v_min_u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_min_u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @min_u16_zext_i32(i16 %x, i16 %y) {
   %cmp = icmp ule i16 %x, %y
   %res = select i1 %cmp, i16 %x, i16 %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }
 
 ; GCN-LABEL: {{^}}min_i16_zext_i32:
-; GCN: v_min_i16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_min_i16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @min_i16_zext_i32(i16 %x, i16 %y) {
   %cmp = icmp sle i16 %x, %y
   %res = select i1 %cmp, i16 %x, i16 %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }
 
 ; GCN-LABEL: {{^}}max_u16_zext_i32:
-; GCN: v_max_u16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_max_u16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @max_u16_zext_i32(i16 %x, i16 %y) {
   %cmp = icmp uge i16 %x, %y
   %res = select i1 %cmp, i16 %x, i16 %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }
 
 ; GCN-LABEL: {{^}}max_i16_zext_i32:
-; GCN: v_max_i16_e{{32|64}} [[OP:v[0-9]+]],
+; GCN: v_max_i16{{[_e32]*}} [[OP:v[0-9]+]],
 ; GFX10-NEXT: v_and_b32_e32 v{{[0-9]+}}, 0xffff, [[OP]]
 ; GCN-NEXT: s_setpc_b64
 define i32 @max_i16_zext_i32(i16 %x, i16 %y) {
   %cmp = icmp sge i16 %x, %y
   %res = select i1 %cmp, i16 %x, i16 %y
   %zext = zext i16 %res to i32
   ret i32 %zext
 }

llvm/test/CodeGen/AMDGPU/saddo.ll

 ; GFX10-NEXT:    v_mov_b32_e32 v2, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_add_u32 s0, s6, s2
 ; GFX10-NEXT:    s_addc_u32 s1, s7, s3
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s2, s[2:3], 0
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s3, s[0:1], s[6:7]
 ; GFX10-NEXT:    s_xor_b32 s2, s2, s3
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s2
-; GFX10-NEXT:    v_add_co_u32_e64 v0, s0, s0, v0
+; GFX10-NEXT:    v_add_co_u32 v0, s0, s0, v0
 ; GFX10-NEXT:    v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
 ; GFX10-NEXT:    global_store_dwordx2 v2, v[0:1], s[4:5]
 ; GFX10-NEXT:    s_endpgm
   %sadd = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) nounwind
   %val = extractvalue { i64, i1 } %sadd, 0
   %carry = extractvalue { i64, i1 } %sadd, 1
   %ext = zext i1 %carry to i64
   %add2 = add i64 %val, %ext

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx8 s[4:11], s[0:1], 0x24
 ; GFX10-NEXT:    v_mov_b32_e32 v6, 0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    s_clause 0x1
 ; GFX10-NEXT:    global_load_dwordx2 v[9:10], v6, s[8:9]
 ; GFX10-NEXT:    global_load_dwordx2 v[2:3], v6, s[10:11]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_add_co_u32_e64 v7, vcc_lo, v9, v2
+; GFX10-NEXT:    v_add_co_u32 v7, vcc_lo, v9, v2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, v10, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e32 vcc_lo, 0, v[2:3]
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s0, v[7:8], v[9:10]
 ; GFX10-NEXT:    s_xor_b32 s0, vcc_lo, s0
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0
 ; GFX10-NEXT:    global_store_dwordx2 v6, v[7:8], s[4:5]
 ; GFX10-NEXT:    global_store_byte v6, v0, s[6:7]
 ; GFX10-NEXT:    s_endpgm

llvm/test/CodeGen/AMDGPU/saddsat.ll

 ; GFX9-NEXT:    v_add_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_saddsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 8, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 8, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
 ; GFX10-NEXT:    v_add_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.sadd.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_saddsat_i16(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_saddsat_i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_saddsat_i64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_add_co_u32_e64 v10, vcc_lo, v0, v2
+; GFX10-NEXT:    v_add_co_u32 v10, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_bfrev_b32_e32 v6, -2
 ; GFX10-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s4, 0, v[2:3]
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s5, 0, v[10:11]
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[0:1]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v11
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo

llvm/test/CodeGen/AMDGPU/sdwa-peephole.ll

define amdgpu_kernel void @mul_shr_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in1, i32 addrspace(1)* %in2) #0 {
   store i32 %mul, i32 addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}mul_i16:
 ; NOSDWA: v_mul_lo_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
 ; GFX89: v_mul_lo_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
-; GFX10: v_mul_lo_u16_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX10: v_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 ; SDWA-NOT: v_mul_u32_u24_sdwa
 
 define amdgpu_kernel void @mul_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %ina, i16 addrspace(1)* %inb) #0 {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gepa = getelementptr i16, i16 addrspace(1)* %ina, i32 %idx
   %gepb = getelementptr i16, i16 addrspace(1)* %inb, i32 %idx
   %a = load i16, i16 addrspace(1)* %gepa, align 4
entry:
   store <8 x half> %mul, <8 x half> addrspace(1)* %out, align 4
   ret void
 }
 
 ; GCN-LABEL: {{^}}mul_i8:
 ; NOSDWA: v_mul_lo_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
 ; GFX89: v_mul_lo_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
-; GFX10: v_mul_lo_u16_e64 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX10: v_mul_lo_u16 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 ; SDWA-NOT: v_mul_u32_u24_sdwa
 
 define amdgpu_kernel void @mul_i8(i8 addrspace(1)* %out, i8 addrspace(1)* %ina, i8 addrspace(1)* %inb) #0 {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gepa = getelementptr i8, i8 addrspace(1)* %ina, i32 %idx
   %gepb = getelementptr i8, i8 addrspace(1)* %inb, i32 %idx
   %a = load i8, i8 addrspace(1)* %gepa, align 4

 ; NOSDWA: v_or_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 ; NOSDWA-NOT: v_mul_u32_u24_sdwa
 
 ; VI: v_mul_lo_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
 
 ; GFX9-DAG: v_mul_lo_u16_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1
 ; GFX9-DAG: v_mul_lo_u16_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
 
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
 
 ; GFX9: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 
-; GFX10: v_lshlrev_b16_e64 v{{[0-9]+}}, 8, v
+; GFX10: v_lshlrev_b16 v{{[0-9]+}}, 8, v
 ; GFX10: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
 define amdgpu_kernel void @mul_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(1)* %ina, <2 x i8> addrspace(1)* %inb) #0 {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gepa = getelementptr <2 x i8>, <2 x i8> addrspace(1)* %ina, i32 %idx
   %gepb = getelementptr <2 x i8>, <2 x i8> addrspace(1)* %inb, i32 %idx
   %a = load <2 x i8>, <2 x i8> addrspace(1)* %gepa, align 4
   %b = load <2 x i8>, <2 x i8> addrspace(1)* %gepb, align 4

 ; VI-DAG: v_mul_lo_u16_sdwa
 ; VI-DAG: v_mul_lo_u16_sdwa
 ; VI-DAG: v_mul_lo_u16_sdwa
 
 ; GFX9-DAG: v_mul_lo_u16_sdwa
 ; GFX9-DAG: v_mul_lo_u16_sdwa
 ; GFX9-DAG: v_mul_lo_u16_sdwa
 
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
 
 define amdgpu_kernel void @mul_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(1)* %ina, <4 x i8> addrspace(1)* %inb) #0 {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gepa = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %ina, i32 %idx
   %gepb = getelementptr <4 x i8>, <4 x i8> addrspace(1)* %inb, i32 %idx
   %a = load <4 x i8>, <4 x i8> addrspace(1)* %gepa, align 4
   %b = load <4 x i8>, <4 x i8> addrspace(1)* %gepb, align 4

 
 ; GFX9-DAG: v_mul_lo_u16_sdwa
 ; GFX9-DAG: v_mul_lo_u16_sdwa
 ; GFX9-DAG: v_mul_lo_u16_sdwa
 ; GFX9-DAG: v_mul_lo_u16_sdwa
 ; GFX9-DAG: v_mul_lo_u16_sdwa
 ; GFX9-DAG: v_mul_lo_u16_sdwa
 
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
-; GFX10-DAG: v_mul_lo_u16_e64
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
+; GFX10-DAG: v_mul_lo_u16
 
 define amdgpu_kernel void @mul_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(1)* %ina, <8 x i8> addrspace(1)* %inb) #0 {
 entry:
   %idx = call i32 @llvm.amdgcn.workitem.id.x()
   %gepa = getelementptr <8 x i8>, <8 x i8> addrspace(1)* %ina, i32 %idx
   %gepb = getelementptr <8 x i8>, <8 x i8> addrspace(1)* %inb, i32 %idx
   %a = load <8 x i8>, <8 x i8> addrspace(1)* %gepa, align 4
   %b = load <8 x i8>, <8 x i8> addrspace(1)* %gepb, align 4

llvm/test/CodeGen/AMDGPU/shl_add_ptr_csub.ll

 ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
 
 ; GCN-LABEL: {{^}}shl_base_atomicrmw_global_atomic_csub_ptr:
 ; GCN-DAG: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5]
 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 43
-; GCN: v_add_co_u32_e64 v[[EXTRA_LO:[0-9]+]], vcc_lo, 0x80, v4
+; GCN: v_add_co_u32 v[[EXTRA_LO:[0-9]+]], vcc_lo, 0x80, v4
 ; GCN: v_add_co_ci_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc_lo, 0, v5, vcc_lo
 ; GCN: global_atomic_csub v{{[0-9]+}}, v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]], off offset:512 glc
 ; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[EXTRA_LO]]:[[EXTRA_HI]]{{\]}}
 define i32 @shl_base_atomicrmw_global_atomic_csub_ptr(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 {
   %arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32
   %cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64
   %shl = shl i64 %cast, 2
   %castback = inttoptr i64 %shl to i32 addrspace(1)*
   %val = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %castback, i32 43)
   store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4
   ret i32 %val
 }
 
 declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #0
 
 attributes #0 = { argmemonly nounwind }

llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll

 ;
 ; GFX10-LABEL: v_test_i16_x_sub_64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_sub_nc_u16_e64 v1, v1, 64
+; GFX10-NEXT:    v_sub_nc_u16 v1, v1, 64
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext
   %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext
   %x = load i16, i16 addrspace(1)* %gep
   %result = sub i16 %x, 64

 ; GFX10-LABEL: v_test_i16_x_sub_64_zext_to_i32:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v1, 1, v0
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 2, v0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    global_load_ushort v1, v1, s[2:3]
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_sub_nc_u16_e64 v1, v1, 64
+; GFX10-NEXT:    v_sub_nc_u16 v1, v1, 64
 ; GFX10-NEXT:    v_and_b32_e32 v1, 0xffff, v1
 ; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
 ; GFX10-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext
   %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
   %x = load i16, i16 addrspace(1)* %gep

 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[0:1], 0x24
 ; GFX10-NEXT:    v_lshlrev_b32_e32 v0, 1, v0
 ; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
 ; GFX10-NEXT:    global_load_ushort v1, v0, s[2:3] glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-NEXT:    global_load_ushort v2, v0, s[2:3] glc dlc
 ; GFX10-NEXT:    s_waitcnt vmcnt(0)
-; GFX10-NEXT:    v_sub_nc_u16_e64 v1, v1, 64
-; GFX10-NEXT:    v_sub_nc_u16_e64 v2, v2, 64
+; GFX10-NEXT:    v_sub_nc_u16 v1, v1, 64
+; GFX10-NEXT:    v_sub_nc_u16 v2, v2, 64
 ; GFX10-NEXT:    global_store_short v0, v1, s[0:1]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    global_store_short v0, v2, s[0:1]
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_endpgm
   %tid = call i32 @llvm.amdgcn.workitem.id.x()
   %tid.ext = sext i32 %tid to i64
   %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext

llvm/test/CodeGen/AMDGPU/ssubsat.ll

 ; GFX9-NEXT:    v_sub_i16 v0, v0, v1 clamp
 ; GFX9-NEXT:    v_ashrrev_i16_e32 v0, 8, v0
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_ssubsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_lshlrev_b16_e64 v1, 8, v1
-; GFX10-NEXT:    v_lshlrev_b16_e64 v0, 8, v0
+; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1
+; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0
 ; GFX10-NEXT:    v_sub_nc_i16 v0, v0, v1 clamp
-; GFX10-NEXT:    v_ashrrev_i16_e64 v0, 8, v0
+; GFX10-NEXT:    v_ashrrev_i16 v0, 8, v0
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_ssubsat_i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_ssubsat_i64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_co_u32_e64 v10, vcc_lo, v0, v2
+; GFX10-NEXT:    v_sub_co_u32 v10, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_bfrev_b32_e32 v6, -2
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v11, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_lt_i64_e64 s4, 0, v[2:3]
 ; GFX10-NEXT:    v_cmp_gt_i64_e64 s5, 0, v[10:11]
 ; GFX10-NEXT:    v_cmp_lt_i64_e32 vcc_lo, v[10:11], v[0:1]
 ; GFX10-NEXT:    v_ashrrev_i32_e32 v0, 31, v11
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0x80000000, v6, s5
 ; GFX10-NEXT:    s_xor_b32 vcc_lo, s4, vcc_lo

llvm/test/CodeGen/AMDGPU/usubsat.ll

 ;
 ; GFX10-LABEL: v_usubsat_i8:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GFX10-NEXT:    s_movk_i32 s4, 0xff
 ; GFX10-NEXT:    v_and_b32_e32 v1, s4, v1
 ; GFX10-NEXT:    v_and_b32_e32 v0, s4, v0
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, v0, v1 clamp
+; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)
   ret i8 %result
 }
 
 define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {
 ; GFX6-LABEL: v_usubsat_i16:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX9-NEXT:    v_sub_u16_e64 v0, v0, v1 clamp
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_usubsat_i16:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_nc_u16_e64 v0, v0, v1 clamp
+; GFX10-NEXT:    v_sub_nc_u16 v0, v0, v1 clamp
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)
   ret i16 %result
 }
 
 define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {
 ; GFX6-LABEL: v_usubsat_i32:
 ; GFX6:       ; %bb.0:

 ; GFX9-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc
 ; GFX9-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc
 ; GFX9-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX10-LABEL: v_usubsat_i64:
 ; GFX10:       ; %bb.0:
 ; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
-; GFX10-NEXT:    v_sub_co_u32_e64 v2, vcc_lo, v0, v2
+; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v0, v2
 ; GFX10-NEXT:    v_sub_co_ci_u32_e32 v3, vcc_lo, v1, v3, vcc_lo
 ; GFX10-NEXT:    v_cmp_gt_u64_e32 vcc_lo, v[2:3], v[0:1]
 ; GFX10-NEXT:    v_cndmask_b32_e64 v0, v2, 0, vcc_lo
 ; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, 0, vcc_lo
 ; GFX10-NEXT:    s_setpc_b64 s[30:31]
   %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)
   ret i64 %result
 }

llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -march=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefix=GCN
 
 define void @vgpr_descriptor_waterfall_loop_idom_update(<4 x i32>* %arg) #0 {
 ; GCN-LABEL: vgpr_descriptor_waterfall_loop_idom_update:
 ; GCN:       ; %bb.0: ; %entry
 ; GCN-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GCN-NEXT:    s_waitcnt_vscnt null, 0x0
 ; GCN-NEXT:  BB0_1: ; %bb0
 ; GCN-NEXT:    ; =>This Loop Header: Depth=1
 ; GCN-NEXT:    ; Child Loop BB0_2 Depth 2
-; GCN-NEXT:    v_add_co_u32_e64 v6, vcc_lo, v0, 8
+; GCN-NEXT:    v_add_co_u32 v6, vcc_lo, v0, 8
 ; GCN-NEXT:    s_mov_b32 s5, exec_lo
 ; GCN-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, 0, v1, vcc_lo
 ; GCN-NEXT:    s_clause 0x1
 ; GCN-NEXT:    flat_load_dwordx2 v[2:3], v[6:7]
 ; GCN-NEXT:    flat_load_dwordx2 v[4:5], v[0:1]
 ; GCN-NEXT:  BB0_2: ; Parent Loop BB0_1 Depth=1
 ; GCN-NEXT:    ; => This Inner Loop Header: Depth=2
 ; GCN-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)

llvm/test/CodeGen/AMDGPU/wave32.ll

bb8:
   %tmp12 = and i1 %tmp10, %tmp11
   br i1 %tmp12, label %bb2, label %.loopexit
 
 .loopexit:
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_addc_vop2b:
-; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, s{{[0-9]+}}
+; GFX1032: v_add_co_u32 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, s{{[0-9]+}}
 ; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}}, vcc_lo
-; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, s{{[0-9]+}}
+; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, s{{[0-9]+}}
 ; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}, vcc{{$}}
 define amdgpu_kernel void @test_addc_vop2b(i64 addrspace(1)* %arg, i64 %arg1) #0 {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp3 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tmp
   %tmp4 = load i64, i64 addrspace(1)* %tmp3, align 8
   %tmp5 = add nsw i64 %tmp4, %arg1
   store i64 %tmp5, i64 addrspace(1)* %tmp3, align 8
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_subbrev_vop2b:
-; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], v{{[0-9]+}}, s{{[0-9]+}}{{$}}
+; GFX1032: v_sub_co_u32 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], v{{[0-9]+}}, s{{[0-9]+}}{{$}}
 ; GFX1032: v_subrev_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[A0]]{{$}}
-; GFX1064: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s\[[0-9:]+\]|vcc]], v{{[0-9]+}}, s{{[0-9]+}}{{$}}
+; GFX1064: v_sub_co_u32 v{{[0-9]+}}, [[A0:s\[[0-9:]+\]|vcc]], v{{[0-9]+}}, s{{[0-9]+}}{{$}}
 ; GFX1064: v_subrev_co_ci_u32_e32 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, {{[vs][0-9]+}}, [[A0]]{{$}}
 define amdgpu_kernel void @test_subbrev_vop2b(i64 addrspace(1)* %arg, i64 %arg1) #0 {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp3 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tmp
   %tmp4 = load i64, i64 addrspace(1)* %tmp3, align 8
   %tmp5 = sub nsw i64 %tmp4, %arg1
   store i64 %tmp5, i64 addrspace(1)* %tmp3, align 8
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_subb_vop2b:
-; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], s{{[0-9]+}}, v{{[0-9]+}}{{$}}
+; GFX1032: v_sub_co_u32 v{{[0-9]+}}, [[A0:s[0-9]+|vcc_lo]], s{{[0-9]+}}, v{{[0-9]+}}{{$}}
 ; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, [[A0]]{{$}}
-; GFX1064: v_sub_co_u32_e64 v{{[0-9]+}}, [[A0:s\[[0-9:]+\]|vcc]], s{{[0-9]+}}, v{{[0-9]+}}{{$}}
+; GFX1064: v_sub_co_u32 v{{[0-9]+}}, [[A0:s\[[0-9:]+\]|vcc]], s{{[0-9]+}}, v{{[0-9]+}}{{$}}
 ; GFX1064: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, v{{[0-9]+}}, [[A0]]{{$}}
 define amdgpu_kernel void @test_subb_vop2b(i64 addrspace(1)* %arg, i64 %arg1) #0 {
 bb:
   %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   %tmp3 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i32 %tmp
   %tmp4 = load i64, i64 addrspace(1)* %tmp3, align 8
   %tmp5 = sub nsw i64 %arg1, %tmp4
   store i64 %tmp5, i64 addrspace(1)* %tmp3, align 8
   ret void
 }
 
 ; GCN-LABEL: {{^}}test_udiv64:
-; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, [[SDST:s[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
+; GFX1032: v_add_co_u32 v{{[0-9]+}}, [[SDST:s[0-9]+]], v{{[0-9]+}}, v{{[0-9]+}}
 ; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0, v{{[0-9]+}}, vcc_lo
 ; GFX1032: v_add_co_ci_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}, [[SDST]]
-; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
-; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
-; GFX1032: v_add_co_u32_e64 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX1032: v_add_co_u32 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX1032: v_add_co_u32 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX1032: v_add_co_u32 v{{[0-9]+}}, vcc_lo, v{{[0-9]+}}, v{{[0-9]+}}
 ; GFX1032: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, 0, v{{[0-9]+}}, vcc_lo
-; GFX1032: v_sub_co_u32_e64 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}}
+; GFX1032: v_sub_co_u32 v{{[0-9]+}}, vcc_lo, s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX1032: v_subrev_co_ci_u32_e64 v{{[0-9]+}}, s{{[0-9]+}}, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo
 ; GFX1032: v_sub_co_ci_u32_e32 v{{[0-9]+}}, vcc_lo, {{[vs][0-9]+}}, v{{[0-9]+}}, vcc_lo
-; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, [[SDST:s\[[0-9:]+\]]], v{{[0-9]+}}, v{{[0-9]+}}
+; GFX1064: v_add_co_u32 v{{[0-9]+}}, [[SDST:s\[[0-9:]+\]]], v{{[0-9]+}}, v{{[0-9]+}}
 ; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
 ; GFX1064: v_add_co_ci_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, [[SDST]]
-; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
-; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
-; GFX1064: v_add_co_u32_e64 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
+; GFX1064: v_add_co_u32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
 ; GFX1064: v_add_co_ci_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc{{$}}
-; GFX1064: v_sub_co_u32_e64 v{{[0-9]+}}, s[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}}
+; GFX1064: v_sub_co_u32 v{{[0-9]+}}, s[{{[0-9:]+}}], s{{[0-9]+}}, v{{[0-9]+}}
 ; GFX1064: v_subrev_co_ci_u32_e64 v{{[0-9]+}}, vcc, {{[vs][0-9]+}}, v{{[0-9]+}}, s[{{[0-9:]+}}]
 ; GFX1064: v_sub_co_ci_u32_e64 v{{[0-9]+}}, s[{{[0-9:]+}}], {{[vs][0-9]+}}, v{{[0-9]+}}, s[{{[0-9:]+}}]
 define amdgpu_kernel void @test_udiv64(i64 addrspace(1)* %arg) #0 {
 bb:
   %tmp = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 1
   %tmp1 = load i64, i64 addrspace(1)* %tmp, align 8
   %tmp2 = load i64, i64 addrspace(1)* %arg, align 8
   %tmp3 = udiv i64 %tmp1, %tmp2

llvm/test/MC/AMDGPU/gfx90a_asm_features.s

 // NOT-GFX90A: error: instruction not supported on this GPU
 // GFX90A: v_fmac_f64_e64 v[4:5], v[2:3], v[8:9] mul:4 ; encoding: [0x04,0x00,0x04,0xd1,0x02,0x11,0x02,0x10]
 v_fmac_f64_e64 v[4:5], v[2:3], v[8:9] mul:4
 
 // NOT-GFX90A: error: instruction not supported on this GPU
 // GFX90A: v_fmac_f64_e64 v[4:5], v[2:3], v[8:9] div:2 ; encoding: [0x04,0x00,0x04,0xd1,0x02,0x11,0x02,0x18]
 v_fmac_f64_e64 v[4:5], v[2:3], v[8:9] div:2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00]
 v_mul_legacy_f32_e64 v5, v1, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v255, v1, v2 ; encoding: [0xff,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v255, v1, v2 ; encoding: [0xff,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00]
 v_mul_legacy_f32_e64 v255, v1, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v255, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xff,0x05,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v255, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xff,0x05,0x02,0x00]
 v_mul_legacy_f32_e64 v5, v255, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, s1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, s1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, s1, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, s101, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x65,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, s101, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x65,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, s101, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x6a,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x6a,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, vcc_lo, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x6b,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x6b,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, vcc_hi, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, m0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7c,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, m0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7c,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, m0, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, exec_lo, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7e,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, exec_lo, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7e,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, exec_lo, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, exec_hi, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7f,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, exec_hi, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7f,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, exec_hi, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, 0, v2  ; encoding: [0x05,0x00,0xa1,0xd2,0x80,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, 0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x80,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, 0, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, -1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xc1,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, -1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xc1,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, -1, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, 0.5, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xf0,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, 0.5, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xf0,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, 0.5, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, -4.0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xf7,0x04,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, -4.0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xf7,0x04,0x02,0x00]
 v_mul_legacy_f32_e64 v5, -4.0, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, v255 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xff,0x03,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, v255 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xff,0x03,0x00]
 v_mul_legacy_f32_e64 v5, v1, v255
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, s2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x00,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, s2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x00,0x00]
 v_mul_legacy_f32_e64 v5, v1, s2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, s101 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xcb,0x00,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, s101 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xcb,0x00,0x00]
 v_mul_legacy_f32_e64 v5, v1, s101
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, vcc_lo ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xd5,0x00,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, vcc_lo ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xd5,0x00,0x00]
 v_mul_legacy_f32_e64 v5, v1, vcc_lo
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, vcc_hi ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xd7,0x00,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, vcc_hi ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xd7,0x00,0x00]
 v_mul_legacy_f32_e64 v5, v1, vcc_hi
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, m0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xf9,0x00,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, m0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xf9,0x00,0x00]
 v_mul_legacy_f32_e64 v5, v1, m0
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, exec_lo ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xfd,0x00,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, exec_lo ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xfd,0x00,0x00]
 v_mul_legacy_f32_e64 v5, v1, exec_lo
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, exec_hi ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xff,0x00,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, exec_hi ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xff,0x00,0x00]
 v_mul_legacy_f32_e64 v5, v1, exec_hi
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, 0  ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x01,0x01,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, 0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x01,0x01,0x00]
 v_mul_legacy_f32_e64 v5, v1, 0
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, -1 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x83,0x01,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, -1 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x83,0x01,0x00]
 v_mul_legacy_f32_e64 v5, v1, -1
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, 0.5 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xe1,0x01,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, 0.5 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xe1,0x01,0x00]
 v_mul_legacy_f32_e64 v5, v1, 0.5
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, -4.0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xef,0x01,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, -4.0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xef,0x01,0x00]
 v_mul_legacy_f32_e64 v5, v1, -4.0
 
-// GFX90A: v_mul_legacy_f32_e64 v5, -v1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x20]
+// GFX90A: v_mul_legacy_f32 v5, -v1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x20]
 v_mul_legacy_f32_e64 v5, -v1, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, -v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x40]
+// GFX90A: v_mul_legacy_f32 v5, v1, -v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x40]
 v_mul_legacy_f32_e64 v5, v1, -v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, -v1, -v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x60]
+// GFX90A: v_mul_legacy_f32 v5, -v1, -v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x60]
 v_mul_legacy_f32_e64 v5, -v1, -v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, |v1|, v2 ; encoding: [0x05,0x01,0xa1,0xd2,0x01,0x05,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, |v1|, v2 ; encoding: [0x05,0x01,0xa1,0xd2,0x01,0x05,0x02,0x00]
 v_mul_legacy_f32_e64 v5, |v1|, v2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, |v2| ; encoding: [0x05,0x02,0xa1,0xd2,0x01,0x05,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, |v2| ; encoding: [0x05,0x02,0xa1,0xd2,0x01,0x05,0x02,0x00]
 v_mul_legacy_f32_e64 v5, v1, |v2|
 
-// GFX90A: v_mul_legacy_f32_e64 v5, |v1|, |v2| ; encoding: [0x05,0x03,0xa1,0xd2,0x01,0x05,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, |v1|, |v2| ; encoding: [0x05,0x03,0xa1,0xd2,0x01,0x05,0x02,0x00]
 v_mul_legacy_f32_e64 v5, |v1|, |v2|
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 clamp ; encoding: [0x05,0x80,0xa1,0xd2,0x01,0x05,0x02,0x00]
+// GFX90A: v_mul_legacy_f32 v5, v1, v2 clamp ; encoding: [0x05,0x80,0xa1,0xd2,0x01,0x05,0x02,0x00]
 v_mul_legacy_f32_e64 v5, v1, v2 clamp
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 mul:2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x08]
+// GFX90A: v_mul_legacy_f32 v5, v1, v2 mul:2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x08]
 v_mul_legacy_f32_e64 v5, v1, v2 mul:2
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 mul:4 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x10]
+// GFX90A: v_mul_legacy_f32 v5, v1, v2 mul:4 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x10]
 v_mul_legacy_f32_e64 v5, v1, v2 mul:4
 
-// GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 div:2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x18]
+// GFX90A: v_mul_legacy_f32 v5, v1, v2 div:2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x18]
 v_mul_legacy_f32_e64 v5, v1, v2 div:2
 
 // GFX90A: v_xor_b32_dpp v6, v29, v27  row_newbcast:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x36,0x0c,0x2a,0x1d,0x50,0x01,0xff]
 // NOT-GFX90A: error: not a valid operand.
 v_xor_b32 v6, v29, v27 row_newbcast:0
 
 // GFX90A: v_xor_b32_dpp v6, v29, v27  row_newbcast:7 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x36,0x0c,0x2a,0x1d,0x57,0x01,0xff]
 // NOT-GFX90A: error: not a valid operand.

llvm/test/MC/AMDGPU/literalv216.s

 
 //===----------------------------------------------------------------------===//
 // Packed VOP2
 //===----------------------------------------------------------------------===//
 
 // FIXME: v_pk_fmac_f16 cannot be promoted to VOP3 so '_e32' suffix is not valid
 v_pk_fmac_f16 v5, 0x12345678, v2
 // NOGFX9: error: instruction not supported on this GPU
-// GFX10: v_pk_fmac_f16_e32 v5, 0x12345678, v2 ; encoding: [0xff,0x04,0x0a,0x78,0x78,0x56,0x34,0x12]
+// GFX10: v_pk_fmac_f16 v5, 0x12345678, v2 ; encoding: [0xff,0x04,0x0a,0x78,0x78,0x56,0x34,0x12]

llvm/test/MC/AMDGPU/vop3-literal.s

 // GFX9-ERR:  error: literal operands are not supported
 // GFX10: v_bfe_u32 v0, s1, 0x3039, s1 ; encoding: [0x00,0x00,0x48,0xd5,0x01,0xfe,0x05,0x00,0x39,0x30,0x00,0x00]
 
 v_bfe_u32 v0, s1, 0x3039, s2
 // GFX9-ERR:  error: literal operands are not supported
 // GFX10-ERR: error: invalid operand (violates constant bus restrictions)
 
 v_bfm_b32_e64 v0, 0x3039, s1
-// GFX10:     v_bfm_b32_e64 v0, 0x3039, s1    ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x00,0x00,0x39,0x30,0x00,0x00]
+// GFX10:     v_bfm_b32 v0, 0x3039, s1 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x00,0x00,0x39,0x30,0x00,0x00]
 // GFX9-ERR:  error: literal operands are not supported
 
 v_bfm_b32_e64 v0, 0x3039, v1
-// GFX10:    v_bfm_b32_e64 v0, 0x3039, v1    ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x02,0x00,0x39,0x30,0x00,0x00]
+// GFX10:    v_bfm_b32 v0, 0x3039, v1 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x02,0x00,0x39,0x30,0x00,0x00]
 // GFX9-ERR: error: literal operands are not supported
 
 v_bfm_b32_e64 v0, 0x3039, 0x3039
-// GFX10:    v_bfm_b32_e64 v0, 0x3039, 0x3039 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0xfe,0x01,0x00,0x39,0x30,0x00,0x00]
+// GFX10:    v_bfm_b32 v0, 0x3039, 0x3039 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0xfe,0x01,0x00,0x39,0x30,0x00,0x00]
 // GFX9-ERR: error: literal operands are not supported
 
 v_bfm_b32_e64 v0, 0x3039, 0x3038
 // GFX10-ERR: error: only one literal operand is allowed
 // GFX9-ERR:  error: literal operands are not supported
 
 v_pk_add_f16 v1, 25.0, v2
 // GFX10:    v_pk_add_f16 v1, 0x4e40, v2     ; encoding: [0x01,0x40,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,0x4e,0x00,0x00]

 // GFX10: v_add_f64 v[0:1], 0x3ff3c0c1, -|0x3ff3c0c1| ; encoding: [0x00,0x02,0x64,0xd5,0xff,0xfe,0x01,0x40,0xc1,0xc0,0xf3,0x3f]
 // GFX9-ERR: error: literal operands are not supported
 
 v_add_f64 v[0:1], 1.23456, -abs(1.2345)
 // GFX10-ERR: error: only one literal operand is allowed
 // GFX9-ERR:  error: literal operands are not supported
 
 v_max_i16_e64 v5, 0xfe0b, v2
-// GFX10: v_max_i16_e64 v5, 0xfe0b, v2    ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x0b,0xfe,0x00,0x00]
+// GFX10: v_max_i16 v5, 0xfe0b, v2 ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x0b,0xfe,0x00,0x00]
 // GFX9-ERR: error: literal operands are not supported
 
 v_max_i16_e64 v5, v1, 0x123
-// GFX10: v_max_i16_e64 v5, v1, 0x123     ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x23,0x01,0x00,0x00]
+// GFX10: v_max_i16 v5, v1, 0x123 ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x23,0x01,0x00,0x00]
 // GFX9-ERR: error: literal operands are not supported
 
 v_max_i16_e64 v5, 0x1234, 0x1234
-// GFX10: v_max_i16_e64 v5, 0x1234, 0x1234 ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0xfe,0x01,0x00,0x34,0x12,0x00,0x00]
+// GFX10: v_max_i16 v5, 0x1234, 0x1234 ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0xfe,0x01,0x00,0x34,0x12,0x00,0x00]
 // GFX9-ERR: error: literal operands are not supported
 
 v_min3_i16 v5, 0xfe0b, v2, v3
 // GFX10: v_min3_i16 v5, 0xfe0b, v2, v3   ; encoding: [0x05,0x00,0x52,0xd7,0xff,0x04,0x0e,0x04,0x0b,0xfe,0x00,0x00]
 // GFX9-ERR: error: literal operands are not supported
 
 v_min3_i16 v5, v1, 0x1234, v3
 // GFX10: v_min3_i16 v5, v1, 0x1234, v3   ; encoding: [0x05,0x00,0x52,0xd7,0x01,0xff,0x0d,0x04,0x34,0x12,0x00,0x00]

 // GFX10-ERR: error: only one literal operand is allowed
 // GFX9-ERR:  error: literal operands are not supported
 
 v_min3_i16 v5, 0x5678, 0x5678, 0x5679
 // GFX10-ERR: error: only one literal operand is allowed
 // GFX9-ERR:  error: literal operands are not supported
 
 v_add_nc_u16 v5, 0xfe0b, v2
-// GFX10: v_add_nc_u16_e64 v5, 0xfe0b, v2 ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x0b,0xfe,0x00,0x00]
+// GFX10: v_add_nc_u16 v5, 0xfe0b, v2 ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x0b,0xfe,0x00,0x00]
 // GFX9-ERR: error: instruction not supported on this GPU
 
 v_add_nc_u16 v5, v1, 0x1234
-// GFX10: v_add_nc_u16_e64 v5, v1, 0x1234 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x34,0x12,0x00,0x00]
+// GFX10: v_add_nc_u16 v5, v1, 0x1234 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x34,0x12,0x00,0x00]
 // GFX9-ERR: error: instruction not supported on this GPU
 
 v_add_nc_u16 v5, 0x1234, 0x1234
-// GFX10: v_add_nc_u16_e64 v5, 0x1234, 0x1234 ; encoding: [0x05,0x00,0x03,0xd7,0xff,0xfe,0x01,0x00,0x34,0x12,0x00,0x00]
+// GFX10: v_add_nc_u16 v5, 0x1234, 0x1234 ; encoding: [0x05,0x00,0x03,0xd7,0xff,0xfe,0x01,0x00,0x34,0x12,0x00,0x00]
 // GFX9-ERR: error: instruction not supported on this GPU
 
 v_ashrrev_i16_e64 v5, 0x3456, v2
-// GFX10: v_ashrrev_i16_e64 v5, 0x3456, v2 ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x56,0x34,0x00,0x00]
+// GFX10: v_ashrrev_i16 v5, 0x3456, v2 ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x56,0x34,0x00,0x00]
 // GFX9-ERR: error: literal operands are not supported
 
 v_mad_u16 v5, 0xfe0b, v2, v3
 // GFX10: v_mad_u16 v5, 0xfe0b, v2, v3    ; encoding: [0x05,0x00,0x40,0xd7,0xff,0x04,0x0e,0x04,0x0b,0xfe,0x00,0x00]
 // GFX9-ERR: error: literal operands are not supported
 
 v_mad_u16 v5, v1, 0x1234, v3
 // GFX10: v_mad_u16 v5, v1, 0x1234, v3    ; encoding: [0x05,0x00,0x40,0xd7,0x01,0xff,0x0d,0x04,0x34,0x12,0x00,0x00]

llvm/test/MC/AMDGPU/wave32.s

 // GFX1032: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:1: error: operands are not valid for this GPU or mode
 
 v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // GFX1032-ERR: :[[@LINE-1]]:1: error: operands are not valid for this GPU or mode
 // GFX1064: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
 
 v_add_co_u32 v0, s0, v0, v2
-// GFX1032: v_add_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX1032: v_add_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:26: error: invalid operand for instruction
 
 v_add_co_u32_e64 v0, s0, v0, v2
-// GFX1032: v_add_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX1032: v_add_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:30: error: invalid operand for instruction
 
 v_add_co_ci_u32_e64 v4, s0, v1, v5, s2
 // GFX1032: v_add_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding: [0x04,0x00,0x28,0xd5,0x01,0x0b,0x0a,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction
 
 v_sub_co_u32 v0, s0, v0, v2
-// GFX1032: v_sub_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX1032: v_sub_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:26: error: invalid operand for instruction
 
 v_sub_co_u32_e64 v0, s0, v0, v2
-// GFX1032: v_sub_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX1032: v_sub_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:30: error: invalid operand for instruction
 
 v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2
 // GFX1032: v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding: [0x04,0x00,0x29,0xd5,0x01,0x0b,0x0a,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:25: error: invalid operand for instruction
 
 v_subrev_co_u32 v0, s0, v0, v2
-// GFX1032: v_subrev_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX1032: v_subrev_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:29: error: invalid operand for instruction
 
 v_subrev_co_u32_e64 v0, s0, v0, v2
-// GFX1032: v_subrev_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX1032: v_subrev_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:33: error: invalid operand for instruction
 
 v_subrev_co_ci_u32_e64 v4, s0, v1, v5, s2
 // GFX1032: v_subrev_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding: [0x04,0x00,0x2a,0xd5,0x01,0x0b,0x0a,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:28: error: invalid operand for instruction
 
 v_add_co_u32 v0, s[0:1], v0, v2
 // GFX1032-ERR: :[[@LINE-1]]:18: error: invalid operand for instruction
-// GFX1064: v_add_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX1064: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
 
 v_add_co_u32_e64 v0, s[0:1], v0, v2
 // GFX1032-ERR: :[[@LINE-1]]:22: error: invalid operand for instruction
-// GFX1064: v_add_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX1064: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
 
 v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
 // GFX1032-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
 // GFX1064: v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding: [0x04,0x00,0x28,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_sub_co_u32 v0, s[0:1], v0, v2
 // GFX1032-ERR: :[[@LINE-1]]:18: error: invalid operand for instruction
-// GFX1064: v_sub_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX1064: v_sub_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
 
 v_sub_co_u32_e64 v0, s[0:1], v0, v2
 // GFX1032-ERR: :[[@LINE-1]]:22: error: invalid operand for instruction
-// GFX1064: v_sub_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX1064: v_sub_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
 
 v_sub_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
 // GFX1032-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
 // GFX1064: v_sub_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding: [0x04,0x00,0x29,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_subrev_co_u32 v0, s[0:1], v0, v2
 // GFX1032-ERR: :[[@LINE-1]]:21: error: invalid operand for instruction
-// GFX1064: v_subrev_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX1064: v_subrev_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
 
 v_subrev_co_u32_e64 v0, s[0:1], v0, v2
 // GFX1032-ERR: :[[@LINE-1]]:25: error: invalid operand for instruction
-// GFX1064: v_subrev_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX1064: v_subrev_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
 
 v_subrev_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
 // GFX1032-ERR: :[[@LINE-1]]:28: error: invalid operand for instruction
 // GFX1064: v_subrev_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding: [0x04,0x00,0x2a,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_add_co_ci_u32_e64 v4, vcc_lo, v1, v5, s2
 // GFX1032: v_add_co_ci_u32_e64 v4, vcc_lo, v1, v5, s2 ; encoding: [0x04,0x6a,0x28,0xd5,0x01,0x0b,0x0a,0x00]
 // GFX1064-ERR: :[[@LINE-2]]:41: error: invalid operand for instruction

llvm/test/MC/AMDGPU/wave_any.s

 
 v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // GFX10: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
 
 v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 // GFX10: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00]
 
 v_add_co_u32 v0, s0, v0, v2
-// GFX10: v_add_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
 
 v_add_co_u32_e64 v0, s0, v0, v2
-// GFX10: v_add_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
 
 v_add_co_ci_u32_e64 v4, s0, v1, v5, s2
 // GFX10: v_add_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding: [0x04,0x00,0x28,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_sub_co_u32 v0, s0, v0, v2
-// GFX10: v_sub_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_sub_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
 
 v_sub_co_u32_e64 v0, s0, v0, v2
-// GFX10: v_sub_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_sub_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
 
 v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2
 // GFX10: v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding: [0x04,0x00,0x29,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_subrev_co_u32 v0, s0, v0, v2
-// GFX10: v_subrev_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_subrev_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
 
 v_subrev_co_u32_e64 v0, s0, v0, v2
-// GFX10: v_subrev_co_u32_e64 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_subrev_co_u32 v0, s0, v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
 
 v_subrev_co_ci_u32_e64 v4, s0, v1, v5, s2
 // GFX10: v_subrev_co_ci_u32_e64 v4, s0, v1, v5, s2 ; encoding: [0x04,0x00,0x2a,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_add_co_u32 v0, s[0:1], v0, v2
-// GFX10: v_add_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
 
 v_add_co_u32 v0, exec, v0, v2
-// GFX10: v_add_co_u32_e64 v0, exec, v0, v2 ; encoding: [0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, exec, v0, v2 ; encoding: [0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
 
 v_add_co_u32 v0, exec_lo, v0, v2
-// GFX10: v_add_co_u32_e64 v0, exec_lo, v0, v2 ; encoding: [0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, exec_lo, v0, v2 ; encoding: [0x00,0x7e,0x0f,0xd7,0x00,0x05,0x02,0x00]
 
 v_add_co_u32_e64 v0, s[0:1], v0, v2
-// GFX10: v_add_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_add_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00]
 
 v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
 // GFX10: v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding: [0x04,0x00,0x28,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_sub_co_u32 v0, s[0:1], v0, v2
-// GFX10: v_sub_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_sub_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
 
 v_sub_co_u32_e64 v0, s[0:1], v0, v2
-// GFX10: v_sub_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_sub_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00]
 
 v_sub_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
 // GFX10: v_sub_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding: [0x04,0x00,0x29,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_subrev_co_u32 v0, s[0:1], v0, v2
-// GFX10: v_subrev_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_subrev_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
 
 v_subrev_co_u32_e64 v0, s[0:1], v0, v2
-// GFX10: v_subrev_co_u32_e64 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
+// GFX10: v_subrev_co_u32 v0, s[0:1], v0, v2 ; encoding: [0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00]
 
 v_subrev_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
 // GFX10: v_subrev_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3] ; encoding: [0x04,0x00,0x2a,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_add_co_ci_u32_e64 v4, vcc_lo, v1, v5, s2
 // GFX10: v_add_co_ci_u32_e64 v4, vcc_lo, v1, v5, s2 ; encoding: [0x04,0x6a,0x28,0xd5,0x01,0x0b,0x0a,0x00]
 
 v_add_co_ci_u32_e64 v4, vcc, v1, v5, s[2:3]

llvm/test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt

 # W32: v_add_co_ci_u32_sdwa v5, vcc_lo, v1, v255, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
 # W64: v_add_co_ci_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06]
 0xf9,0xfe,0x0b,0x50,0x01,0x06,0x06,0x06
 
 # W32: v_add_co_ci_u32_sdwa v5, vcc_lo, v255, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
 # W64: v_add_co_ci_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x50,0xff,0x06,0x06,0x06
 
-# W32: v_add_co_u32_e64 v255, s0, v1, v2       ; encoding: [0xff,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
-# W64: v_add_co_u32_e64 v255, s[0:1], v1, v2   ; encoding: [0xff,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
+# W32: v_add_co_u32 v255, s0, v1, v2           ; encoding: [0xff,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
+# W64: v_add_co_u32 v255, s[0:1], v1, v2       ; encoding: [0xff,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, -1, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0xc1,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], -1, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0xc1,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, -1, v2             ; encoding: [0x05,0x00,0x0f,0xd7,0xc1,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], -1, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0xc1,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, -4.0, v2       ; encoding: [0x05,0x00,0x0f,0xd7,0xf7,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], -4.0, v2   ; encoding: [0x05,0x00,0x0f,0xd7,0xf7,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, -4.0, v2           ; encoding: [0x05,0x00,0x0f,0xd7,0xf7,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], -4.0, v2       ; encoding: [0x05,0x00,0x0f,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0xf7,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, 0, v2          ; encoding: [0x05,0x00,0x0f,0xd7,0x80,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], 0, v2      ; encoding: [0x05,0x00,0x0f,0xd7,0x80,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, 0, v2              ; encoding: [0x05,0x00,0x0f,0xd7,0x80,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], 0, v2          ; encoding: [0x05,0x00,0x0f,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x80,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, 0.5, v2        ; encoding: [0x05,0x00,0x0f,0xd7,0xf0,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], 0.5, v2    ; encoding: [0x05,0x00,0x0f,0xd7,0xf0,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, 0.5, v2            ; encoding: [0x05,0x00,0x0f,0xd7,0xf0,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], 0.5, v2        ; encoding: [0x05,0x00,0x0f,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0xf0,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, exec_hi, v2    ; encoding: [0x05,0x00,0x0f,0xd7,0x7f,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], exec_hi, v2 ; encoding: [0x05,0x00,0x0f,0xd7,0x7f,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, exec_hi, v2        ; encoding: [0x05,0x00,0x0f,0xd7,0x7f,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], exec_hi, v2    ; encoding: [0x05,0x00,0x0f,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x7f,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, exec_lo, v2    ; encoding: [0x05,0x00,0x0f,0xd7,0x7e,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], exec_lo, v2 ; encoding: [0x05,0x00,0x0f,0xd7,0x7e,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, exec_lo, v2        ; encoding: [0x05,0x00,0x0f,0xd7,0x7e,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], exec_lo, v2    ; encoding: [0x05,0x00,0x0f,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x7e,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, m0, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0x7c,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], m0, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0x7c,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, m0, v2             ; encoding: [0x05,0x00,0x0f,0xd7,0x7c,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], m0, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x7c,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, s1, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], s1, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, s1, v2             ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], s1, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, s103, v2       ; encoding: [0x05,0x00,0x0f,0xd7,0x67,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], s103, v2   ; encoding: [0x05,0x00,0x0f,0xd7,0x67,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, s103, v2           ; encoding: [0x05,0x00,0x0f,0xd7,0x67,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], s103, v2       ; encoding: [0x05,0x00,0x0f,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x67,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, ttmp11, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0x77,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], ttmp11, v2 ; encoding: [0x05,0x00,0x0f,0xd7,0x77,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, ttmp11, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0x77,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], ttmp11, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x77,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, -1         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x83,0x01,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, -1     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x83,0x01,0x00]
+# W32: v_add_co_u32 v5, s0, v1, -1             ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x83,0x01,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, -1         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0x83,0x01,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, -4.0       ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x01,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, -4.0   ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x01,0x00]
+# W32: v_add_co_u32 v5, s0, v1, -4.0           ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x01,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, -4.0       ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xef,0x01,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, 0          ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x01,0x01,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, 0      ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x01,0x01,0x00]
+# W32: v_add_co_u32 v5, s0, v1, 0              ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x01,0x01,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, 0          ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0x01,0x01,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, 0.5        ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xe1,0x01,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, 0.5    ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xe1,0x01,0x00]
+# W32: v_add_co_u32 v5, s0, v1, 0.5            ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xe1,0x01,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, 0.5        ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xe1,0x01,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, exec_hi    ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x00,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, exec_hi ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x00,0x00]
+# W32: v_add_co_u32 v5, s0, v1, exec_hi        ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x00,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, exec_hi    ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xff,0x00,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, exec_lo    ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xfd,0x00,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, exec_lo ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xfd,0x00,0x00]
+# W32: v_add_co_u32 v5, s0, v1, exec_lo        ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xfd,0x00,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, exec_lo    ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xfd,0x00,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, m0         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xf9,0x00,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, m0     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xf9,0x00,0x00]
+# W32: v_add_co_u32 v5, s0, v1, m0             ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xf9,0x00,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, m0         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xf9,0x00,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, s103       ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xcf,0x00,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, s103   ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xcf,0x00,0x00]
+# W32: v_add_co_u32 v5, s0, v1, s103           ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xcf,0x00,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, s103       ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xcf,0x00,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, s2         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x00,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, s2     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x00,0x00]
+# W32: v_add_co_u32 v5, s0, v1, s2             ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x00,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, s2         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0x05,0x00,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, ttmp11     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x00,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, ttmp11 ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x00,0x00]
+# W32: v_add_co_u32 v5, s0, v1, ttmp11         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x00,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, ttmp11     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xef,0x00,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, v1, v2             ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0x05,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, v255       ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x03,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, v255   ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x03,0x00]
+# W32: v_add_co_u32 v5, s0, v1, v255           ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x03,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, v255       ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xff,0x03,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, vcc_hi     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd7,0x00,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, vcc_hi ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd7,0x00,0x00]
+# W32: v_add_co_u32 v5, s0, v1, vcc_hi         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd7,0x00,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, vcc_hi     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xd7,0x00,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v1, vcc_lo     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd5,0x00,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v1, vcc_lo ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd5,0x00,0x00]
+# W32: v_add_co_u32 v5, s0, v1, vcc_lo         ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd5,0x00,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v1, vcc_lo     ; encoding: [0x05,0x00,0x0f,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x0f,0xd7,0x01,0xd5,0x00,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, v255, v2       ; encoding: [0x05,0x00,0x0f,0xd7,0xff,0x05,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], v255, v2   ; encoding: [0x05,0x00,0x0f,0xd7,0xff,0x05,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, v255, v2           ; encoding: [0x05,0x00,0x0f,0xd7,0xff,0x05,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], v255, v2       ; encoding: [0x05,0x00,0x0f,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0xff,0x05,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, vcc_hi, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0x6b,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], vcc_hi, v2 ; encoding: [0x05,0x00,0x0f,0xd7,0x6b,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, vcc_hi, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0x6b,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], vcc_hi, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x6b,0x04,0x02,0x00
 
-# W32: v_add_co_u32_e64 v5, s0, vcc_lo, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0x6a,0x04,0x02,0x00]
-# W64: v_add_co_u32_e64 v5, s[0:1], vcc_lo, v2 ; encoding: [0x05,0x00,0x0f,0xd7,0x6a,0x04,0x02,0x00]
+# W32: v_add_co_u32 v5, s0, vcc_lo, v2         ; encoding: [0x05,0x00,0x0f,0xd7,0x6a,0x04,0x02,0x00]
+# W64: v_add_co_u32 v5, s[0:1], vcc_lo, v2     ; encoding: [0x05,0x00,0x0f,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x0f,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_add_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x65,0x01,0xe4,0x00,0x00
 
 # GFX10: v_add_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x64,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x64,0x01,0xe4,0x10,0x00
 

 0x05,0x00,0x7f,0xd7,0x6b,0x04,0x02,0x00
 
 # GFX10: v_add_nc_i32 v5, vcc_lo, v2             ; encoding: [0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x7f,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_add_nc_i32 v1, v2, v3 clamp           ; encoding: [0x01,0x80,0x7f,0xd7,0x02,0x07,0x02,0x00]
 0x01,0x80,0x7f,0xd7,0x02,0x07,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v255, v1, v2           ; encoding: [0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_add_nc_u16 v255, v1, v2               ; encoding: [0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x03,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, -1, v2             ; encoding: [0x05,0x00,0x03,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, -1, v2                 ; encoding: [0x05,0x00,0x03,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, 0xc400, v2         ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, 0xc400, v2             ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x03,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, 0, v2              ; encoding: [0x05,0x00,0x03,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, 0, v2                  ; encoding: [0x05,0x00,0x03,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, 0x3800, v2         ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, 0x3800, v2             ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x03,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, exec_hi, v2        ; encoding: [0x05,0x00,0x03,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, exec_hi, v2            ; encoding: [0x05,0x00,0x03,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, exec_lo, v2        ; encoding: [0x05,0x00,0x03,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, exec_lo, v2            ; encoding: [0x05,0x00,0x03,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, m0, v2             ; encoding: [0x05,0x00,0x03,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, m0, v2                 ; encoding: [0x05,0x00,0x03,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, s1, v2             ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, s1, v2                 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, s101, v2           ; encoding: [0x05,0x00,0x03,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, s101, v2               ; encoding: [0x05,0x00,0x03,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, -1             ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_add_nc_u16 v5, v1, -1                 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x03,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, 0xc400         ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, v1, 0xc400             ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x03,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, 0              ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_add_nc_u16 v5, v1, 0                  ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x03,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, 0x3800         ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, v1, 0x3800             ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x03,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, exec_hi        ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, v1, exec_hi            ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x03,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, exec_lo        ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, v1, exec_lo            ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x03,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, m0             ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, v1, m0                 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x03,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, s101           ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, v1, s101               ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x03,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, s2             ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, v1, s2                 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x03,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, v2             ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, v1, v2                 ; encoding: [0x05,0x00,0x03,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, v255           ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_add_nc_u16 v5, v1, v255               ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x03,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, vcc_hi         ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, v1, vcc_hi             ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x03,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v1, vcc_lo         ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_add_nc_u16 v5, v1, vcc_lo             ; encoding: [0x05,0x00,0x03,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x03,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, v255, v2           ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, v255, v2               ; encoding: [0x05,0x00,0x03,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x03,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, vcc_hi, v2         ; encoding: [0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, vcc_hi, v2             ; encoding: [0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, vcc_lo, v2         ; encoding: [0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, vcc_lo, v2             ; encoding: [0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x03,0xd7,0x6a,0x04,0x02,0x00
 
-# GFX10: v_add_nc_u16_e64 v5, vcc_lo, v2 clamp   ; encoding: [0x05,0x80,0x03,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_add_nc_u16 v5, vcc_lo, v2 clamp       ; encoding: [0x05,0x80,0x03,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x80,0x03,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_add_nc_u32_e32 v255, v1, v2           ; encoding: [0x01,0x05,0xfe,0x4b]
 0x01,0x05,0xfe,0x4b
 
 # GFX10: v_add_nc_u32_e32 v5, -1, v2             ; encoding: [0xc1,0x04,0x0a,0x4a]
 0xc1,0x04,0x0a,0x4a
 

 0x05,0x00,0x71,0xd7,0xff,0x05,0x0e,0x04
 
 # GFX10: v_and_or_b32 v5, vcc_hi, v2, v3         ; encoding: [0x05,0x00,0x71,0xd7,0x6b,0x04,0x0e,0x04]
 0x05,0x00,0x71,0xd7,0x6b,0x04,0x0e,0x04
 
 # GFX10: v_and_or_b32 v5, vcc_lo, v2, v3         ; encoding: [0x05,0x00,0x71,0xd7,0x6a,0x04,0x0e,0x04]
 0x05,0x00,0x71,0xd7,0x6a,0x04,0x0e,0x04
 
-# GFX10: v_ashrrev_i16_e64 v255, v1, v2          ; encoding: [0xff,0x00,0x08,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_ashrrev_i16 v255, v1, v2              ; encoding: [0xff,0x00,0x08,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x08,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, -1, v2            ; encoding: [0x05,0x00,0x08,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, -1, v2                ; encoding: [0x05,0x00,0x08,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x08,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, 0xc400, v2        ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, 0xc400, v2            ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x08,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, 0, v2             ; encoding: [0x05,0x00,0x08,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, 0, v2                 ; encoding: [0x05,0x00,0x08,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x08,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, 0x3800, v2        ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, 0x3800, v2            ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x08,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, exec_hi, v2       ; encoding: [0x05,0x00,0x08,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, exec_hi, v2           ; encoding: [0x05,0x00,0x08,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x08,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, exec_lo, v2       ; encoding: [0x05,0x00,0x08,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, exec_lo, v2           ; encoding: [0x05,0x00,0x08,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x08,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, m0, v2            ; encoding: [0x05,0x00,0x08,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, m0, v2                ; encoding: [0x05,0x00,0x08,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x08,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, s1, v2            ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, s1, v2                ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x08,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, s101, v2          ; encoding: [0x05,0x00,0x08,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, s101, v2              ; encoding: [0x05,0x00,0x08,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x08,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, -1            ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, -1                ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x08,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, 0xc400        ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, 0xc400            ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x08,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, 0             ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, 0                 ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x08,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, 0x3800        ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, 0x3800            ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x08,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, exec_hi       ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, exec_hi           ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x08,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, exec_lo       ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, exec_lo           ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x08,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, m0            ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, m0                ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x08,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, s101          ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, s101              ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x08,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, s2            ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, s2                ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x08,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, v2                ; encoding: [0x05,0x00,0x08,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x08,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, v255          ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, v255              ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x08,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, vcc_hi        ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, vcc_hi            ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x08,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v1, vcc_lo        ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_ashrrev_i16 v5, v1, vcc_lo            ; encoding: [0x05,0x00,0x08,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x08,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, v255, v2          ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, v255, v2              ; encoding: [0x05,0x00,0x08,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x08,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, vcc_hi, v2        ; encoding: [0x05,0x00,0x08,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, vcc_hi, v2            ; encoding: [0x05,0x00,0x08,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x08,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_ashrrev_i16_e64 v5, vcc_lo, v2        ; encoding: [0x05,0x00,0x08,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_ashrrev_i16 v5, vcc_lo, v2            ; encoding: [0x05,0x00,0x08,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x08,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_ashrrev_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x31,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x31,0x01,0xe4,0x00,0x00
 
 # GFX10: v_ashrrev_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x30,0x01,0xe4,0x00,0x00
 

 0x05,0x00,0x01,0xd7,0xff,0x05,0x02,0x00
 
 # GFX10: v_ashrrev_i64 v[5:6], vcc_hi, v[2:3]    ; encoding: [0x05,0x00,0x01,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x01,0xd7,0x6b,0x04,0x02,0x00
 
 # GFX10: v_ashrrev_i64 v[5:6], vcc_lo, v[2:3]    ; encoding: [0x05,0x00,0x01,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x01,0xd7,0x6a,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v255, v1, v2         ; encoding: [0xff,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v255, v1, v2             ; encoding: [0xff,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x64,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, -1, v2           ; encoding: [0x05,0x00,0x64,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, -1, v2               ; encoding: [0x05,0x00,0x64,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, -4.0, v2         ; encoding: [0x05,0x00,0x64,0xd7,0xf7,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, -4.0, v2             ; encoding: [0x05,0x00,0x64,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, 0, v2            ; encoding: [0x05,0x00,0x64,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, 0, v2                ; encoding: [0x05,0x00,0x64,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, 0.5, v2          ; encoding: [0x05,0x00,0x64,0xd7,0xf0,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, 0.5, v2              ; encoding: [0x05,0x00,0x64,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, exec_hi, v2      ; encoding: [0x05,0x00,0x64,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, exec_hi, v2          ; encoding: [0x05,0x00,0x64,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, exec_lo, v2      ; encoding: [0x05,0x00,0x64,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, exec_lo, v2          ; encoding: [0x05,0x00,0x64,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, m0, v2           ; encoding: [0x05,0x00,0x64,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, m0, v2               ; encoding: [0x05,0x00,0x64,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, s1, v2           ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, s1, v2               ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, s103, v2         ; encoding: [0x05,0x00,0x64,0xd7,0x67,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, s103, v2             ; encoding: [0x05,0x00,0x64,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x67,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, ttmp11, v2       ; encoding: [0x05,0x00,0x64,0xd7,0x77,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, ttmp11, v2           ; encoding: [0x05,0x00,0x64,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x77,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, -1           ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, -1               ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x64,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, -4.0         ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xef,0x01,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, -4.0             ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, 0            ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, 0                ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x64,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, 0.5          ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xe1,0x01,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, 0.5              ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, exec_hi      ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, exec_hi          ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, exec_lo      ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, exec_lo          ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, m0           ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, m0               ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, s103         ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xcf,0x00,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, s103             ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xcf,0x00,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, s2           ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, s2               ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x64,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, ttmp11       ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xef,0x00,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, ttmp11           ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xef,0x00,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, v2           ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, v2               ; encoding: [0x05,0x00,0x64,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, v255         ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, v255             ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, vcc_hi       ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, vcc_hi           ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v1, vcc_lo       ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v1, vcc_lo           ; encoding: [0x05,0x00,0x64,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x64,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, v255, v2         ; encoding: [0x05,0x00,0x64,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, v255, v2             ; encoding: [0x05,0x00,0x64,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x64,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, vcc_hi, v2       ; encoding: [0x05,0x00,0x64,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, vcc_hi, v2           ; encoding: [0x05,0x00,0x64,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_bcnt_u32_b32_e64 v5, vcc_lo, v2       ; encoding: [0x05,0x00,0x64,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_bcnt_u32_b32 v5, vcc_lo, v2           ; encoding: [0x05,0x00,0x64,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x64,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_bfe_i32 v255, v1, v2, v3              ; encoding: [0xff,0x00,0x49,0xd5,0x01,0x05,0x0e,0x04]
 0xff,0x00,0x49,0xd5,0x01,0x05,0x0e,0x04
 
 # GFX10: v_bfe_i32 v5, -1, v2, v3                ; encoding: [0x05,0x00,0x49,0xd5,0xc1,0x04,0x0e,0x04]
 0x05,0x00,0x49,0xd5,0xc1,0x04,0x0e,0x04
 

 0x05,0x00,0x4a,0xd5,0xff,0x05,0x0e,0x04
 
 # GFX10: v_bfi_b32 v5, vcc_hi, v2, v3            ; encoding: [0x05,0x00,0x4a,0xd5,0x6b,0x04,0x0e,0x04]
 0x05,0x00,0x4a,0xd5,0x6b,0x04,0x0e,0x04
 
 # GFX10: v_bfi_b32 v5, vcc_lo, v2, v3            ; encoding: [0x05,0x00,0x4a,0xd5,0x6a,0x04,0x0e,0x04]
 0x05,0x00,0x4a,0xd5,0x6a,0x04,0x0e,0x04
 
-# GFX10: v_bfm_b32_e64 v255, v1, v2              ; encoding: [0xff,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_bfm_b32 v255, v1, v2                  ; encoding: [0xff,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x63,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, -1, v2                ; encoding: [0x05,0x00,0x63,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, -1, v2                    ; encoding: [0x05,0x00,0x63,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, -4.0, v2              ; encoding: [0x05,0x00,0x63,0xd7,0xf7,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, -4.0, v2                  ; encoding: [0x05,0x00,0x63,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, 0, v2                 ; encoding: [0x05,0x00,0x63,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, 0, v2                     ; encoding: [0x05,0x00,0x63,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, 0.5, v2               ; encoding: [0x05,0x00,0x63,0xd7,0xf0,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, 0.5, v2                   ; encoding: [0x05,0x00,0x63,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, exec_hi, v2           ; encoding: [0x05,0x00,0x63,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, exec_hi, v2               ; encoding: [0x05,0x00,0x63,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, exec_lo, v2           ; encoding: [0x05,0x00,0x63,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, exec_lo, v2               ; encoding: [0x05,0x00,0x63,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, m0, v2                ; encoding: [0x05,0x00,0x63,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, m0, v2                    ; encoding: [0x05,0x00,0x63,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, s1, v2                ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, s1, v2                    ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, s103, v2              ; encoding: [0x05,0x00,0x63,0xd7,0x67,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, s103, v2                  ; encoding: [0x05,0x00,0x63,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x67,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, ttmp11, v2            ; encoding: [0x05,0x00,0x63,0xd7,0x77,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, ttmp11, v2                ; encoding: [0x05,0x00,0x63,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x77,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, -1                ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_bfm_b32 v5, v1, -1                    ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x63,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, -4.0              ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xef,0x01,0x00]
+# GFX10: v_bfm_b32 v5, v1, -4.0                  ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, 0                 ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_bfm_b32 v5, v1, 0                     ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x63,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, 0.5               ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xe1,0x01,0x00]
+# GFX10: v_bfm_b32 v5, v1, 0.5                   ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, exec_hi           ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_bfm_b32 v5, v1, exec_hi               ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, exec_lo           ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_bfm_b32 v5, v1, exec_lo               ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, m0                ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_bfm_b32 v5, v1, m0                    ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, s103              ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xcf,0x00,0x00]
+# GFX10: v_bfm_b32 v5, v1, s103                  ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xcf,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, s2                ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_bfm_b32 v5, v1, s2                    ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x63,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, ttmp11            ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xef,0x00,0x00]
+# GFX10: v_bfm_b32 v5, v1, ttmp11                ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xef,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_bfm_b32 v5, v1, v2                    ; encoding: [0x05,0x00,0x63,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, v255              ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_bfm_b32 v5, v1, v255                  ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, vcc_hi            ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_bfm_b32 v5, v1, vcc_hi                ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v1, vcc_lo            ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_bfm_b32 v5, v1, vcc_lo                ; encoding: [0x05,0x00,0x63,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x63,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v5, v255, v2              ; encoding: [0x05,0x00,0x63,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_bfm_b32 v5, v255, v2                  ; encoding: [0x05,0x00,0x63,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x63,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, vcc_hi, v2            ; encoding: [0x05,0x00,0x63,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, vcc_hi, v2                ; encoding: [0x05,0x00,0x63,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_bfm_b32_e64 v5, vcc_lo, v2            ; encoding: [0x05,0x00,0x63,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_bfm_b32 v5, vcc_lo, v2                ; encoding: [0x05,0x00,0x63,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x63,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_bfrev_b32_dpp v255, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x70,0xfe,0x7f,0x01,0xe4,0x00,0x00]
 0xfa,0x70,0xfe,0x7f,0x01,0xe4,0x00,0x00
 
 # GFX10: v_bfrev_b32_dpp v5, v1 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x00]
 0xfa,0x70,0x0a,0x7e,0x01,0xe4,0x00,0x00
 

 0xf9,0x1c,0x0a,0x7e,0xff,0x06,0x06,0x00
 
 # GFX10: v_cvt_off_f32_i4_sdwa v5, vcc_hi dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x1c,0x0a,0x7e,0x6b,0x06,0x86,0x00]
 0xf9,0x1c,0x0a,0x7e,0x6b,0x06,0x86,0x00
 
 # GFX10: v_cvt_off_f32_i4_sdwa v5, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD ; encoding: [0xf9,0x1c,0x0a,0x7e,0x6a,0x06,0x86,0x00]
 0xf9,0x1c,0x0a,0x7e,0x6a,0x06,0x86,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v255, v1, v2       ; encoding: [0xff,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v255, v1, v2           ; encoding: [0xff,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, -1, v2         ; encoding: [0x05,0x00,0x6b,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, -1, v2             ; encoding: [0x05,0x00,0x6b,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, -4.0, v2       ; encoding: [0x05,0x00,0x6b,0xd7,0xf7,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, -4.0, v2           ; encoding: [0x05,0x00,0x6b,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, 0, v2          ; encoding: [0x05,0x00,0x6b,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, 0, v2              ; encoding: [0x05,0x00,0x6b,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, 0.5, v2        ; encoding: [0x05,0x00,0x6b,0xd7,0xf0,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, 0.5, v2            ; encoding: [0x05,0x00,0x6b,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, exec_hi, v2    ; encoding: [0x05,0x00,0x6b,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, exec_hi, v2        ; encoding: [0x05,0x00,0x6b,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, exec_lo, v2    ; encoding: [0x05,0x00,0x6b,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, exec_lo, v2        ; encoding: [0x05,0x00,0x6b,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, m0, v2         ; encoding: [0x05,0x00,0x6b,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, m0, v2             ; encoding: [0x05,0x00,0x6b,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, s1, v2         ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, s1, v2             ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, s103, v2       ; encoding: [0x05,0x00,0x6b,0xd7,0x67,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, s103, v2           ; encoding: [0x05,0x00,0x6b,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x67,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, ttmp11, v2     ; encoding: [0x05,0x00,0x6b,0xd7,0x77,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, ttmp11, v2         ; encoding: [0x05,0x00,0x6b,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x77,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, -1         ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, -1             ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, -4.0       ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xef,0x01,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, -4.0           ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, 0          ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, 0              ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, 0.5        ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xe1,0x01,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, 0.5            ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, exec_hi    ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, exec_hi        ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, exec_lo    ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, exec_lo        ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, m0         ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, m0             ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, s103       ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xcf,0x00,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, s103           ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xcf,0x00,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, s2         ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, s2             ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, ttmp11     ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xef,0x00,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, ttmp11         ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xef,0x00,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, v2         ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, v2             ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, v255       ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, v255           ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, vcc_hi     ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, vcc_hi         ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v1, vcc_lo     ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v1, vcc_lo         ; encoding: [0x05,0x00,0x6b,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x6b,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, v255, v2       ; encoding: [0x05,0x00,0x6b,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, v255, v2           ; encoding: [0x05,0x00,0x6b,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, vcc_hi, v2     ; encoding: [0x05,0x00,0x6b,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, vcc_hi, v2         ; encoding: [0x05,0x00,0x6b,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_i16_i32_e64 v5, vcc_lo, v2     ; encoding: [0x05,0x00,0x6b,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_i16_i32 v5, vcc_lo, v2         ; encoding: [0x05,0x00,0x6b,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x6b,0xd7,0x6a,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v255, v1, v2       ; encoding: [0xff,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v255, v1, v2           ; encoding: [0xff,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, -1, v2         ; encoding: [0x05,0x00,0x6a,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, -1, v2             ; encoding: [0x05,0x00,0x6a,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, -4.0, v2       ; encoding: [0x05,0x00,0x6a,0xd7,0xf7,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, -4.0, v2           ; encoding: [0x05,0x00,0x6a,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, 0, v2          ; encoding: [0x05,0x00,0x6a,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, 0, v2              ; encoding: [0x05,0x00,0x6a,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, 0.5, v2        ; encoding: [0x05,0x00,0x6a,0xd7,0xf0,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, 0.5, v2            ; encoding: [0x05,0x00,0x6a,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, exec_hi, v2    ; encoding: [0x05,0x00,0x6a,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, exec_hi, v2        ; encoding: [0x05,0x00,0x6a,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, exec_lo, v2    ; encoding: [0x05,0x00,0x6a,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, exec_lo, v2        ; encoding: [0x05,0x00,0x6a,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, m0, v2         ; encoding: [0x05,0x00,0x6a,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, m0, v2             ; encoding: [0x05,0x00,0x6a,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, s1, v2         ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, s1, v2             ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, s103, v2       ; encoding: [0x05,0x00,0x6a,0xd7,0x67,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, s103, v2           ; encoding: [0x05,0x00,0x6a,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x67,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, ttmp11, v2     ; encoding: [0x05,0x00,0x6a,0xd7,0x77,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, ttmp11, v2         ; encoding: [0x05,0x00,0x6a,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x77,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, -1         ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, -1             ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, -4.0       ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xef,0x01,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, -4.0           ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, 0          ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, 0              ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, 0.5        ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xe1,0x01,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, 0.5            ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, exec_hi    ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, exec_hi        ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, exec_lo    ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, exec_lo        ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, m0         ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, m0             ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, s103       ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xcf,0x00,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, s103           ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xcf,0x00,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, s2         ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, s2             ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, ttmp11     ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xef,0x00,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, ttmp11         ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xef,0x00,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, v2         ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, v2             ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, v255       ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, v255           ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, vcc_hi     ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, vcc_hi         ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v1, vcc_lo     ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v1, vcc_lo         ; encoding: [0x05,0x00,0x6a,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x6a,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, v255, v2       ; encoding: [0x05,0x00,0x6a,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, v255, v2           ; encoding: [0x05,0x00,0x6a,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, vcc_hi, v2     ; encoding: [0x05,0x00,0x6a,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, vcc_hi, v2         ; encoding: [0x05,0x00,0x6a,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_cvt_pk_u16_u32_e64 v5, vcc_lo, v2     ; encoding: [0x05,0x00,0x6a,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_cvt_pk_u16_u32 v5, vcc_lo, v2         ; encoding: [0x05,0x00,0x6a,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x6a,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_cvt_pk_u8_f32 v255, v1, v2, v3        ; encoding: [0xff,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x04]
 0xff,0x00,0x5e,0xd5,0x01,0x05,0x0e,0x04
 
 # GFX10: v_cvt_pk_u8_f32 v5, -1, v2, v3          ; encoding: [0x05,0x00,0x5e,0xd5,0xc1,0x04,0x0e,0x04]
 0x05,0x00,0x5e,0xd5,0xc1,0x04,0x0e,0x04
 

 0x05,0x00,0x12,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_cvt_pknorm_i16_f16 v5, |v1|, v2       ; encoding: [0x05,0x01,0x12,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x01,0x12,0xd7,0x01,0x05,0x02,0x00
 
 # GFX10: v_cvt_pknorm_i16_f16 v5, |v1|, |v2|     ; encoding: [0x05,0x03,0x12,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x03,0x12,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v255, v1, v2   ; encoding: [0xff,0x00,0x68,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v255, v1, v2       ; encoding: [0xff,0x00,0x68,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x68,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, -1, v2     ; encoding: [0x05,0x00,0x68,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, -1, v2         ; encoding: [0x05,0x00,0x68,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, -4.0, v2   ; encoding: [0x05,0x00,0x68,0xd7,0xf7,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, -4.0, v2       ; encoding: [0x05,0x00,0x68,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, -v1, -v2   ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x60]
+# GFX10: v_cvt_pknorm_i16_f32 v5, -v1, -v2       ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x60]
 0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x60
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, -v1, v2    ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x20]
+# GFX10: v_cvt_pknorm_i16_f32 v5, -v1, v2        ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x20]
 0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x20
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, 0, v2      ; encoding: [0x05,0x00,0x68,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, 0, v2          ; encoding: [0x05,0x00,0x68,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, 0.5, v2    ; encoding: [0x05,0x00,0x68,0xd7,0xf0,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, 0.5, v2        ; encoding: [0x05,0x00,0x68,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, exec_hi, v2 ; encoding: [0x05,0x00,0x68,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, exec_hi, v2    ; encoding: [0x05,0x00,0x68,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, exec_lo, v2 ; encoding: [0x05,0x00,0x68,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, exec_lo, v2    ; encoding: [0x05,0x00,0x68,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, m0, v2     ; encoding: [0x05,0x00,0x68,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, m0, v2         ; encoding: [0x05,0x00,0x68,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, s1, v2     ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, s1, v2         ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, s103, v2   ; encoding: [0x05,0x00,0x68,0xd7,0x67,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, s103, v2       ; encoding: [0x05,0x00,0x68,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x67,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, ttmp11, v2 ; encoding: [0x05,0x00,0x68,0xd7,0x77,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, ttmp11, v2     ; encoding: [0x05,0x00,0x68,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x77,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, -1     ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, -1         ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x68,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, -4.0   ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xef,0x01,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, -4.0       ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, -v2    ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x40]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, -v2        ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x40]
 0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x40
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, 0      ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, 0          ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x68,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, 0.5    ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xe1,0x01,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, 0.5        ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, exec_hi ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, exec_hi    ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, exec_lo ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, exec_lo    ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, m0     ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, m0         ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, s103   ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xcf,0x00,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, s103       ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xcf,0x00,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, s2     ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, s2         ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x68,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, ttmp11 ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xef,0x00,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, ttmp11     ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xef,0x00,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, v2     ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, v2         ; encoding: [0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, v2 clamp ; encoding: [0x05,0x80,0x68,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, v2 clamp   ; encoding: [0x05,0x80,0x68,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x80,0x68,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, v255   ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, v255       ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, vcc_hi ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, vcc_hi     ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, vcc_lo ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, vcc_lo     ; encoding: [0x05,0x00,0x68,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x68,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v1, |v2|   ; encoding: [0x05,0x02,0x68,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v1, |v2|       ; encoding: [0x05,0x02,0x68,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x02,0x68,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, v255, v2   ; encoding: [0x05,0x00,0x68,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, v255, v2       ; encoding: [0x05,0x00,0x68,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x68,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x68,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, vcc_hi, v2     ; encoding: [0x05,0x00,0x68,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x68,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, vcc_lo, v2     ; encoding: [0x05,0x00,0x68,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd7,0x6a,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, |v1|, v2   ; encoding: [0x05,0x01,0x68,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, |v1|, v2       ; encoding: [0x05,0x01,0x68,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x01,0x68,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_i16_f32_e64 v5, |v1|, |v2| ; encoding: [0x05,0x03,0x68,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_i16_f32 v5, |v1|, |v2|     ; encoding: [0x05,0x03,0x68,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x03,0x68,0xd7,0x01,0x05,0x02,0x00
 
 # GFX10: v_cvt_pknorm_u16_f16 v255, v1, v2       ; encoding: [0xff,0x00,0x13,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x13,0xd7,0x01,0x05,0x02,0x00
 
 # GFX10: v_cvt_pknorm_u16_f16 v5, -1, v2         ; encoding: [0x05,0x00,0x13,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x13,0xd7,0xc1,0x04,0x02,0x00
 

 0x05,0x00,0x13,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_cvt_pknorm_u16_f16 v5, |v1|, v2       ; encoding: [0x05,0x01,0x13,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x01,0x13,0xd7,0x01,0x05,0x02,0x00
 
 # GFX10: v_cvt_pknorm_u16_f16 v5, |v1|, |v2|     ; encoding: [0x05,0x03,0x13,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x03,0x13,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v255, v1, v2   ; encoding: [0xff,0x00,0x69,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v255, v1, v2       ; encoding: [0xff,0x00,0x69,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x69,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, -1, v2     ; encoding: [0x05,0x00,0x69,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, -1, v2         ; encoding: [0x05,0x00,0x69,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, -4.0, v2   ; encoding: [0x05,0x00,0x69,0xd7,0xf7,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, -4.0, v2       ; encoding: [0x05,0x00,0x69,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, -v1, -v2   ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x60]
+# GFX10: v_cvt_pknorm_u16_f32 v5, -v1, -v2       ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x60]
 0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x60
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, -v1, v2    ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x20]
+# GFX10: v_cvt_pknorm_u16_f32 v5, -v1, v2        ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x20]
 0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x20
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, 0, v2      ; encoding: [0x05,0x00,0x69,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, 0, v2          ; encoding: [0x05,0x00,0x69,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, 0.5, v2    ; encoding: [0x05,0x00,0x69,0xd7,0xf0,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, 0.5, v2        ; encoding: [0x05,0x00,0x69,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, exec_hi, v2 ; encoding: [0x05,0x00,0x69,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, exec_hi, v2    ; encoding: [0x05,0x00,0x69,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, exec_lo, v2 ; encoding: [0x05,0x00,0x69,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, exec_lo, v2    ; encoding: [0x05,0x00,0x69,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, m0, v2     ; encoding: [0x05,0x00,0x69,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, m0, v2         ; encoding: [0x05,0x00,0x69,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, s1, v2     ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, s1, v2         ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, s103, v2   ; encoding: [0x05,0x00,0x69,0xd7,0x67,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, s103, v2       ; encoding: [0x05,0x00,0x69,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x67,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, ttmp11, v2 ; encoding: [0x05,0x00,0x69,0xd7,0x77,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, ttmp11, v2     ; encoding: [0x05,0x00,0x69,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x77,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, -1     ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, -1         ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x69,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, -4.0   ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xef,0x01,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, -4.0       ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, -v2    ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x40]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, -v2        ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x40]
 0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x40
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, 0      ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, 0          ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x69,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, 0.5    ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xe1,0x01,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, 0.5        ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, exec_hi ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, exec_hi    ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, exec_lo ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, exec_lo    ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, m0     ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, m0         ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, s103   ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xcf,0x00,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, s103       ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xcf,0x00,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, s2     ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, s2         ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x69,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, ttmp11 ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xef,0x00,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, ttmp11     ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xef,0x00,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, v2     ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, v2         ; encoding: [0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, v2 clamp ; encoding: [0x05,0x80,0x69,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, v2 clamp   ; encoding: [0x05,0x80,0x69,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x80,0x69,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, v255   ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, v255       ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, vcc_hi ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, vcc_hi     ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, vcc_lo ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, vcc_lo     ; encoding: [0x05,0x00,0x69,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x69,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v1, |v2|   ; encoding: [0x05,0x02,0x69,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v1, |v2|       ; encoding: [0x05,0x02,0x69,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x02,0x69,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, v255, v2   ; encoding: [0x05,0x00,0x69,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, v255, v2       ; encoding: [0x05,0x00,0x69,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x69,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0x69,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, vcc_hi, v2     ; encoding: [0x05,0x00,0x69,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0x69,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, vcc_lo, v2     ; encoding: [0x05,0x00,0x69,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd7,0x6a,0x04,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, |v1|, v2   ; encoding: [0x05,0x01,0x69,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, |v1|, v2       ; encoding: [0x05,0x01,0x69,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x01,0x69,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_cvt_pknorm_u16_f32_e64 v5, |v1|, |v2| ; encoding: [0x05,0x03,0x69,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_cvt_pknorm_u16_f32 v5, |v1|, |v2|     ; encoding: [0x05,0x03,0x69,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x03,0x69,0xd7,0x01,0x05,0x02,0x00
 
 # GFX10: v_cvt_pkrtz_f16_f32_e32 v255, v1, v2    ; encoding: [0x01,0x05,0xfe,0x5f]
 0x01,0x05,0xfe,0x5f
 
 # GFX10: v_cvt_pkrtz_f16_f32_e32 v5, -1, v2      ; encoding: [0xc1,0x04,0x0a,0x5e]
 0xc1,0x04,0x0a,0x5e
 

 0xf9,0x04,0x0a,0x76,0x6b,0x06,0x86,0x06
 
 # GFX10: v_ldexp_f16_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x76,0x6a,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x76,0x6a,0x06,0x86,0x06
 
 # GFX10: v_ldexp_f16_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x76,0x01,0x06,0x26,0x06]
 0xf9,0x04,0x0a,0x76,0x01,0x06,0x26,0x06
 
-# GFX10: v_ldexp_f32_e64 v255, v1, v2            ; encoding: [0xff,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_ldexp_f32 v255, v1, v2                ; encoding: [0xff,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x62,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, -1, v2              ; encoding: [0x05,0x00,0x62,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, -1, v2                  ; encoding: [0x05,0x00,0x62,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, -4.0, v2            ; encoding: [0x05,0x00,0x62,0xd7,0xf7,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, -4.0, v2                ; encoding: [0x05,0x00,0x62,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, -v1, v2             ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x20]
+# GFX10: v_ldexp_f32 v5, -v1, v2                 ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x20]
 0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x20
 
-# GFX10: v_ldexp_f32_e64 v5, 0, v2               ; encoding: [0x05,0x00,0x62,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, 0, v2                   ; encoding: [0x05,0x00,0x62,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, 0.5, v2             ; encoding: [0x05,0x00,0x62,0xd7,0xf0,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, 0.5, v2                 ; encoding: [0x05,0x00,0x62,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, exec_hi, v2         ; encoding: [0x05,0x00,0x62,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, exec_hi, v2             ; encoding: [0x05,0x00,0x62,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, exec_lo, v2         ; encoding: [0x05,0x00,0x62,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, exec_lo, v2             ; encoding: [0x05,0x00,0x62,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, m0, v2              ; encoding: [0x05,0x00,0x62,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, m0, v2                  ; encoding: [0x05,0x00,0x62,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, s1, v2              ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, s1, v2                  ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, s103, v2            ; encoding: [0x05,0x00,0x62,0xd7,0x67,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, s103, v2                ; encoding: [0x05,0x00,0x62,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x67,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, ttmp11, v2          ; encoding: [0x05,0x00,0x62,0xd7,0x77,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, ttmp11, v2              ; encoding: [0x05,0x00,0x62,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x77,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, -1              ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_ldexp_f32 v5, v1, -1                  ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x62,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, -4.0            ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xef,0x01,0x00]
+# GFX10: v_ldexp_f32 v5, v1, -4.0                ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, 0               ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_ldexp_f32 v5, v1, 0                   ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x62,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, 0.5             ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xe1,0x01,0x00]
+# GFX10: v_ldexp_f32 v5, v1, 0.5                 ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, exec_hi         ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_ldexp_f32 v5, v1, exec_hi             ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, exec_lo         ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_ldexp_f32 v5, v1, exec_lo             ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, m0              ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_ldexp_f32 v5, v1, m0                  ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, s103            ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xcf,0x00,0x00]
+# GFX10: v_ldexp_f32 v5, v1, s103                ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xcf,0x00,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, s2              ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_ldexp_f32 v5, v1, s2                  ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x62,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, ttmp11          ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xef,0x00,0x00]
+# GFX10: v_ldexp_f32 v5, v1, ttmp11              ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xef,0x00,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, v2              ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, v1, v2                  ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, v2 clamp        ; encoding: [0x05,0x80,0x62,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, v1, v2 clamp            ; encoding: [0x05,0x80,0x62,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x80,0x62,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, v2 div:2        ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x18]
+# GFX10: v_ldexp_f32 v5, v1, v2 div:2            ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x18]
 0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x18
 
-# GFX10: v_ldexp_f32_e64 v5, v1, v2 mul:2        ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x08]
+# GFX10: v_ldexp_f32 v5, v1, v2 mul:2            ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x08]
 0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x08
 
-# GFX10: v_ldexp_f32_e64 v5, v1, v2 mul:4        ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x10]
+# GFX10: v_ldexp_f32 v5, v1, v2 mul:4            ; encoding: [0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x10]
 0x05,0x00,0x62,0xd7,0x01,0x05,0x02,0x10
 
-# GFX10: v_ldexp_f32_e64 v5, v1, v255            ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_ldexp_f32 v5, v1, v255                ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, vcc_hi          ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_ldexp_f32 v5, v1, vcc_hi              ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v1, vcc_lo          ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_ldexp_f32 v5, v1, vcc_lo              ; encoding: [0x05,0x00,0x62,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x62,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, v255, v2            ; encoding: [0x05,0x00,0x62,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, v255, v2                ; encoding: [0x05,0x00,0x62,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x62,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, vcc_hi, v2          ; encoding: [0x05,0x00,0x62,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, vcc_hi, v2              ; encoding: [0x05,0x00,0x62,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, vcc_lo, v2          ; encoding: [0x05,0x00,0x62,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, vcc_lo, v2              ; encoding: [0x05,0x00,0x62,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x62,0xd7,0x6a,0x04,0x02,0x00
 
-# GFX10: v_ldexp_f32_e64 v5, |v1|, v2            ; encoding: [0x05,0x01,0x62,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_ldexp_f32 v5, |v1|, v2                ; encoding: [0x05,0x01,0x62,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x01,0x62,0xd7,0x01,0x05,0x02,0x00
 
 # GFX10: v_ldexp_f64 v[254:255], v[1:2], v2      ; encoding: [0xfe,0x00,0x68,0xd5,0x01,0x05,0x02,0x00]
 0xfe,0x00,0x68,0xd5,0x01,0x05,0x02,0x00
 
 # GFX10: v_ldexp_f64 v[5:6], -1, v2              ; encoding: [0x05,0x00,0x68,0xd5,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x68,0xd5,0xc1,0x04,0x02,0x00
 

 0x05,0x00,0x6f,0xd7,0xff,0x05,0x0e,0x04
 
 # GFX10: v_lshl_or_b32 v5, vcc_hi, v2, v3        ; encoding: [0x05,0x00,0x6f,0xd7,0x6b,0x04,0x0e,0x04]
 0x05,0x00,0x6f,0xd7,0x6b,0x04,0x0e,0x04
 
 # GFX10: v_lshl_or_b32 v5, vcc_lo, v2, v3        ; encoding: [0x05,0x00,0x6f,0xd7,0x6a,0x04,0x0e,0x04]
 0x05,0x00,0x6f,0xd7,0x6a,0x04,0x0e,0x04
 
-# GFX10: v_lshlrev_b16_e64 v255, v1, v2          ; encoding: [0xff,0x00,0x14,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_lshlrev_b16 v255, v1, v2              ; encoding: [0xff,0x00,0x14,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x14,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, -1, v2            ; encoding: [0x05,0x00,0x14,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, -1, v2                ; encoding: [0x05,0x00,0x14,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x14,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, 0xc400, v2        ; encoding: [0x05,0x00,0x14,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, 0xc400, v2            ; encoding: [0x05,0x00,0x14,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x14,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, 0, v2             ; encoding: [0x05,0x00,0x14,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, 0, v2                 ; encoding: [0x05,0x00,0x14,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x14,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, 0x3800, v2        ; encoding: [0x05,0x00,0x14,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, 0x3800, v2            ; encoding: [0x05,0x00,0x14,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x14,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, exec_hi, v2       ; encoding: [0x05,0x00,0x14,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, exec_hi, v2           ; encoding: [0x05,0x00,0x14,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x14,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, exec_lo, v2       ; encoding: [0x05,0x00,0x14,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, exec_lo, v2           ; encoding: [0x05,0x00,0x14,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x14,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, m0, v2            ; encoding: [0x05,0x00,0x14,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, m0, v2                ; encoding: [0x05,0x00,0x14,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x14,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, s1, v2            ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, s1, v2                ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x14,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, s101, v2          ; encoding: [0x05,0x00,0x14,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, s101, v2              ; encoding: [0x05,0x00,0x14,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x14,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, -1            ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, -1                ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x14,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, 0xc400        ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, 0xc400            ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x14,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, 0             ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, 0                 ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x14,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, 0x3800        ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, 0x3800            ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x14,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, exec_hi       ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, exec_hi           ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x14,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, exec_lo       ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, exec_lo           ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x14,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, m0            ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, m0                ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x14,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, s101          ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, s101              ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x14,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, s2            ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, s2                ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x14,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, v2                ; encoding: [0x05,0x00,0x14,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x14,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, v255          ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, v255              ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x14,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, vcc_hi        ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, vcc_hi            ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x14,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v1, vcc_lo        ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_lshlrev_b16 v5, v1, vcc_lo            ; encoding: [0x05,0x00,0x14,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x14,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, v255, v2          ; encoding: [0x05,0x00,0x14,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, v255, v2              ; encoding: [0x05,0x00,0x14,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x14,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, vcc_hi, v2        ; encoding: [0x05,0x00,0x14,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, vcc_hi, v2            ; encoding: [0x05,0x00,0x14,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x14,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_lshlrev_b16_e64 v5, vcc_lo, v2        ; encoding: [0x05,0x00,0x14,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_lshlrev_b16 v5, vcc_lo, v2            ; encoding: [0x05,0x00,0x14,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x14,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_lshlrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x35,0x01,0xe4,0x00,0x00
 
 # GFX10: v_lshlrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x34,0x01,0xe4,0x00,0x00
 

 0x05,0x00,0xff,0xd6,0xff,0x05,0x02,0x00
 
 # GFX10: v_lshlrev_b64 v[5:6], vcc_hi, v[2:3]    ; encoding: [0x05,0x00,0xff,0xd6,0x6b,0x04,0x02,0x00]
 0x05,0x00,0xff,0xd6,0x6b,0x04,0x02,0x00
 
 # GFX10: v_lshlrev_b64 v[5:6], vcc_lo, v[2:3]    ; encoding: [0x05,0x00,0xff,0xd6,0x6a,0x04,0x02,0x00]
 0x05,0x00,0xff,0xd6,0x6a,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v255, v1, v2          ; encoding: [0xff,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_lshrrev_b16 v255, v1, v2              ; encoding: [0xff,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x07,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, -1, v2            ; encoding: [0x05,0x00,0x07,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, -1, v2                ; encoding: [0x05,0x00,0x07,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x07,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, 0xc400, v2        ; encoding: [0x05,0x00,0x07,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, 0xc400, v2            ; encoding: [0x05,0x00,0x07,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x07,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, 0, v2             ; encoding: [0x05,0x00,0x07,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, 0, v2                 ; encoding: [0x05,0x00,0x07,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x07,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, 0x3800, v2        ; encoding: [0x05,0x00,0x07,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, 0x3800, v2            ; encoding: [0x05,0x00,0x07,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x07,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, exec_hi, v2       ; encoding: [0x05,0x00,0x07,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, exec_hi, v2           ; encoding: [0x05,0x00,0x07,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x07,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, exec_lo, v2       ; encoding: [0x05,0x00,0x07,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, exec_lo, v2           ; encoding: [0x05,0x00,0x07,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x07,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, m0, v2            ; encoding: [0x05,0x00,0x07,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, m0, v2                ; encoding: [0x05,0x00,0x07,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x07,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, s1, v2            ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, s1, v2                ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x07,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, s101, v2          ; encoding: [0x05,0x00,0x07,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, s101, v2              ; encoding: [0x05,0x00,0x07,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x07,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, -1            ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, -1                ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x07,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, 0xc400        ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, 0xc400            ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x07,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, 0             ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, 0                 ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x07,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, 0x3800        ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, 0x3800            ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x07,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, exec_hi       ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, exec_hi           ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x07,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, exec_lo       ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, exec_lo           ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x07,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, m0            ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, m0                ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x07,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, s101          ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, s101              ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x07,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, s2            ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, s2                ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x07,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, v2            ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, v2                ; encoding: [0x05,0x00,0x07,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x07,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, v255          ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, v255              ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x07,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, vcc_hi        ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, vcc_hi            ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x07,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v1, vcc_lo        ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_lshrrev_b16 v5, v1, vcc_lo            ; encoding: [0x05,0x00,0x07,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x07,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, v255, v2          ; encoding: [0x05,0x00,0x07,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, v255, v2              ; encoding: [0x05,0x00,0x07,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x07,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, vcc_hi, v2        ; encoding: [0x05,0x00,0x07,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, vcc_hi, v2            ; encoding: [0x05,0x00,0x07,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x07,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_lshrrev_b16_e64 v5, vcc_lo, v2        ; encoding: [0x05,0x00,0x07,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_lshrrev_b16 v5, vcc_lo, v2            ; encoding: [0x05,0x00,0x07,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x07,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_lshrrev_b32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x2d,0x01,0xe4,0x00,0x00
 
 # GFX10: v_lshrrev_b32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x2c,0x01,0xe4,0x00,0x00
 

 0x05,0x00,0x67,0xd5,0x6a,0x04,0x02,0x00
 
 # GFX10: v_max_f64 v[5:6], |v[1:2]|, v[2:3]      ; encoding: [0x05,0x01,0x67,0xd5,0x01,0x05,0x02,0x00]
 0x05,0x01,0x67,0xd5,0x01,0x05,0x02,0x00
 
 # GFX10: v_max_f64 v[5:6], |v[1:2]|, |v[2:3]|    ; encoding: [0x05,0x03,0x67,0xd5,0x01,0x05,0x02,0x00]
 0x05,0x03,0x67,0xd5,0x01,0x05,0x02,0x00
 
-# GFX10: v_max_i16_e64 v255, v1, v2              ; encoding: [0xff,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_max_i16 v255, v1, v2                  ; encoding: [0xff,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, -1, v2                ; encoding: [0x05,0x00,0x0a,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_max_i16 v5, -1, v2                    ; encoding: [0x05,0x00,0x0a,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, 0xc400, v2            ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_max_i16 v5, 0xc400, v2                ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, 0, v2                 ; encoding: [0x05,0x00,0x0a,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_max_i16 v5, 0, v2                     ; encoding: [0x05,0x00,0x0a,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, 0x3800, v2            ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_max_i16 v5, 0x3800, v2                ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, exec_hi, v2           ; encoding: [0x05,0x00,0x0a,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_max_i16 v5, exec_hi, v2               ; encoding: [0x05,0x00,0x0a,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, exec_lo, v2           ; encoding: [0x05,0x00,0x0a,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_max_i16 v5, exec_lo, v2               ; encoding: [0x05,0x00,0x0a,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, m0, v2                ; encoding: [0x05,0x00,0x0a,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_max_i16 v5, m0, v2                    ; encoding: [0x05,0x00,0x0a,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, s1, v2                ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_max_i16 v5, s1, v2                    ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, s101, v2              ; encoding: [0x05,0x00,0x0a,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_max_i16 v5, s101, v2                  ; encoding: [0x05,0x00,0x0a,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, -1                ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_max_i16 v5, v1, -1                    ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, 0xc400            ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_max_i16 v5, v1, 0xc400                ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, 0                 ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_max_i16 v5, v1, 0                     ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, 0x3800            ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_max_i16 v5, v1, 0x3800                ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, exec_hi           ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_max_i16 v5, v1, exec_hi               ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, exec_lo           ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_max_i16 v5, v1, exec_lo               ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, m0                ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_max_i16 v5, v1, m0                    ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, s101              ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_max_i16 v5, v1, s101                  ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, s2                ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_max_i16 v5, v1, s2                    ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_max_i16 v5, v1, v2                    ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, v255              ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_max_i16 v5, v1, v255                  ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, vcc_hi            ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_max_i16 v5, v1, vcc_hi                ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_max_i16_e64 v5, v1, vcc_lo            ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_max_i16 v5, v1, vcc_lo                ; encoding: [0x05,0x00,0x0a,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x0a,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_max_i16_e64 v5, v255, v2              ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_max_i16 v5, v255, v2                  ; encoding: [0x05,0x00,0x0a,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, vcc_hi, v2            ; encoding: [0x05,0x00,0x0a,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_max_i16 v5, vcc_hi, v2                ; encoding: [0x05,0x00,0x0a,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_max_i16_e64 v5, vcc_lo, v2            ; encoding: [0x05,0x00,0x0a,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_max_i16 v5, vcc_lo, v2                ; encoding: [0x05,0x00,0x0a,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x0a,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_max_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x25,0x01,0xe4,0x00,0x00
 
 # GFX10: v_max_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x24,0x01,0xe4,0x00,0x00
 

 0xf9,0x04,0x0a,0x24,0xff,0x06,0x06,0x06
 
 # GFX10: v_max_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x24,0x6b,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x24,0x6b,0x06,0x86,0x06
 
 # GFX10: v_max_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x24,0x6a,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x24,0x6a,0x06,0x86,0x06
 
-# GFX10: v_max_u16_e64 v255, v1, v2              ; encoding: [0xff,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_max_u16 v255, v1, v2                  ; encoding: [0xff,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x09,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, -1, v2                ; encoding: [0x05,0x00,0x09,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_max_u16 v5, -1, v2                    ; encoding: [0x05,0x00,0x09,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x09,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, 0xc400, v2            ; encoding: [0x05,0x00,0x09,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_max_u16 v5, 0xc400, v2                ; encoding: [0x05,0x00,0x09,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x09,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, 0, v2                 ; encoding: [0x05,0x00,0x09,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_max_u16 v5, 0, v2                     ; encoding: [0x05,0x00,0x09,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x09,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, 0x3800, v2            ; encoding: [0x05,0x00,0x09,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_max_u16 v5, 0x3800, v2                ; encoding: [0x05,0x00,0x09,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x09,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, exec_hi, v2           ; encoding: [0x05,0x00,0x09,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_max_u16 v5, exec_hi, v2               ; encoding: [0x05,0x00,0x09,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x09,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, exec_lo, v2           ; encoding: [0x05,0x00,0x09,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_max_u16 v5, exec_lo, v2               ; encoding: [0x05,0x00,0x09,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x09,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, m0, v2                ; encoding: [0x05,0x00,0x09,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_max_u16 v5, m0, v2                    ; encoding: [0x05,0x00,0x09,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x09,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, s1, v2                ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_max_u16 v5, s1, v2                    ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x09,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, s101, v2              ; encoding: [0x05,0x00,0x09,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_max_u16 v5, s101, v2                  ; encoding: [0x05,0x00,0x09,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x09,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, -1                ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_max_u16 v5, v1, -1                    ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x09,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, 0xc400            ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_max_u16 v5, v1, 0xc400                ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x09,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, 0                 ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_max_u16 v5, v1, 0                     ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x09,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, 0x3800            ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_max_u16 v5, v1, 0x3800                ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x09,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, exec_hi           ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_max_u16 v5, v1, exec_hi               ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x09,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, exec_lo           ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_max_u16 v5, v1, exec_lo               ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x09,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, m0                ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_max_u16 v5, v1, m0                    ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x09,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, s101              ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_max_u16 v5, v1, s101                  ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x09,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, s2                ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_max_u16 v5, v1, s2                    ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x09,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_max_u16 v5, v1, v2                    ; encoding: [0x05,0x00,0x09,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x09,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, v255              ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_max_u16 v5, v1, v255                  ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x09,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, vcc_hi            ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_max_u16 v5, v1, vcc_hi                ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x09,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_max_u16_e64 v5, v1, vcc_lo            ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_max_u16 v5, v1, vcc_lo                ; encoding: [0x05,0x00,0x09,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x09,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_max_u16_e64 v5, v255, v2              ; encoding: [0x05,0x00,0x09,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_max_u16 v5, v255, v2                  ; encoding: [0x05,0x00,0x09,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x09,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, vcc_hi, v2            ; encoding: [0x05,0x00,0x09,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_max_u16 v5, vcc_hi, v2                ; encoding: [0x05,0x00,0x09,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x09,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_max_u16_e64 v5, vcc_lo, v2            ; encoding: [0x05,0x00,0x09,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_max_u16 v5, vcc_lo, v2                ; encoding: [0x05,0x00,0x09,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x09,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_max_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x29,0x01,0xe4,0x00,0x00
 
 # GFX10: v_max_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x28,0x01,0xe4,0x00,0x00
 

 0xf9,0x04,0x0a,0x28,0xff,0x06,0x06,0x06
 
 # GFX10: v_max_u32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x28,0x6b,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x28,0x6b,0x06,0x86,0x06
 
 # GFX10: v_max_u32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x28,0x6a,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x28,0x6a,0x06,0x86,0x06
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v255, v1, v2     ; encoding: [0xff,0x00,0x66,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v255, v1, v2         ; encoding: [0xff,0x00,0x66,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x66,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, -1, v2       ; encoding: [0x05,0x00,0x66,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, -1, v2           ; encoding: [0x05,0x00,0x66,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, -4.0, v2     ; encoding: [0x05,0x00,0x66,0xd7,0xf7,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, -4.0, v2         ; encoding: [0x05,0x00,0x66,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, 0, v2        ; encoding: [0x05,0x00,0x66,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, 0, v2            ; encoding: [0x05,0x00,0x66,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, 0.5, v2      ; encoding: [0x05,0x00,0x66,0xd7,0xf0,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, 0.5, v2          ; encoding: [0x05,0x00,0x66,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, exec_hi, v2  ; encoding: [0x05,0x00,0x66,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, exec_hi, v2      ; encoding: [0x05,0x00,0x66,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, exec_lo, v2  ; encoding: [0x05,0x00,0x66,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, exec_lo, v2      ; encoding: [0x05,0x00,0x66,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, m0, v2       ; encoding: [0x05,0x00,0x66,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, m0, v2           ; encoding: [0x05,0x00,0x66,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, s1, v2       ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, s1, v2           ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, s103, v2     ; encoding: [0x05,0x00,0x66,0xd7,0x67,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, s103, v2         ; encoding: [0x05,0x00,0x66,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x67,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, ttmp11, v2   ; encoding: [0x05,0x00,0x66,0xd7,0x77,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, ttmp11, v2       ; encoding: [0x05,0x00,0x66,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x77,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, -1       ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, -1           ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x66,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, -4.0     ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xef,0x01,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, -4.0         ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, 0        ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, 0            ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x66,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, 0.5      ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xe1,0x01,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, 0.5          ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, exec_hi  ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, exec_hi      ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, exec_lo  ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, exec_lo      ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, m0       ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, m0           ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, s103     ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xcf,0x00,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, s103         ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xcf,0x00,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, s2       ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, s2           ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x66,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, ttmp11   ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xef,0x00,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, ttmp11       ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xef,0x00,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, v2       ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, v2           ; encoding: [0x05,0x00,0x66,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, v255     ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, v255         ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, vcc_hi   ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, vcc_hi       ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v1, vcc_lo   ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v1, vcc_lo       ; encoding: [0x05,0x00,0x66,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x66,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, v255, v2     ; encoding: [0x05,0x00,0x66,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, v255, v2         ; encoding: [0x05,0x00,0x66,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x66,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, vcc_hi, v2   ; encoding: [0x05,0x00,0x66,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, vcc_hi, v2       ; encoding: [0x05,0x00,0x66,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_hi_u32_b32_e64 v5, vcc_lo, v2   ; encoding: [0x05,0x00,0x66,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_mbcnt_hi_u32_b32 v5, vcc_lo, v2       ; encoding: [0x05,0x00,0x66,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x66,0xd7,0x6a,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v255, v1, v2     ; encoding: [0xff,0x00,0x65,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v255, v1, v2         ; encoding: [0xff,0x00,0x65,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x65,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, -1, v2       ; encoding: [0x05,0x00,0x65,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, -1, v2           ; encoding: [0x05,0x00,0x65,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, -4.0, v2     ; encoding: [0x05,0x00,0x65,0xd7,0xf7,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, -4.0, v2         ; encoding: [0x05,0x00,0x65,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, 0, v2        ; encoding: [0x05,0x00,0x65,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, 0, v2            ; encoding: [0x05,0x00,0x65,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, 0.5, v2      ; encoding: [0x05,0x00,0x65,0xd7,0xf0,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, 0.5, v2          ; encoding: [0x05,0x00,0x65,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, exec_hi, v2  ; encoding: [0x05,0x00,0x65,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, exec_hi, v2      ; encoding: [0x05,0x00,0x65,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, exec_lo, v2  ; encoding: [0x05,0x00,0x65,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, exec_lo, v2      ; encoding: [0x05,0x00,0x65,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, m0, v2       ; encoding: [0x05,0x00,0x65,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, m0, v2           ; encoding: [0x05,0x00,0x65,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, s1, v2       ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, s1, v2           ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, s103, v2     ; encoding: [0x05,0x00,0x65,0xd7,0x67,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, s103, v2         ; encoding: [0x05,0x00,0x65,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x67,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, ttmp11, v2   ; encoding: [0x05,0x00,0x65,0xd7,0x77,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, ttmp11, v2       ; encoding: [0x05,0x00,0x65,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x77,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, -1       ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, -1           ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x65,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, -4.0     ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xef,0x01,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, -4.0         ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, 0        ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, 0            ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x65,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, 0.5      ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xe1,0x01,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, 0.5          ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, exec_hi  ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, exec_hi      ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, exec_lo  ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, exec_lo      ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, m0       ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, m0           ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, s103     ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xcf,0x00,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, s103         ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xcf,0x00,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, s2       ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, s2           ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x65,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, ttmp11   ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xef,0x00,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, ttmp11       ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xef,0x00,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, v2       ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, v2           ; encoding: [0x05,0x00,0x65,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, v255     ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, v255         ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, vcc_hi   ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, vcc_hi       ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v1, vcc_lo   ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v1, vcc_lo       ; encoding: [0x05,0x00,0x65,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x65,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, v255, v2     ; encoding: [0x05,0x00,0x65,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, v255, v2         ; encoding: [0x05,0x00,0x65,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x65,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, vcc_hi, v2   ; encoding: [0x05,0x00,0x65,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, vcc_hi, v2       ; encoding: [0x05,0x00,0x65,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_mbcnt_lo_u32_b32_e64 v5, vcc_lo, v2   ; encoding: [0x05,0x00,0x65,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_mbcnt_lo_u32_b32 v5, vcc_lo, v2       ; encoding: [0x05,0x00,0x65,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x65,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_med3_f16 v255, v1, v2, v3             ; encoding: [0xff,0x00,0x57,0xd7,0x01,0x05,0x0e,0x04]
 0xff,0x00,0x57,0xd7,0x01,0x05,0x0e,0x04
 
 # GFX10: v_med3_f16 v5, -1, v2, v3               ; encoding: [0x05,0x00,0x57,0xd7,0xc1,0x04,0x0e,0x04]
 0x05,0x00,0x57,0xd7,0xc1,0x04,0x0e,0x04
 

 0x05,0x00,0x66,0xd5,0x6a,0x04,0x02,0x00
 
 # GFX10: v_min_f64 v[5:6], |v[1:2]|, v[2:3]      ; encoding: [0x05,0x01,0x66,0xd5,0x01,0x05,0x02,0x00]
 0x05,0x01,0x66,0xd5,0x01,0x05,0x02,0x00
 
 # GFX10: v_min_f64 v[5:6], |v[1:2]|, |v[2:3]|    ; encoding: [0x05,0x03,0x66,0xd5,0x01,0x05,0x02,0x00]
 0x05,0x03,0x66,0xd5,0x01,0x05,0x02,0x00
 
-# GFX10: v_min_i16_e64 v255, v1, v2              ; encoding: [0xff,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_min_i16 v255, v1, v2                  ; encoding: [0xff,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, -1, v2                ; encoding: [0x05,0x00,0x0c,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_min_i16 v5, -1, v2                    ; encoding: [0x05,0x00,0x0c,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, 0xc400, v2            ; encoding: [0x05,0x00,0x0c,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_min_i16 v5, 0xc400, v2                ; encoding: [0x05,0x00,0x0c,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, 0, v2                 ; encoding: [0x05,0x00,0x0c,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_min_i16 v5, 0, v2                     ; encoding: [0x05,0x00,0x0c,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, 0x3800, v2            ; encoding: [0x05,0x00,0x0c,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_min_i16 v5, 0x3800, v2                ; encoding: [0x05,0x00,0x0c,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, exec_hi, v2           ; encoding: [0x05,0x00,0x0c,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_min_i16 v5, exec_hi, v2               ; encoding: [0x05,0x00,0x0c,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, exec_lo, v2           ; encoding: [0x05,0x00,0x0c,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_min_i16 v5, exec_lo, v2               ; encoding: [0x05,0x00,0x0c,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, m0, v2                ; encoding: [0x05,0x00,0x0c,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_min_i16 v5, m0, v2                    ; encoding: [0x05,0x00,0x0c,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, s1, v2                ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_min_i16 v5, s1, v2                    ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, s101, v2              ; encoding: [0x05,0x00,0x0c,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_min_i16 v5, s101, v2                  ; encoding: [0x05,0x00,0x0c,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, -1                ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_min_i16 v5, v1, -1                    ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, 0xc400            ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_min_i16 v5, v1, 0xc400                ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, 0                 ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_min_i16 v5, v1, 0                     ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, 0x3800            ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_min_i16 v5, v1, 0x3800                ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, exec_hi           ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_min_i16 v5, v1, exec_hi               ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, exec_lo           ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_min_i16 v5, v1, exec_lo               ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, m0                ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_min_i16 v5, v1, m0                    ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, s101              ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_min_i16 v5, v1, s101                  ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, s2                ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_min_i16 v5, v1, s2                    ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_min_i16 v5, v1, v2                    ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, v255              ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_min_i16 v5, v1, v255                  ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, vcc_hi            ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_min_i16 v5, v1, vcc_hi                ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_min_i16_e64 v5, v1, vcc_lo            ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_min_i16 v5, v1, vcc_lo                ; encoding: [0x05,0x00,0x0c,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x0c,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_min_i16_e64 v5, v255, v2              ; encoding: [0x05,0x00,0x0c,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_min_i16 v5, v255, v2                  ; encoding: [0x05,0x00,0x0c,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, vcc_hi, v2            ; encoding: [0x05,0x00,0x0c,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_min_i16 v5, vcc_hi, v2                ; encoding: [0x05,0x00,0x0c,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_min_i16_e64 v5, vcc_lo, v2            ; encoding: [0x05,0x00,0x0c,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_min_i16 v5, vcc_lo, v2                ; encoding: [0x05,0x00,0x0c,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x0c,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_min_i32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x23,0x01,0xe4,0x00,0x00
 
 # GFX10: v_min_i32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x22,0x01,0xe4,0x00,0x00
 

 0xf9,0x04,0x0a,0x22,0xff,0x06,0x06,0x06
 
 # GFX10: v_min_i32_sdwa v5, vcc_hi, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x22,0x6b,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x22,0x6b,0x06,0x86,0x06
 
 # GFX10: v_min_i32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x22,0x6a,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x22,0x6a,0x06,0x86,0x06
 
-# GFX10: v_min_u16_e64 v255, v1, v2              ; encoding: [0xff,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_min_u16 v255, v1, v2                  ; encoding: [0xff,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, -1, v2                ; encoding: [0x05,0x00,0x0b,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_min_u16 v5, -1, v2                    ; encoding: [0x05,0x00,0x0b,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, 0xc400, v2            ; encoding: [0x05,0x00,0x0b,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_min_u16 v5, 0xc400, v2                ; encoding: [0x05,0x00,0x0b,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, 0, v2                 ; encoding: [0x05,0x00,0x0b,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_min_u16 v5, 0, v2                     ; encoding: [0x05,0x00,0x0b,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, 0x3800, v2            ; encoding: [0x05,0x00,0x0b,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_min_u16 v5, 0x3800, v2                ; encoding: [0x05,0x00,0x0b,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, exec_hi, v2           ; encoding: [0x05,0x00,0x0b,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_min_u16 v5, exec_hi, v2               ; encoding: [0x05,0x00,0x0b,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, exec_lo, v2           ; encoding: [0x05,0x00,0x0b,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_min_u16 v5, exec_lo, v2               ; encoding: [0x05,0x00,0x0b,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, m0, v2                ; encoding: [0x05,0x00,0x0b,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_min_u16 v5, m0, v2                    ; encoding: [0x05,0x00,0x0b,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, s1, v2                ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_min_u16 v5, s1, v2                    ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, s101, v2              ; encoding: [0x05,0x00,0x0b,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_min_u16 v5, s101, v2                  ; encoding: [0x05,0x00,0x0b,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, -1                ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_min_u16 v5, v1, -1                    ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, 0xc400            ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_min_u16 v5, v1, 0xc400                ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, 0                 ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_min_u16 v5, v1, 0                     ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, 0x3800            ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_min_u16 v5, v1, 0x3800                ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, exec_hi           ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_min_u16 v5, v1, exec_hi               ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, exec_lo           ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_min_u16 v5, v1, exec_lo               ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, m0                ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_min_u16 v5, v1, m0                    ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, s101              ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_min_u16 v5, v1, s101                  ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, s2                ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_min_u16 v5, v1, s2                    ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, v2                ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_min_u16 v5, v1, v2                    ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, v255              ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_min_u16 v5, v1, v255                  ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, vcc_hi            ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_min_u16 v5, v1, vcc_hi                ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_min_u16_e64 v5, v1, vcc_lo            ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_min_u16 v5, v1, vcc_lo                ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x0b,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_min_u16_e64 v5, v255, v2              ; encoding: [0x05,0x00,0x0b,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_min_u16 v5, v255, v2                  ; encoding: [0x05,0x00,0x0b,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, vcc_hi, v2            ; encoding: [0x05,0x00,0x0b,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_min_u16 v5, vcc_hi, v2                ; encoding: [0x05,0x00,0x0b,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_min_u16_e64 v5, vcc_lo, v2            ; encoding: [0x05,0x00,0x0b,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_min_u16 v5, vcc_lo, v2                ; encoding: [0x05,0x00,0x0b,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x0b,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_min_u32_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x27,0x01,0xe4,0x00,0x00
 
 # GFX10: v_min_u32_dpp v5, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0x0a,0x26,0x01,0xe4,0x00,0x00
 

 0xf9,0x04,0x0a,0x0e,0x6b,0x06,0x86,0x06
 
 # GFX10: v_mul_legacy_f32_sdwa v5, vcc_lo, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x0e,0x6a,0x06,0x86,0x06]
 0xf9,0x04,0x0a,0x0e,0x6a,0x06,0x86,0x06
 
 # GFX10: v_mul_legacy_f32_sdwa v5, |v1|, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x0e,0x01,0x06,0x26,0x06]
 0xf9,0x04,0x0a,0x0e,0x01,0x06,0x26,0x06
 
-# GFX10: v_mul_lo_u16_e64 v255, v1, v2           ; encoding: [0xff,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_mul_lo_u16 v255, v1, v2               ; encoding: [0xff,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x05,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, -1, v2             ; encoding: [0x05,0x00,0x05,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, -1, v2                 ; encoding: [0x05,0x00,0x05,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x05,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, 0xc400, v2         ; encoding: [0x05,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, 0xc400, v2             ; encoding: [0x05,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x05,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, 0, v2              ; encoding: [0x05,0x00,0x05,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, 0, v2                  ; encoding: [0x05,0x00,0x05,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x05,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, 0x3800, v2         ; encoding: [0x05,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, 0x3800, v2             ; encoding: [0x05,0x00,0x05,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x05,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, exec_hi, v2        ; encoding: [0x05,0x00,0x05,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, exec_hi, v2            ; encoding: [0x05,0x00,0x05,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x05,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, exec_lo, v2        ; encoding: [0x05,0x00,0x05,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, exec_lo, v2            ; encoding: [0x05,0x00,0x05,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x05,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, m0, v2             ; encoding: [0x05,0x00,0x05,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, m0, v2                 ; encoding: [0x05,0x00,0x05,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x05,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, s1, v2             ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, s1, v2                 ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x05,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, s101, v2           ; encoding: [0x05,0x00,0x05,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, s101, v2               ; encoding: [0x05,0x00,0x05,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x05,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, -1             ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, -1                 ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x05,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, 0xc400         ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, 0xc400             ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x05,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, 0              ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, 0                  ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x05,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, 0x3800         ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, 0x3800             ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x05,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, exec_hi        ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, exec_hi            ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x05,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, exec_lo        ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, exec_lo            ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x05,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, m0             ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, m0                 ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x05,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, s101           ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, s101               ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x05,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, s2             ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, s2                 ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x05,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, v2             ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, v2                 ; encoding: [0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x05,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, v255           ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, v255               ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x05,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, vcc_hi         ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, vcc_hi             ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x05,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v1, vcc_lo         ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_mul_lo_u16 v5, v1, vcc_lo             ; encoding: [0x05,0x00,0x05,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x05,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, v255, v2           ; encoding: [0x05,0x00,0x05,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, v255, v2               ; encoding: [0x05,0x00,0x05,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x05,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, vcc_hi, v2         ; encoding: [0x05,0x00,0x05,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, vcc_hi, v2             ; encoding: [0x05,0x00,0x05,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x05,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_mul_lo_u16_e64 v5, vcc_lo, v2         ; encoding: [0x05,0x00,0x05,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_mul_lo_u16 v5, vcc_lo, v2             ; encoding: [0x05,0x00,0x05,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x05,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_mul_lo_u32 v255, v1, v2               ; encoding: [0xff,0x00,0x69,0xd5,0x01,0x05,0x02,0x00]
 0xff,0x00,0x69,0xd5,0x01,0x05,0x02,0x00
 
 # GFX10: v_mul_lo_u32 v5, -1, v2                 ; encoding: [0x05,0x00,0x69,0xd5,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x69,0xd5,0xc1,0x04,0x02,0x00
 

 0x05,0x00,0x78,0xd7,0x67,0x05,0x0c,0x00
 
 # GFX10: v_permlanex16_b32 v5, v255, s2, s3      ; encoding: [0x05,0x00,0x78,0xd7,0xff,0x05,0x0c,0x00]
 0x05,0x00,0x78,0xd7,0xff,0x05,0x0c,0x00
 
 # GFX10: v_pipeflush                             ; encoding: [0x00,0x36,0x00,0x7e]
 0x00,0x36,0x00,0x7e
 
-# GFX10: v_pk_fmac_f16_e32 v255, v1, v2          ; encoding: [0x01,0x05,0xfe,0x79]
+# GFX10: v_pk_fmac_f16 v255, v1, v2              ; encoding: [0x01,0x05,0xfe,0x79]
 0x01,0x05,0xfe,0x79
 
-# GFX10: v_pk_fmac_f16_e32 v5, -1, v2            ; encoding: [0xc1,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, -1, v2                ; encoding: [0xc1,0x04,0x0a,0x78]
 0xc1,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, -4.0, v2          ; encoding: [0xf7,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, -4.0, v2              ; encoding: [0xf7,0x04,0x0a,0x78]
 0xf7,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, 0, v2             ; encoding: [0x80,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, 0, v2                 ; encoding: [0x80,0x04,0x0a,0x78]
 0x80,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, 0.5, v2           ; encoding: [0xf0,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, 0.5, v2               ; encoding: [0xf0,0x04,0x0a,0x78]
 0xf0,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, exec_hi, v2       ; encoding: [0x7f,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, exec_hi, v2           ; encoding: [0x7f,0x04,0x0a,0x78]
 0x7f,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, exec_lo, v2       ; encoding: [0x7e,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, exec_lo, v2           ; encoding: [0x7e,0x04,0x0a,0x78]
 0x7e,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, m0, v2            ; encoding: [0x7c,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, m0, v2                ; encoding: [0x7c,0x04,0x0a,0x78]
 0x7c,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, s1, v2            ; encoding: [0x01,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, s1, v2                ; encoding: [0x01,0x04,0x0a,0x78]
 0x01,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, s103, v2          ; encoding: [0x67,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, s103, v2              ; encoding: [0x67,0x04,0x0a,0x78]
 0x67,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, ttmp11, v2        ; encoding: [0x77,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, ttmp11, v2            ; encoding: [0x77,0x04,0x0a,0x78]
 0x77,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, v1, v2            ; encoding: [0x01,0x05,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, v1, v2                ; encoding: [0x01,0x05,0x0a,0x78]
 0x01,0x05,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, v1, v255          ; encoding: [0x01,0xff,0x0b,0x78]
+# GFX10: v_pk_fmac_f16 v5, v1, v255              ; encoding: [0x01,0xff,0x0b,0x78]
 0x01,0xff,0x0b,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, v255, v2          ; encoding: [0xff,0x05,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, v255, v2              ; encoding: [0xff,0x05,0x0a,0x78]
 0xff,0x05,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, vcc_hi, v2        ; encoding: [0x6b,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, vcc_hi, v2            ; encoding: [0x6b,0x04,0x0a,0x78]
 0x6b,0x04,0x0a,0x78
 
-# GFX10: v_pk_fmac_f16_e32 v5, vcc_lo, v2        ; encoding: [0x6a,0x04,0x0a,0x78]
+# GFX10: v_pk_fmac_f16 v5, vcc_lo, v2            ; encoding: [0x6a,0x04,0x0a,0x78]
 0x6a,0x04,0x0a,0x78
 
 # GFX10: v_qsad_pk_u16_u8 v[254:255], v[1:2], v2, v[3:4] ; encoding: [0xfe,0x00,0x72,0xd5,0x01,0x05,0x0e,0x04]
 0xfe,0x00,0x72,0xd5,0x01,0x05,0x0e,0x04
 
 # GFX10: v_qsad_pk_u16_u8 v[5:6], -1, v2, v[3:4] ; encoding: [0x05,0x00,0x72,0xd5,0xc1,0x04,0x0e,0x04]
 0x05,0x00,0x72,0xd5,0xc1,0x04,0x0e,0x04
 

 # W32: v_sub_co_ci_u32_sdwa v5, vcc_lo, v1, v255, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
 # W64: v_sub_co_ci_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06]
 0xf9,0xfe,0x0b,0x52,0x01,0x06,0x06,0x06
 
 # W32: v_sub_co_ci_u32_sdwa v5, vcc_lo, v255, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
 # W64: v_sub_co_ci_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x52,0xff,0x06,0x06,0x06
 
-# W32: v_sub_co_u32_e64 v255, s0, v1, v2       ; encoding: [0xff,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
-# W64: v_sub_co_u32_e64 v255, s[0:1], v1, v2   ; encoding: [0xff,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
+# W32: v_sub_co_u32 v255, s0, v1, v2           ; encoding: [0xff,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
+# W64: v_sub_co_u32 v255, s[0:1], v1, v2       ; encoding: [0xff,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x10,0xd7,0x01,0x05,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, -1, v2         ; encoding: [0x05,0x00,0x10,0xd7,0xc1,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], -1, v2     ; encoding: [0x05,0x00,0x10,0xd7,0xc1,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, -1, v2             ; encoding: [0x05,0x00,0x10,0xd7,0xc1,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], -1, v2         ; encoding: [0x05,0x00,0x10,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0xc1,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, -4.0, v2       ; encoding: [0x05,0x00,0x10,0xd7,0xf7,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], -4.0, v2   ; encoding: [0x05,0x00,0x10,0xd7,0xf7,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, -4.0, v2           ; encoding: [0x05,0x00,0x10,0xd7,0xf7,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], -4.0, v2       ; encoding: [0x05,0x00,0x10,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0xf7,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, 0, v2          ; encoding: [0x05,0x00,0x10,0xd7,0x80,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], 0, v2      ; encoding: [0x05,0x00,0x10,0xd7,0x80,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, 0, v2              ; encoding: [0x05,0x00,0x10,0xd7,0x80,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], 0, v2          ; encoding: [0x05,0x00,0x10,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x80,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, 0.5, v2        ; encoding: [0x05,0x00,0x10,0xd7,0xf0,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], 0.5, v2    ; encoding: [0x05,0x00,0x10,0xd7,0xf0,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, 0.5, v2            ; encoding: [0x05,0x00,0x10,0xd7,0xf0,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], 0.5, v2        ; encoding: [0x05,0x00,0x10,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0xf0,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, exec_hi, v2    ; encoding: [0x05,0x00,0x10,0xd7,0x7f,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], exec_hi, v2 ; encoding: [0x05,0x00,0x10,0xd7,0x7f,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, exec_hi, v2        ; encoding: [0x05,0x00,0x10,0xd7,0x7f,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], exec_hi, v2    ; encoding: [0x05,0x00,0x10,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x7f,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, exec_lo, v2    ; encoding: [0x05,0x00,0x10,0xd7,0x7e,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], exec_lo, v2 ; encoding: [0x05,0x00,0x10,0xd7,0x7e,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, exec_lo, v2        ; encoding: [0x05,0x00,0x10,0xd7,0x7e,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], exec_lo, v2    ; encoding: [0x05,0x00,0x10,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x7e,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, m0, v2         ; encoding: [0x05,0x00,0x10,0xd7,0x7c,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], m0, v2     ; encoding: [0x05,0x00,0x10,0xd7,0x7c,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, m0, v2             ; encoding: [0x05,0x00,0x10,0xd7,0x7c,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], m0, v2         ; encoding: [0x05,0x00,0x10,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x7c,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, s1, v2         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], s1, v2     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, s1, v2             ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], s1, v2         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x01,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, s103, v2       ; encoding: [0x05,0x00,0x10,0xd7,0x67,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], s103, v2   ; encoding: [0x05,0x00,0x10,0xd7,0x67,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, s103, v2           ; encoding: [0x05,0x00,0x10,0xd7,0x67,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], s103, v2       ; encoding: [0x05,0x00,0x10,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x67,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, ttmp11, v2     ; encoding: [0x05,0x00,0x10,0xd7,0x77,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], ttmp11, v2 ; encoding: [0x05,0x00,0x10,0xd7,0x77,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, ttmp11, v2         ; encoding: [0x05,0x00,0x10,0xd7,0x77,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], ttmp11, v2     ; encoding: [0x05,0x00,0x10,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x77,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, -1         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x83,0x01,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, -1     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x83,0x01,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, -1             ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x83,0x01,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, -1         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x10,0xd7,0x01,0x83,0x01,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, -4.0       ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x01,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, -4.0   ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x01,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, -4.0           ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x01,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, -4.0       ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xef,0x01,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, 0          ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x01,0x01,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, 0      ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x01,0x01,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, 0              ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x01,0x01,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, 0          ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x10,0xd7,0x01,0x01,0x01,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, 0.5        ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xe1,0x01,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, 0.5    ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xe1,0x01,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, 0.5            ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xe1,0x01,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, 0.5        ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xe1,0x01,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, exec_hi    ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x00,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, exec_hi ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x00,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, exec_hi        ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, exec_hi    ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xff,0x00,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, exec_lo    ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xfd,0x00,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, exec_lo ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xfd,0x00,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, exec_lo        ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xfd,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, exec_lo    ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xfd,0x00,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, m0         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xf9,0x00,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, m0     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xf9,0x00,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, m0             ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xf9,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, m0         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xf9,0x00,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, s103       ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xcf,0x00,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, s103   ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xcf,0x00,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, s103           ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xcf,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, s103       ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xcf,0x00,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, s2         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x00,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, s2     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x00,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, s2             ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, s2         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x10,0xd7,0x01,0x05,0x00,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, ttmp11     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x00,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, ttmp11 ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x00,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, ttmp11         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, ttmp11     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xef,0x00,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, v2         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, v2     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, v2             ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, v2         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x01,0x05,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, v255       ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x03,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, v255   ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x03,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, v255           ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x03,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, v255       ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xff,0x03,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, vcc_hi     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xd7,0x00,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, vcc_hi ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xd7,0x00,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, vcc_hi         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xd7,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, vcc_hi     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xd7,0x00,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v1, vcc_lo     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xd5,0x00,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v1, vcc_lo ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xd5,0x00,0x00]
+# W32: v_sub_co_u32 v5, s0, v1, vcc_lo         ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xd5,0x00,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v1, vcc_lo     ; encoding: [0x05,0x00,0x10,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x10,0xd7,0x01,0xd5,0x00,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, v255, v2       ; encoding: [0x05,0x00,0x10,0xd7,0xff,0x05,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], v255, v2   ; encoding: [0x05,0x00,0x10,0xd7,0xff,0x05,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, v255, v2           ; encoding: [0x05,0x00,0x10,0xd7,0xff,0x05,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], v255, v2       ; encoding: [0x05,0x00,0x10,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x10,0xd7,0xff,0x05,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, vcc_hi, v2     ; encoding: [0x05,0x00,0x10,0xd7,0x6b,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], vcc_hi, v2 ; encoding: [0x05,0x00,0x10,0xd7,0x6b,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, vcc_hi, v2         ; encoding: [0x05,0x00,0x10,0xd7,0x6b,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], vcc_hi, v2     ; encoding: [0x05,0x00,0x10,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x6b,0x04,0x02,0x00
 
-# W32: v_sub_co_u32_e64 v5, s0, vcc_lo, v2     ; encoding: [0x05,0x00,0x10,0xd7,0x6a,0x04,0x02,0x00]
-# W64: v_sub_co_u32_e64 v5, s[0:1], vcc_lo, v2 ; encoding: [0x05,0x00,0x10,0xd7,0x6a,0x04,0x02,0x00]
+# W32: v_sub_co_u32 v5, s0, vcc_lo, v2         ; encoding: [0x05,0x00,0x10,0xd7,0x6a,0x04,0x02,0x00]
+# W64: v_sub_co_u32 v5, s[0:1], vcc_lo, v2     ; encoding: [0x05,0x00,0x10,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x10,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_sub_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x67,0x01,0xe4,0x00,0x00
 
 # GFX10: v_sub_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x66,0x01,0xe4,0x10,0x00
 

 0x05,0x00,0x76,0xd7,0x6b,0x04,0x02,0x00
 
 # GFX10: v_sub_nc_i32 v5, vcc_lo, v2             ; encoding: [0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x76,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_sub_nc_i32 v1, v2, v3 clamp           ; encoding: [0x01,0x80,0x76,0xd7,0x02,0x07,0x02,0x00]
 0x01,0x80,0x76,0xd7,0x02,0x07,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v255, v1, v2           ; encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_sub_nc_u16 v255, v1, v2               ; encoding: [0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x04,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, -1, v2             ; encoding: [0x05,0x00,0x04,0xd7,0xc1,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, -1, v2                 ; encoding: [0x05,0x00,0x04,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0xc1,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, 0xc400, v2         ; encoding: [0x05,0x00,0x04,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, 0xc400, v2             ; encoding: [0x05,0x00,0x04,0xd7,0xff,0x04,0x02,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x04,0xd7,0xf7,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, 0, v2              ; encoding: [0x05,0x00,0x04,0xd7,0x80,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, 0, v2                  ; encoding: [0x05,0x00,0x04,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x80,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, 0x3800, v2         ; encoding: [0x05,0x00,0x04,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, 0x3800, v2             ; encoding: [0x05,0x00,0x04,0xd7,0xff,0x04,0x02,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x04,0xd7,0xf0,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, exec_hi, v2        ; encoding: [0x05,0x00,0x04,0xd7,0x7f,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, exec_hi, v2            ; encoding: [0x05,0x00,0x04,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x7f,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, exec_lo, v2        ; encoding: [0x05,0x00,0x04,0xd7,0x7e,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, exec_lo, v2            ; encoding: [0x05,0x00,0x04,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x7e,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, m0, v2             ; encoding: [0x05,0x00,0x04,0xd7,0x7c,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, m0, v2                 ; encoding: [0x05,0x00,0x04,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x7c,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, s1, v2             ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, s1, v2                 ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x01,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, s101, v2           ; encoding: [0x05,0x00,0x04,0xd7,0x65,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, s101, v2               ; encoding: [0x05,0x00,0x04,0xd7,0x65,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x65,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, -1             ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x83,0x01,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, -1                 ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x04,0xd7,0x01,0x83,0x01,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, 0xc400         ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, 0xc400             ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0xc4,0x00,0x00]
 0x05,0x00,0x04,0xd7,0x01,0xef,0x01,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, 0              ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x01,0x01,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, 0                  ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x04,0xd7,0x01,0x01,0x01,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, 0x3800         ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, 0x3800             ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x01,0x00,0x00,0x38,0x00,0x00]
 0x05,0x00,0x04,0xd7,0x01,0xe1,0x01,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, exec_hi        ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, exec_hi            ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x04,0xd7,0x01,0xff,0x00,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, exec_lo        ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xfd,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, exec_lo            ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x04,0xd7,0x01,0xfd,0x00,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, m0             ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xf9,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, m0                 ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x04,0xd7,0x01,0xf9,0x00,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, s101           ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xcb,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, s101               ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xcb,0x00,0x00]
 0x05,0x00,0x04,0xd7,0x01,0xcb,0x00,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, s2             ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, s2                 ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x04,0xd7,0x01,0x05,0x00,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, v2             ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, v2                 ; encoding: [0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x01,0x05,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, v255           ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x03,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, v255               ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x04,0xd7,0x01,0xff,0x03,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, vcc_hi         ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xd7,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, vcc_hi             ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x04,0xd7,0x01,0xd7,0x00,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v1, vcc_lo         ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xd5,0x00,0x00]
+# GFX10: v_sub_nc_u16 v5, v1, vcc_lo             ; encoding: [0x05,0x00,0x04,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x04,0xd7,0x01,0xd5,0x00,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, v255, v2           ; encoding: [0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, v255, v2               ; encoding: [0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x04,0xd7,0xff,0x05,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, vcc_hi, v2         ; encoding: [0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, vcc_hi, v2             ; encoding: [0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x6b,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, vcc_lo, v2         ; encoding: [0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, vcc_lo, v2             ; encoding: [0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x04,0xd7,0x6a,0x04,0x02,0x00
 
-# GFX10: v_sub_nc_u16_e64 v5, vcc_lo, v2 clamp   ; encoding: [0x05,0x80,0x04,0xd7,0x6a,0x04,0x02,0x00]
+# GFX10: v_sub_nc_u16 v5, vcc_lo, v2 clamp       ; encoding: [0x05,0x80,0x04,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x80,0x04,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_sub_nc_u32_e32 v255, v1, v2           ; encoding: [0x01,0x05,0xfe,0x4d]
 0x01,0x05,0xfe,0x4d
 
 # GFX10: v_sub_nc_u32_e32 v5, -1, v2             ; encoding: [0xc1,0x04,0x0a,0x4c]
 0xc1,0x04,0x0a,0x4c
 

 # W32: v_subrev_co_ci_u32_sdwa v5, vcc_lo, v1, v255, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
 # W64: v_subrev_co_ci_u32_sdwa v5, vcc, v1, v255, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06]
 0xf9,0xfe,0x0b,0x54,0x01,0x06,0x06,0x06
 
 # W32: v_subrev_co_ci_u32_sdwa v5, vcc_lo, v255, v2, vcc_lo dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
 # W64: v_subrev_co_ci_u32_sdwa v5, vcc, v255, v2, vcc dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; encoding: [0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06]
 0xf9,0x04,0x0a,0x54,0xff,0x06,0x06,0x06
 
-# W32: v_subrev_co_u32_e64 v255, s0, v1, v2    ; encoding: [0xff,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v255, s[0:1], v1, v2 ; encoding: [0xff,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
+# W32: v_subrev_co_u32 v255, s0, v1, v2        ; encoding: [0xff,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
+# W64: v_subrev_co_u32 v255, s[0:1], v1, v2    ; encoding: [0xff,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
 0xff,0x00,0x19,0xd7,0x01,0x05,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, -1, v2      ; encoding: [0x05,0x00,0x19,0xd7,0xc1,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], -1, v2  ; encoding: [0x05,0x00,0x19,0xd7,0xc1,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, -1, v2          ; encoding: [0x05,0x00,0x19,0xd7,0xc1,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], -1, v2      ; encoding: [0x05,0x00,0x19,0xd7,0xc1,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0xc1,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, -4.0, v2    ; encoding: [0x05,0x00,0x19,0xd7,0xf7,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], -4.0, v2 ; encoding: [0x05,0x00,0x19,0xd7,0xf7,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, -4.0, v2        ; encoding: [0x05,0x00,0x19,0xd7,0xf7,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], -4.0, v2    ; encoding: [0x05,0x00,0x19,0xd7,0xf7,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0xf7,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, 0, v2       ; encoding: [0x05,0x00,0x19,0xd7,0x80,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], 0, v2   ; encoding: [0x05,0x00,0x19,0xd7,0x80,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, 0, v2           ; encoding: [0x05,0x00,0x19,0xd7,0x80,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], 0, v2       ; encoding: [0x05,0x00,0x19,0xd7,0x80,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x80,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, 0.5, v2     ; encoding: [0x05,0x00,0x19,0xd7,0xf0,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], 0.5, v2 ; encoding: [0x05,0x00,0x19,0xd7,0xf0,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, 0.5, v2         ; encoding: [0x05,0x00,0x19,0xd7,0xf0,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], 0.5, v2     ; encoding: [0x05,0x00,0x19,0xd7,0xf0,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0xf0,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, exec_hi, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x7f,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], exec_hi, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x7f,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, exec_hi, v2     ; encoding: [0x05,0x00,0x19,0xd7,0x7f,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], exec_hi, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x7f,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x7f,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, exec_lo, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x7e,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], exec_lo, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x7e,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, exec_lo, v2     ; encoding: [0x05,0x00,0x19,0xd7,0x7e,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], exec_lo, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x7e,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x7e,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, m0, v2      ; encoding: [0x05,0x00,0x19,0xd7,0x7c,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], m0, v2  ; encoding: [0x05,0x00,0x19,0xd7,0x7c,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, m0, v2          ; encoding: [0x05,0x00,0x19,0xd7,0x7c,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], m0, v2      ; encoding: [0x05,0x00,0x19,0xd7,0x7c,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x7c,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, s1, v2      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], s1, v2  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, s1, v2          ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], s1, v2      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x01,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, s103, v2    ; encoding: [0x05,0x00,0x19,0xd7,0x67,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], s103, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x67,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, s103, v2        ; encoding: [0x05,0x00,0x19,0xd7,0x67,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], s103, v2    ; encoding: [0x05,0x00,0x19,0xd7,0x67,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x67,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, ttmp11, v2  ; encoding: [0x05,0x00,0x19,0xd7,0x77,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], ttmp11, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x77,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, ttmp11, v2      ; encoding: [0x05,0x00,0x19,0xd7,0x77,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], ttmp11, v2  ; encoding: [0x05,0x00,0x19,0xd7,0x77,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x77,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, -1      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x83,0x01,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, -1  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x83,0x01,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, -1          ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x83,0x01,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, -1      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x83,0x01,0x00]
 0x05,0x00,0x19,0xd7,0x01,0x83,0x01,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, -4.0    ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x01,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, -4.0 ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x01,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, -4.0        ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x01,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, -4.0    ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x01,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xef,0x01,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, 0       ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x01,0x01,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, 0   ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x01,0x01,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, 0           ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x01,0x01,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, 0       ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x01,0x01,0x00]
 0x05,0x00,0x19,0xd7,0x01,0x01,0x01,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, 0.5     ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xe1,0x01,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, 0.5 ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xe1,0x01,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, 0.5         ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xe1,0x01,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, 0.5     ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xe1,0x01,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xe1,0x01,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, exec_hi ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x00,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, exec_hi ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x00,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, exec_hi     ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, exec_hi ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x00,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xff,0x00,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, exec_lo ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xfd,0x00,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, exec_lo ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xfd,0x00,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, exec_lo     ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xfd,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, exec_lo ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xfd,0x00,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xfd,0x00,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, m0      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xf9,0x00,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, m0  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xf9,0x00,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, m0          ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xf9,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, m0      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xf9,0x00,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xf9,0x00,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, s103    ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xcf,0x00,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, s103 ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xcf,0x00,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, s103        ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xcf,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, s103    ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xcf,0x00,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xcf,0x00,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, s2      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x00,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, s2  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x00,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, s2          ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, s2      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x00,0x00]
 0x05,0x00,0x19,0xd7,0x01,0x05,0x00,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, ttmp11  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x00,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, ttmp11 ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x00,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, ttmp11      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, ttmp11  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xef,0x00,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xef,0x00,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, v2      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, v2  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, v2          ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, v2      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0x05,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x01,0x05,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, v255    ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x03,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, v255 ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x03,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, v255        ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x03,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, v255    ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xff,0x03,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xff,0x03,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, vcc_hi  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xd7,0x00,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, vcc_hi ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xd7,0x00,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, vcc_hi      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xd7,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, vcc_hi  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xd7,0x00,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xd7,0x00,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v1, vcc_lo  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xd5,0x00,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v1, vcc_lo ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xd5,0x00,0x00]
+# W32: v_subrev_co_u32 v5, s0, v1, vcc_lo      ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xd5,0x00,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v1, vcc_lo  ; encoding: [0x05,0x00,0x19,0xd7,0x01,0xd5,0x00,0x00]
 0x05,0x00,0x19,0xd7,0x01,0xd5,0x00,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, v255, v2    ; encoding: [0x05,0x00,0x19,0xd7,0xff,0x05,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], v255, v2 ; encoding: [0x05,0x00,0x19,0xd7,0xff,0x05,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, v255, v2        ; encoding: [0x05,0x00,0x19,0xd7,0xff,0x05,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], v255, v2    ; encoding: [0x05,0x00,0x19,0xd7,0xff,0x05,0x02,0x00]
 0x05,0x00,0x19,0xd7,0xff,0x05,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, vcc_hi, v2  ; encoding: [0x05,0x00,0x19,0xd7,0x6b,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], vcc_hi, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x6b,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, vcc_hi, v2      ; encoding: [0x05,0x00,0x19,0xd7,0x6b,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], vcc_hi, v2  ; encoding: [0x05,0x00,0x19,0xd7,0x6b,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x6b,0x04,0x02,0x00
 
-# W32: v_subrev_co_u32_e64 v5, s0, vcc_lo, v2  ; encoding: [0x05,0x00,0x19,0xd7,0x6a,0x04,0x02,0x00]
-# W64: v_subrev_co_u32_e64 v5, s[0:1], vcc_lo, v2 ; encoding: [0x05,0x00,0x19,0xd7,0x6a,0x04,0x02,0x00]
+# W32: v_subrev_co_u32 v5, s0, vcc_lo, v2      ; encoding: [0x05,0x00,0x19,0xd7,0x6a,0x04,0x02,0x00]
+# W64: v_subrev_co_u32 v5, s[0:1], vcc_lo, v2  ; encoding: [0x05,0x00,0x19,0xd7,0x6a,0x04,0x02,0x00]
 0x05,0x00,0x19,0xd7,0x6a,0x04,0x02,0x00
 
 # GFX10: v_subrev_f16_dpp v255, v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0xfe,0x69,0x01,0xe4,0x00,0x00]
 0xfa,0x04,0xfe,0x69,0x01,0xe4,0x00,0x00
 
 # GFX10: v_subrev_f16_dpp v5, -v1, v2 quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0 ; encoding: [0xfa,0x04,0x0a,0x68,0x01,0xe4,0x10,0x00]
 0xfa,0x04,0x0a,0x68,0x01,0xe4,0x10,0x00
 

llvm/test/MC/Disassembler/AMDGPU/gfx90a_dasm_features.txt

 0x04,0x00,0x04,0xd1,0x02,0x11,0x02,0x08
 
 # GFX90A: v_fmac_f64_e64 v[4:5], v[2:3], v[8:9] mul:4 ; encoding: [0x04,0x00,0x04,0xd1,0x02,0x11,0x02,0x10]
 0x04,0x00,0x04,0xd1,0x02,0x11,0x02,0x10
 
 # GFX90A: v_fmac_f64_e64 v[4:5], v[2:3], v[8:9] div:2 ; encoding: [0x04,0x00,0x04,0xd1,0x02,0x11,0x02,0x18]
 0x04,0x00,0x04,0xd1,0x02,0x11,0x02,0x18
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v255, v1, v2 ; encoding: [0xff,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v255, v1, v2 ; encoding: [0xff,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00]
 0xff,0x00,0xa1,0xd2,0x01,0x05,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v255, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xff,0x05,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v255, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xff,0x05,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0xff,0x05,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, s1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, s1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, s101, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x65,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, s101, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x65,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0x65,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x6a,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, vcc_lo, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x6a,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0x6a,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x6b,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, vcc_hi, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x6b,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0x6b,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, m0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7c,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, m0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7c,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0x7c,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, exec_lo, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7e,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, exec_lo, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7e,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0x7e,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, exec_hi, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7f,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, exec_hi, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x7f,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0x7f,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, 0, v2  ; encoding: [0x05,0x00,0xa1,0xd2,0x80,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, 0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x80,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0x80,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, -1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xc1,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, -1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xc1,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0xc1,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, 0.5, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xf0,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, 0.5, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xf0,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0xf0,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, -4.0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xf7,0x04,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, -4.0, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0xf7,0x04,0x02,0x00]
 0x05,0x00,0xa1,0xd2,0xf7,0x04,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, v255 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xff,0x03,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, v255 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xff,0x03,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0xff,0x03,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, s2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x00,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, s2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x00,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0x05,0x00,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, s101 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xcb,0x00,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, s101 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xcb,0x00,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0xcb,0x00,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, vcc_lo ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xd5,0x00,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, vcc_lo ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xd5,0x00,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0xd5,0x00,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, vcc_hi ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xd7,0x00,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, vcc_hi ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xd7,0x00,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0xd7,0x00,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, m0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xf9,0x00,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, m0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xf9,0x00,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0xf9,0x00,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, exec_lo ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xfd,0x00,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, exec_lo ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xfd,0x00,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0xfd,0x00,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, exec_hi ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xff,0x00,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, exec_hi ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xff,0x00,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0xff,0x00,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, 0  ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x01,0x01,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, 0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x01,0x01,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0x01,0x01,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, -1 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x83,0x01,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, -1 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x83,0x01,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0x83,0x01,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, 0.5 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xe1,0x01,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, 0.5 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xe1,0x01,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0xe1,0x01,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, -4.0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xef,0x01,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, -4.0 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0xef,0x01,0x00]
 0x05,0x00,0xa1,0xd2,0x01,0xef,0x01,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, -v1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x20]
+# GFX90A: v_mul_legacy_f32 v5, -v1, v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x20]
 0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x20
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, -v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x40]
+# GFX90A: v_mul_legacy_f32 v5, v1, -v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x40]
 0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x40
 
-# GFX90A: v_mul_legacy_f32_e64 v5, -v1, -v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x60]
+# GFX90A: v_mul_legacy_f32 v5, -v1, -v2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x60]
 0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x60
 
-# GFX90A: v_mul_legacy_f32_e64 v5, |v1|, v2 ; encoding: [0x05,0x01,0xa1,0xd2,0x01,0x05,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, |v1|, v2 ; encoding: [0x05,0x01,0xa1,0xd2,0x01,0x05,0x02,0x00]
 0x05,0x01,0xa1,0xd2,0x01,0x05,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, |v2| ; encoding: [0x05,0x02,0xa1,0xd2,0x01,0x05,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, |v2| ; encoding: [0x05,0x02,0xa1,0xd2,0x01,0x05,0x02,0x00]
 0x05,0x02,0xa1,0xd2,0x01,0x05,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, |v1|, |v2| ; encoding: [0x05,0x03,0xa1,0xd2,0x01,0x05,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, |v1|, |v2| ; encoding: [0x05,0x03,0xa1,0xd2,0x01,0x05,0x02,0x00]
 0x05,0x03,0xa1,0xd2,0x01,0x05,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 clamp ; encoding: [0x05,0x80,0xa1,0xd2,0x01,0x05,0x02,0x00]
+# GFX90A: v_mul_legacy_f32 v5, v1, v2 clamp ; encoding: [0x05,0x80,0xa1,0xd2,0x01,0x05,0x02,0x00]
 0x05,0x80,0xa1,0xd2,0x01,0x05,0x02,0x00
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 mul:2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x08]
+# GFX90A: v_mul_legacy_f32 v5, v1, v2 mul:2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x08]
 0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x08
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 mul:4 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x10]
+# GFX90A: v_mul_legacy_f32 v5, v1, v2 mul:4 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x10]
 0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x10
 
-# GFX90A: v_mul_legacy_f32_e64 v5, v1, v2 div:2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x18]
+# GFX90A: v_mul_legacy_f32 v5, v1, v2 div:2 ; encoding: [0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x18]
 0x05,0x00,0xa1,0xd2,0x01,0x05,0x02,0x18
 
 # GFX90A: v_xor_b32_dpp v6, v29, v27  row_newbcast:0 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x36,0x0c,0x2a,0x1d,0x50,0x01,0xff]
 0xfa,0x36,0x0c,0x2a,0x1d,0x50,0x01,0xff
 
 # GFX90A: v_xor_b32_dpp v6, v29, v27  row_newbcast:7 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x36,0x0c,0x2a,0x1d,0x57,0x01,0xff]
 0xfa,0x36,0x0c,0x2a,0x1d,0x57,0x01,0xff
 

llvm/test/MC/Disassembler/AMDGPU/literalv216_gfx10.txt

 # GFX10: v_pk_ashrrev_i16 v5, v1, 0x12345678 ; encoding: [0x05,0x40,0x06,0xcc,0x01,0xff,0x01,0x18,0x78,0x56,0x34,0x12]
 0x05,0x00,0x06,0xcc,0x01,0xff,0x01,0x18,0x78,0x56,0x34,0x12
 
 #===----------------------------------------------------------------------===//
 # Packed VOP2
 #===----------------------------------------------------------------------===//
 
 # FIXME: v_pk_fmac_f16 cannot be promoted to VOP3 so '_e32' suffix is not valid
-# GFX10: v_pk_fmac_f16_e32 v5, 0x12345678, v2 ; encoding: [0xff,0x04,0x0a,0x78,0x78,0x56,0x34,0x12]
+# GFX10: v_pk_fmac_f16 v5, 0x12345678, v2 ; encoding: [0xff,0x04,0x0a,0x78,0x78,0x56,0x34,0x12]
 0xff,0x04,0x0a,0x78,0x78,0x56,0x34,0x12

llvm/test/MC/Disassembler/AMDGPU/vop3-literal.txt

 0x00,0x00,0x48,0xd5,0x01,0x03,0xfc,0x03,0x39,0x30,0x00,0x00
 
 # GFX10: v_bfe_u32 v0, 0x3039, v1, v2    ; encoding: [0x00,0x00,0x48,0xd5,0xff,0x02,0x0a,0x04,0x39,0x30,0x00,0x00]
 0x00,0x00,0x48,0xd5,0xff,0x02,0x0a,0x04,0x39,0x30,0x00,0x00
 
 # GFX10: v_bfe_u32 v0, s1, 0x3039, s1    ; encoding: [0x00,0x00,0x48,0xd5,0x01,0xfe,0x05,0x00,0x39,0x30,0x00,0x00]
 0x00,0x00,0x48,0xd5,0x01,0xfe,0x05,0x00,0x39,0x30,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v0, 0x3039, s1    ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x00,0x00,0x39,0x30,0x00,0x00]
+# GFX10: v_bfm_b32 v0, 0x3039, s1 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x00,0x00,0x39,0x30,0x00,0x00]
 0x00,0x00,0x63,0xd7,0xff,0x02,0x00,0x00,0x39,0x30,0x00,0x00
 
-# GFX10: v_bfm_b32_e64 v0, 0x3039, v1    ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x02,0x00,0x39,0x30,0x00,0x00]
+# GFX10: v_bfm_b32 v0, 0x3039, v1 ; encoding: [0x00,0x00,0x63,0xd7,0xff,0x02,0x02,0x00,0x39,0x30,0x00,0x00]
 0x00,0x00,0x63,0xd7,0xff,0x02,0x02,0x00,0x39,0x30,0x00,0x00
 
 # GFX10: v_pk_add_f16 v1, 0x4e40, v2     ; encoding: [0x01,0x40,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,0x4e,0x00,0x00]
 0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,0x4e,0x00,0x00
 
 # GFX10: v_pk_add_f16 v1, 0x1e240, v2    ; encoding: [0x01,0x40,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,0xe2,0x01,0x00]
 0x01,0x00,0x0f,0xcc,0xff,0x04,0x02,0x18,0x40,0xe2,0x01,0x00
 

 0x01,0x00,0x0a,0xcc,0xff,0x04,0x02,0x18,0x9c,0xff,0xff,0xff
 
 # GFX10: v_add_nc_i16 v5, v1, 0xcdab ; encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x01,0x00,0xab,0xcd,0xff,0xff]
 0x05,0x00,0x0d,0xd7,0x01,0xff,0x01,0x00,0xab,0xcd,0xff,0xff
 
 # GFX10: v_ceil_f16_e64 v255, 0xabcd clamp ; encoding: [0xff,0x80,0xdc,0xd5,0xff,0x00,0x00,0x00,0xcd,0xab,0xff,0xff]
 0xff,0x80,0xdc,0xd5,0xff,0x00,0x00,0x00,0xcd,0xab,0xff,0xff
 
-# GFX10: v_min_u16_e64 v5, v1, 0xabcd ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0xcd,0xab,0xff,0xff]
+# GFX10: v_min_u16 v5, v1, 0xabcd ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0xcd,0xab,0xff,0xff]
 0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0xcd,0xab,0xff,0xff

llvm/test/MC/Disassembler/AMDGPU/wave32.txt

 # GFX1032: v_cndmask_b32_sdwa v5, v1, v2, vcc_lo  dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
 # GFX1064: v_cndmask_b32_sdwa v5, v1, v2, vcc  dst_sel:DWORD dst_unused:UNUSED_PRESERVE src0_sel:DWORD src1_sel:DWORD
 0xf9,0x04,0x0a,0x02,0x01,0x16,0x06,0x06
 
 # GFX1032: v_cndmask_b32_dpp v5, v1, v2, vcc_lo  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 # GFX1064: v_cndmask_b32_dpp v5, v1, v2, vcc  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 0xfa,0x04,0x0a,0x02,0x01,0xe4,0x00,0x00
 
-# GFX1032: v_add_co_u32_e64 v2, vcc_lo, s0, v2
-# GFX1064: v_add_co_u32_e64 v2, vcc, s0, v2
+# GFX1032: v_add_co_u32 v2, vcc_lo, s0, v2
+# GFX1064: v_add_co_u32 v2, vcc, s0, v2
 0x02,0x6a,0x0f,0xd7,0x00,0x04,0x02,0x00
 
 # GFX1032: v_add_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo
 # GFX1064: v_add_co_ci_u32_e32 v3, vcc, v3, v4, vcc ;
 0x03,0x09,0x06,0x50
 
-# GFX1032: v_sub_co_u32_e64 v2, vcc_lo, s0, v2
-# GFX1064: v_sub_co_u32_e64 v2, vcc, s0, v2
+# GFX1032: v_sub_co_u32 v2, vcc_lo, s0, v2
+# GFX1064: v_sub_co_u32 v2, vcc, s0, v2
 0x02,0x6a,0x10,0xd7,0x00,0x04,0x02,0x00
 
-# GFX1032: v_subrev_co_u32_e64 v2, vcc_lo, s0, v2
-# GFX1064: v_subrev_co_u32_e64 v2, vcc, s0, v2
+# GFX1032: v_subrev_co_u32 v2, vcc_lo, s0, v2
+# GFX1064: v_subrev_co_u32 v2, vcc, s0, v2
 0x02,0x6a,0x19,0xd7,0x00,0x04,0x02,0x00
 
 # GFX1032: v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v4, vcc_lo
 # GFX1064: v_sub_co_ci_u32_e32 v3, vcc, v3, v4, vcc ;
 0x03,0x09,0x06,0x52
 
 # GFX1032: v_subrev_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo
 # GFX1064: v_subrev_co_ci_u32_e32 v1, vcc, 0, v1, vcc ;

 # 0xfa,0x04,0x0a,0x52,0x01,0xe4,0x00,0x00
 
 # FIXME: gives v_lshlrev_b16_dpp
 
 # gfx1032: v_subrev_co_ci_u32_dpp v5, vcc_lo, v1, v2, vcc_lo  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 # gfx1064: v_subrev_co_ci_u32_dpp v5, vcc, v1, v2, vcc  quad_perm:[0,1,2,3] row_mask:0x0 bank_mask:0x0
 # 0xfa,0x04,0x0a,0x54,0x01,0xe4,0x00,0x00
 
-# GFX1032: v_add_co_u32_e64 v0, s0, v0, v2
-# GFX1064: v_add_co_u32_e64 v0, s[0:1], v0, v2
+# GFX1032: v_add_co_u32 v0, s0, v0, v2
+# GFX1064: v_add_co_u32 v0, s[0:1], v0, v2
 0x00,0x00,0x0f,0xd7,0x00,0x05,0x02,0x00
 
 # GFX1032: v_add_co_ci_u32_e64 v4, s0, v1, v5, s2
 # GFX1064: v_add_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
 0x04,0x00,0x28,0xd5,0x01,0x0b,0x0a,0x00
 
-# GFX1032: v_sub_co_u32_e64 v0, s0, v0, v2
-# GFX1064: v_sub_co_u32_e64 v0, s[0:1], v0, v2
+# GFX1032: v_sub_co_u32 v0, s0, v0, v2
+# GFX1064: v_sub_co_u32 v0, s[0:1], v0, v2
 0x00,0x00,0x10,0xd7,0x00,0x05,0x02,0x00
 
 # GFX1032: v_sub_co_ci_u32_e64 v4, s0, v1, v5, s2
 # GFX1064: v_sub_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
 0x04,0x00,0x29,0xd5,0x01,0x0b,0x0a,0x00
 
-# GFX1032: v_subrev_co_u32_e64 v0, s0, v0, v2
-# GFX1064: v_subrev_co_u32_e64 v0, s[0:1], v0, v2
+# GFX1032: v_subrev_co_u32 v0, s0, v0, v2
+# GFX1064: v_subrev_co_u32 v0, s[0:1], v0, v2
 0x00,0x00,0x19,0xd7,0x00,0x05,0x02,0x00
 
 # GFX1032: v_subrev_co_ci_u32_e64 v4, s0, v1, v5, s2
 # GFX1064: v_subrev_co_ci_u32_e64 v4, s[0:1], v1, v5, s[2:3]
 0x04,0x00,0x2a,0xd5,0x01,0x0b,0x0a,0x00
 
 # GFX1032: v_add_co_ci_u32_e64 v4, vcc_lo, v1, v5, s2
 # GFX1064: v_add_co_ci_u32_e64 v4, vcc, v1, v5, s[2:3]