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Differential D99267

[AMDGPU] Extend gfx10 test coverage. NFC.
ClosedPublic

Authored by Petar.Avramovic on Mar 24 2021, 7:51 AM.

Details

Reviewers
dstuttard
foad
piotr
rampitec
arsenm
Commits
rGb082e6f88acf: [AMDGPU] Extend gfx10 test coverage. NFC.

Diff Detail

Event Timeline

Petar.Avramovic created this revision.Mar 24 2021, 7:51 AM
Herald added subscribers: kerbowa, asbirlea, jfb and 6 others. · View Herald TranscriptMar 24 2021, 7:51 AM
Petar.Avramovic requested review of this revision.Mar 24 2021, 7:51 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 24 2021, 7:51 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B95490: Diff 332990.Mar 24 2021, 1:52 PM
foad accepted this revision.Mar 25 2021, 4:23 AM
foad added reviewers: rampitec, arsenm.

Seems obviously fine to me, but please wait 24 hours in case anyone else objects. It increases the size of test/CodeGen/AMDGPU/ by 24000 lines which is "only" about 2.5%.

This revision is now accepted and ready to land.Mar 25 2021, 4:23 AM
This revision was landed with ongoing or failed builds.Mar 29 2021, 2:17 AM
Closed by commit rGb082e6f88acf: [AMDGPU] Extend gfx10 test coverage. NFC. (authored by Petar.Avramovic). · Explain Why
This revision was automatically updated to reflect the committed changes.
Petar.Avramovic added a commit: rGb082e6f88acf: [AMDGPU] Extend gfx10 test coverage. NFC..

Large Diff

This large diff affects 183 files. Files without inline comments have been collapsed. Expand All Files

Revision Contents

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Diff 332990

llvm/test/CodeGen/AMDGPU/GlobalISel/add.v2i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/ashr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.large.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-local-128.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-private.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-and-or.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-or3.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcopysign.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-srem.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-urem.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fadd.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ds.fmin.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/lshr.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/mul.v2i16.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-and.mir

llvm/test/CodeGen/AMDGPU/GlobalISel/roundeven.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/shl-ext-reduce.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/shl.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/shlN_add.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll

llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll

llvm/test/CodeGen/AMDGPU/amd.endpgm.ll

llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll

llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir

llvm/test/CodeGen/AMDGPU/ctlz.ll

llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll

llvm/test/CodeGen/AMDGPU/early-term.mir

llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll

llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll

llvm/test/CodeGen/AMDGPU/fmad-formation-fmul-distribute-denormal-mode.ll

llvm/test/CodeGen/AMDGPU/fneg-fold-legalize-dag-increase-insts.ll

llvm/test/CodeGen/AMDGPU/fpow.ll

llvm/test/CodeGen/AMDGPU/frem.ll

llvm/test/CodeGen/AMDGPU/fshl.ll

llvm/test/CodeGen/AMDGPU/fshr.ll

llvm/test/CodeGen/AMDGPU/global-atomics-fp.ll

llvm/test/CodeGen/AMDGPU/gws-hazards.mir

llvm/test/CodeGen/AMDGPU/idiv-licm.ll

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll

llvm/test/CodeGen/AMDGPU/llvm.cos.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll

llvm/test/CodeGen/AMDGPU/llvm.mulo.ll

llvm/test/CodeGen/AMDGPU/llvm.sin.f16.ll

llvm/test/CodeGen/AMDGPU/load-local.128.ll

llvm/test/CodeGen/AMDGPU/load-local.96.ll

llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll

llvm/test/CodeGen/AMDGPU/ptrmask.ll

llvm/test/CodeGen/AMDGPU/saddo.ll

llvm/test/CodeGen/AMDGPU/saddsat.ll

llvm/test/CodeGen/AMDGPU/shl.v2i16.ll

llvm/test/CodeGen/AMDGPU/ssubsat.ll

llvm/test/CodeGen/AMDGPU/store-local.128.ll

llvm/test/CodeGen/AMDGPU/store-local.96.ll

llvm/test/CodeGen/AMDGPU/store-weird-sizes.ll

llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll

llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll

llvm/test/CodeGen/AMDGPU/strict_fma.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fma.f32.ll

llvm/test/CodeGen/AMDGPU/strict_fma.f64.ll

llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll

llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll

llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll

llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll

llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll

llvm/test/CodeGen/AMDGPU/sub.v2i16.ll

llvm/test/CodeGen/AMDGPU/usubsat.ll

llvm/test/CodeGen/AMDGPU/vector_shuffle.packed.ll