[RISCV] Improve 64-bit integer materialization for some cases.

[craig.topper]

Summary

This adds a new integer materialization strategy mainly targeted
at 64-bit constants like 0xffffffff where there are 32 or more trailing
ones with leading zeros. We can materialize these by using an addi -1
and srli to restore the leading zeros. This matches what gcc does.

I haven't limited to just these cases though. The implementation
here takes the constant, shifts out all the leading zeros and
shifts ones into the LSBs, creates the new sequence, adds an srli,
and checks if this is shorter than our original strategy.

I've separated the recursive portion into a standalone function
so I could append the new strategy outside of the recursion. Since
external users are no longer using the recursive function, I've
cleaned up the external interface to return the sequence instead of
taking a vector by reference.

[jrtc27]

llvm/test/CodeGen/RISCV/sadd_sat.ll

135

Hm, would be nice to not make this pattern worse

[craig.topper]

llvm/test/CodeGen/RISCV/sadd_sat.ll

124–125

This is a regression, but was suboptimal before. We have a select_cc picking between INT64_MIN and INT64_MAX. Those are only one apart with wraparound. We could just generate one constant and add/sub the result of a sltz to it to generate the other constant.

I think DAG combine would normally do that for select of constants, but the select here is created during LegalizeDAG and is turned into select_cc immediately so DAG combine never sees it.

137–138

Same here

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

132–133

And here

145–146

And here

[craig.topper]

Ping

[craig.topper]

Rebase after adding Zbt version of saturating add/sub tests.

[asb]

LGTM, left a couple of nits on comment typos. Thanks!

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

88

"And example" => "An example"

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h

28–29

Pre-existing typo you might fix while editing this: "produced" => "is produced".

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
   bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
   if (Res)
     ++RISCVNumInstrsCompressed;
   S.emitInstruction((Res ? CInst : Inst), getSTI());
 }
 
 void RISCVAsmParser::emitLoadImm(MCRegister DestReg, int64_t Value,
                                  MCStreamer &Out) {
-  RISCVMatInt::InstSeq Seq;
-  RISCVMatInt::generateInstSeq(Value, isRV64(), Seq);
+  RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Value, isRV64());
 
   MCRegister SrcReg = RISCV::X0;
   for (RISCVMatInt::Inst &Inst : Seq) {
     if (Inst.Opc == RISCV::LUI) {
       emitToStreamer(
           Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm));
     } else {
       emitToStreamer(

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.h

struct Inst {
   unsigned Opc;
   int64_t Imm;
 
   Inst(unsigned Opc, int64_t Imm) : Opc(Opc), Imm(Imm) {}
 };
 using InstSeq = SmallVector<Inst, 8>;
 
 // Helper to generate an instruction sequence that will materialise the given
-// immediate value into a register. A sequence of instructions represented by
-// a simple struct produced rather than directly emitting the instructions in
+// immediate value into a register. A sequence of instructions represented by a
+// simple struct is produced rather than directly emitting the instructions in
 // order to allow this helper to be used from both the MC layer and during
 // instruction selection.
-void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res);
+InstSeq generateInstSeq(int64_t Val, bool IsRV64);
 
 // Helper to estimate the number of instructions required to materialise the
 // given immediate value into a register. This estimate does not account for
 // `Val` possibly fitting into an immediate, and so may over-estimate.
 //
 // This will attempt to produce instructions to materialise `Val` as an
 // `Size`-bit immediate. `IsRV64` should match the target architecture.
 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64);
 } // namespace RISCVMatInt
 } // namespace llvm
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

 //===- RISCVMatInt.cpp - Immediate materialisation -------------*- C++ -*--===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "RISCVMatInt.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/ADT/APInt.h"
 #include "llvm/Support/MathExtras.h"
+using namespace llvm;
 
-namespace llvm {
-
-namespace RISCVMatInt {
-void generateInstSeq(int64_t Val, bool IsRV64, InstSeq &Res) {
+// Recursively generate a sequence for materializing an integer.
+static void generateInstSeqImpl(int64_t Val, bool IsRV64,
+                                RISCVMatInt::InstSeq &Res) {
   if (isInt<32>(Val)) {
     // Depending on the active bits in the immediate Value v, the following
     // instruction sequences are emitted:
     //
     // v == 0                        : ADDI
     // v[0,12) != 0 && v[12,32) == 0 : ADDI
     // v[0,12) == 0 && v[12,32) != 0 : LUI
     // v[0,32) != 0                  : LUI+ADDI(W)
     int64_t Hi20 = ((Val + 0x800) >> 12) & 0xFFFFF;
     int64_t Lo12 = SignExtend64<12>(Val);
 
     if (Hi20)
-      Res.push_back(Inst(RISCV::LUI, Hi20));
+      Res.push_back(RISCVMatInt::Inst(RISCV::LUI, Hi20));
 
     if (Lo12 || Hi20 == 0) {
       unsigned AddiOpc = (IsRV64 && Hi20) ? RISCV::ADDIW : RISCV::ADDI;
-      Res.push_back(Inst(AddiOpc, Lo12));
+      Res.push_back(RISCVMatInt::Inst(AddiOpc, Lo12));
     }
     return;
   }
 
   assert(IsRV64 && "Can't emit >32-bit imm for non-RV64 target");
 
   // In the worst case, for a full 64-bit constant, a sequence of 8 instructions
   // (i.e., LUI+ADDIW+SLLI+ADDI+SLLI+ADDI+SLLI+ADDI) has to be emmitted. Note
static void generateInstSeqImpl(int64_t Val, bool IsRV64,
   // fits into 32 bits. The emission of the shifts and additions is subsequently
   // performed when the recursion returns.
 
   int64_t Lo12 = SignExtend64<12>(Val);
   int64_t Hi52 = ((uint64_t)Val + 0x800ull) >> 12;
   int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
   Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
 
-  generateInstSeq(Hi52, IsRV64, Res);
+  generateInstSeqImpl(Hi52, IsRV64, Res);
 
-  Res.push_back(Inst(RISCV::SLLI, ShiftAmount));
+  Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount));
   if (Lo12)
-    Res.push_back(Inst(RISCV::ADDI, Lo12));
+    Res.push_back(RISCVMatInt::Inst(RISCV::ADDI, Lo12));
+}
+
+namespace llvm {
+namespace RISCVMatInt {
+InstSeq generateInstSeq(int64_t Val, bool IsRV64) {
+  RISCVMatInt::InstSeq Res;
+  generateInstSeqImpl(Val, IsRV64, Res);
+
+  // If the constant is positive we might be able to generate a shifted constant
+  // with no leading zeros and use a final SRLI to restore them.
+  if (Val > 0 && Res.size() > 2) {
+    assert(IsRV64 && "Expected RV32 to only need 2 instructions");
+    unsigned ShiftAmount = countLeadingZeros((uint64_t)Val);
+    Val <<= ShiftAmount;
+    // Fill in the bits that will be shifted out with 1s. An example where this
+    // helps is trailing one masks with 32 or more ones. This will generate
+    // ADDI -1 and an SRLI.
+    Val |= maskTrailingOnes<uint64_t>(ShiftAmount);
+
+    RISCVMatInt::InstSeq TmpSeq;
+    generateInstSeqImpl(Val, IsRV64, TmpSeq);
+    TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, ShiftAmount));
+
+    // Keep the new sequence if it is an improvement.
+    if (TmpSeq.size() < Res.size())
+      Res = TmpSeq;
+  }
+
+  return Res;
 }
 
 int getIntMatCost(const APInt &Val, unsigned Size, bool IsRV64) {
   int PlatRegSize = IsRV64 ? 64 : 32;
 
   // Split the constant into platform register sized chunks, and calculate cost
   // of each chunk.
   int Cost = 0;
   for (unsigned ShiftVal = 0; ShiftVal < Size; ShiftVal += PlatRegSize) {
     APInt Chunk = Val.ashr(ShiftVal).sextOrTrunc(PlatRegSize);
-    InstSeq MatSeq;
-    generateInstSeq(Chunk.getSExtValue(), IsRV64, MatSeq);
+    InstSeq MatSeq = generateInstSeq(Chunk.getSExtValue(), IsRV64);
     Cost += MatSeq.size();
   }
   return std::max(1, Cost);
 }
 } // namespace RISCVMatInt
 } // namespace llvm

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 } // namespace llvm
 
 void RISCVDAGToDAGISel::PostprocessISelDAG() {
   doPeepholeLoadStoreADDI();
 }
 
 static SDNode *selectImm(SelectionDAG *CurDAG, const SDLoc &DL, int64_t Imm,
                          MVT XLenVT) {
-  RISCVMatInt::InstSeq Seq;
-  RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64, Seq);
+  RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Imm, XLenVT == MVT::i64);
 
   SDNode *Result = nullptr;
   SDValue SrcReg = CurDAG->getRegister(RISCV::X0, XLenVT);
   for (RISCVMatInt::Inst &Inst : Seq) {
     SDValue SDImm = CurDAG->getTargetConstant(Inst.Imm, DL, XLenVT);
     if (Inst.Opc == RISCV::LUI)
       Result = CurDAG->getMachineNode(RISCV::LUI, DL, XLenVT, SDImm);
     else

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
   bool IsRV64 = MF->getSubtarget<RISCVSubtarget>().is64Bit();
   Register SrcReg = RISCV::X0;
   Register Result = MRI.createVirtualRegister(&RISCV::GPRRegClass);
   unsigned Num = 0;
 
   if (!IsRV64 && !isInt<32>(Val))
     report_fatal_error("Should only materialize 32-bit constants for RV32");
 
-  RISCVMatInt::InstSeq Seq;
-  RISCVMatInt::generateInstSeq(Val, IsRV64, Seq);
+  RISCVMatInt::InstSeq Seq = RISCVMatInt::generateInstSeq(Val, IsRV64);
   assert(Seq.size() > 0);
 
   for (RISCVMatInt::Inst &Inst : Seq) {
     // Write the final result to DstReg if it's the last instruction in the Seq.
     // Otherwise, write the result to the temp register.
     if (++Num == Seq.size())
       Result = DstReg;
 

llvm/test/CodeGen/RISCV/copysign-casts.ll

 ; RV32I-NEXT:    addi a3, a3, -1
 ; RV32I-NEXT:    and a1, a1, a3
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_promote_d_s:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    addi a2, a2, -1
+; RV64I-NEXT:    srli a2, a2, 1
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    lui a2, 524288
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a1, a1, 32
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fold_promote_d_s:

 ; RV32I-NEXT:    and a2, a2, a3
 ; RV32I-NEXT:    slli a2, a2, 16
 ; RV32I-NEXT:    or a1, a1, a2
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fold_promote_d_h:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a2, zero, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    addi a2, a2, -1
+; RV64I-NEXT:    srli a2, a2, 1
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    lui a2, 8
 ; RV64I-NEXT:    and a1, a1, a2
 ; RV64I-NEXT:    slli a1, a1, 48
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IF-LABEL: fold_promote_d_h:

llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll

 ; RV32IFD-NEXT:    lui a2, 524288
 ; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64I-LABEL: fabs:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
-; RV64I-NEXT:    slli a1, a1, 63
-; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    srli a1, a1, 1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fabs:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a1, zero, -1
-; RV64IFD-NEXT:    slli a1, a1, 63
-; RV64IFD-NEXT:    addi a1, a1, -1
+; RV64IFD-NEXT:    srli a1, a1, 1
 ; RV64IFD-NEXT:    and a0, a0, a1
 ; RV64IFD-NEXT:    ret
   %1 = call double @llvm.fabs.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.copysign.f64(double, double)
 

 ; RV32IFD-NEXT:    lw a1, 12(sp)
 ; RV32IFD-NEXT:    addi sp, sp, 16
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64I-LABEL: fcopysign_fneg:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    not a1, a1
 ; RV64I-NEXT:    addi a2, zero, -1
-; RV64I-NEXT:    slli a2, a2, 63
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    addi a2, a2, -1
+; RV64I-NEXT:    slli a3, a2, 63
+; RV64I-NEXT:    and a1, a1, a3
+; RV64I-NEXT:    srli a2, a2, 1
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcopysign_fneg:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a2, zero, -1
 ; RV64IFD-NEXT:    slli a2, a2, 63

llvm/test/CodeGen/RISCV/double-intrinsics.ll

 ; RV32IFD-NEXT:    lui a2, 524288
 ; RV32IFD-NEXT:    addi a2, a2, -1
 ; RV32IFD-NEXT:    and a1, a1, a2
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fabs_f64:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addi a1, zero, -1
-; RV64IFD-NEXT:    slli a1, a1, 63
-; RV64IFD-NEXT:    addi a1, a1, -1
+; RV64IFD-NEXT:    srli a1, a1, 1
 ; RV64IFD-NEXT:    and a0, a0, a1
 ; RV64IFD-NEXT:    ret
   %1 = call double @llvm.fabs.f64(double %a)
   ret double %1
 }
 
 declare double @llvm.minnum.f64(double, double)
 

llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll

 ; RV64F-LABEL: bitcast_double_and:
 ; RV64F:       # %bb.0:
 ; RV64F-NEXT:    addi sp, sp, -16
 ; RV64F-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64F-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; RV64F-NEXT:    mv s0, a0
 ; RV64F-NEXT:    call __adddf3@plt
 ; RV64F-NEXT:    addi a1, zero, -1
-; RV64F-NEXT:    slli a1, a1, 63
-; RV64F-NEXT:    addi a1, a1, -1
+; RV64F-NEXT:    srli a1, a1, 1
 ; RV64F-NEXT:    and a1, a0, a1
 ; RV64F-NEXT:    mv a0, s0
 ; RV64F-NEXT:    call __adddf3@plt
 ; RV64F-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
 ; RV64F-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64F-NEXT:    addi sp, sp, 16
 ; RV64F-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/imm.ll

 ; RV32I-LABEL: imm64_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a0, zero, -1
 ; RV32I-NEXT:    mv a1, zero
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm64_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a0, zero, 1
-; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    addi a0, zero, -1
+; RV64I-NEXT:    srli a0, a0, 32
 ; RV64I-NEXT:    ret
   ret i64 4294967295 ; 0xFFFF_FFFF
 }
 
 define i64 @imm64_3() nounwind {
 ; RV32I-LABEL: imm64_3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 1

 ; RV32I-NEXT:    lui a0, 1048575
 ; RV32I-NEXT:    addi a0, a0, 1
 ; RV32I-NEXT:    lui a1, 16
 ; RV32I-NEXT:    addi a1, a1, -1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: imm_right_shifted_lui_1:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    addi a0, zero, 1
-; RV64I-NEXT:    slli a0, a0, 36
-; RV64I-NEXT:    addi a0, a0, -1
-; RV64I-NEXT:    slli a0, a0, 12
-; RV64I-NEXT:    addi a0, a0, 1
+; RV64I-NEXT:    lui a0, 983072
+; RV64I-NEXT:    addiw a0, a0, -1
+; RV64I-NEXT:    srli a0, a0, 16
 ; RV64I-NEXT:    ret
   ret i64 281474976706561 ; 0xFFFF_FFFF_F001
 }
 
 define i64 @imm_right_shifted_lui_2() nounwind {
 ; RV32I-LABEL: imm_right_shifted_lui_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a0, 1048575

llvm/test/CodeGen/RISCV/rv64zbp.ll

 }
 
 define i64 @gorc16_i64(i64 %a) nounwind {
 ; RV64I-LABEL: gorc16_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 16
 ; RV64I-NEXT:    lui a2, 1048560
 ; RV64I-NEXT:    addiw a2, a2, 1
-; RV64I-NEXT:    slli a2, a2, 16
-; RV64I-NEXT:    addi a2, a2, -1
-; RV64I-NEXT:    slli a2, a2, 16
-; RV64I-NEXT:    and a1, a1, a2
-; RV64I-NEXT:    srli a2, a0, 16
-; RV64I-NEXT:    lui a3, 16
-; RV64I-NEXT:    addiw a3, a3, -1
-; RV64I-NEXT:    slli a3, a3, 16
-; RV64I-NEXT:    addi a3, a3, 1
-; RV64I-NEXT:    slli a3, a3, 16
+; RV64I-NEXT:    slli a3, a2, 16
 ; RV64I-NEXT:    addi a3, a3, -1
-; RV64I-NEXT:    and a2, a2, a3
+; RV64I-NEXT:    slli a3, a3, 16
+; RV64I-NEXT:    and a1, a1, a3
+; RV64I-NEXT:    srli a3, a0, 16
+; RV64I-NEXT:    slli a2, a2, 32
+; RV64I-NEXT:    addi a2, a2, -1
+; RV64I-NEXT:    srli a2, a2, 16
+; RV64I-NEXT:    and a2, a3, a2
 ; RV64I-NEXT:    or a0, a2, a0
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: gorc16_i64:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    orc16.w a0, a0
 ; RV64IB-NEXT:    ret

 }
 
 define i64 @grev16_i64(i64 %a) nounwind {
 ; RV64I-LABEL: grev16_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 16
 ; RV64I-NEXT:    lui a2, 1048560
 ; RV64I-NEXT:    addiw a2, a2, 1
-; RV64I-NEXT:    slli a2, a2, 16
-; RV64I-NEXT:    addi a2, a2, -1
-; RV64I-NEXT:    slli a2, a2, 16
-; RV64I-NEXT:    and a1, a1, a2
+; RV64I-NEXT:    slli a3, a2, 16
+; RV64I-NEXT:    addi a3, a3, -1
+; RV64I-NEXT:    slli a3, a3, 16
+; RV64I-NEXT:    and a1, a1, a3
 ; RV64I-NEXT:    srli a0, a0, 16
-; RV64I-NEXT:    lui a2, 16
-; RV64I-NEXT:    addiw a2, a2, -1
-; RV64I-NEXT:    slli a2, a2, 16
-; RV64I-NEXT:    addi a2, a2, 1
-; RV64I-NEXT:    slli a2, a2, 16
+; RV64I-NEXT:    slli a2, a2, 32
 ; RV64I-NEXT:    addi a2, a2, -1
+; RV64I-NEXT:    srli a2, a2, 16
 ; RV64I-NEXT:    and a0, a0, a2
 ; RV64I-NEXT:    or a0, a1, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: grev16_i64:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    rev16.w a0, a0
 ; RV64IB-NEXT:    ret

llvm/test/CodeGen/RISCV/rv64zbs.ll

; RV64IBS-NEXT:    ret
   %and = and i64 %a, -4611686018427387905
   ret i64 %and
 }
 
 define i64 @sbclri_i64_63(i64 %a) nounwind {
 ; RV64I-LABEL: sbclri_i64_63:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi a1, zero, -1
-; RV64I-NEXT:    slli a1, a1, 63
-; RV64I-NEXT:    addi a1, a1, -1
+; RV64I-NEXT:    srli a1, a1, 1
 ; RV64I-NEXT:    and a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sbclri_i64_63:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    bclri a0, a0, 63
 ; RV64IB-NEXT:    ret
 ;

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll

 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
-; RV64-NEXT:    slli a0, a0, 63
-; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v26, a0
 ; RV64-NEXT:    vsetivli a0, 2, e64,m1,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v25, v26
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <2 x i64>, <2 x i64>* %x
   %red = call i64 @llvm.vector.reduce.smin.v2i64(<2 x i64> %v)

 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v4i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vle64.v v26, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
-; RV64-NEXT:    slli a0, a0, 63
-; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 4, e64,m2,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v26, v25
 ; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <4 x i64>, <4 x i64>* %x

 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v8i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vle64.v v28, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
-; RV64-NEXT:    slli a0, a0, 63
-; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v28, v25
 ; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <8 x i64>, <8 x i64>* %x

 ; RV32-NEXT:    vmv.x.s a1, v25
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vreduce_smin_v16i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, zero, -1
-; RV64-NEXT:    slli a0, a0, 63
-; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
 ; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <16 x i64>, <16 x i64>* %x

 ; RV64-LABEL: vreduce_smin_v32i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vle64.v v8, (a0)
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v16, (a0)
 ; RV64-NEXT:    vmin.vv v8, v8, v16
 ; RV64-NEXT:    addi a0, zero, -1
-; RV64-NEXT:    slli a0, a0, 63
-; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
 ; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <32 x i64>, <32 x i64>* %x

 ; RV64-NEXT:    addi a1, a0, 256
 ; RV64-NEXT:    addi a0, a0, 128
 ; RV64-NEXT:    vle64.v v24, (a0)
 ; RV64-NEXT:    vle64.v v0, (a1)
 ; RV64-NEXT:    vmin.vv v16, v24, v16
 ; RV64-NEXT:    vmin.vv v8, v8, v0
 ; RV64-NEXT:    vmin.vv v8, v8, v16
 ; RV64-NEXT:    addi a0, zero, -1
-; RV64-NEXT:    slli a0, a0, 63
-; RV64-NEXT:    addi a0, a0, -1
+; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.v.x v25, a0
 ; RV64-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
 ; RV64-NEXT:    vredmin.vs v25, v8, v25
 ; RV64-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; RV64-NEXT:    vmv.x.s a0, v25
 ; RV64-NEXT:    ret
   %v = load <64 x i64>, <64 x i64>* %x

llvm/test/CodeGen/RISCV/rvv/vreductions-int-rv64.ll

 }
 
 declare i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64>)
 
 define i64 @vreduce_smin_nxv1i64(<vscale x 1 x i64> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv1i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -1
-; CHECK-NEXT:    slli a0, a0, 63
-; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    srli a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv1i64(<vscale x 1 x i64> %v)
   ret i64 %red
 }

 }
 
 declare i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64>)
 
 define i64 @vreduce_smin_nxv2i64(<vscale x 2 x i64> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv2i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -1
-; CHECK-NEXT:    slli a0, a0, 63
-; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    srli a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m2,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv2i64(<vscale x 2 x i64> %v)

 }
 
 declare i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64>)
 
 define i64 @vreduce_smin_nxv4i64(<vscale x 4 x i64> %v) {
 ; CHECK-LABEL: vreduce_smin_nxv4i64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    addi a0, zero, -1
-; CHECK-NEXT:    slli a0, a0, 63
-; CHECK-NEXT:    addi a0, a0, -1
+; CHECK-NEXT:    srli a0, a0, 1
 ; CHECK-NEXT:    vsetvli a1, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.v.x v25, a0
 ; CHECK-NEXT:    vsetvli a0, zero, e64,m4,ta,mu
 ; CHECK-NEXT:    vredmin.vs v25, v8, v25
 ; CHECK-NEXT:    vsetvli zero, zero, e64,m1,ta,mu
 ; CHECK-NEXT:    vmv.x.s a0, v25
 ; CHECK-NEXT:    ret
   %red = call i64 @llvm.vector.reduce.smin.nxv4i64(<vscale x 4 x i64> %v)

llvm/test/CodeGen/RISCV/sadd_sat.ll

 ; RV32I-NEXT:    mv a1, a2
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB1_4:
 ; RV32I-NEXT:    srai a0, a2, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    add a3, a0, a1
-; RV64I-NEXT:    addi a0, zero, -1
-; RV64I-NEXT:    slli a0, a0, 63
-; RV64I-NEXT:    bgez a3, .LBB1_2
+; RV64I-NEXT:    addi a2, zero, -1
+; RV64I-NEXT:    bltz a3, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    slli a2, a2, 63
+; RV64I-NEXT:    j .LBB1_3
 ; RV64I-NEXT:  .LBB1_2:
-; RV64I-NEXT:    slt a2, a3, a2
+; RV64I-NEXT:    srli a2, a2, 1
+; RV64I-NEXT:  .LBB1_3:
+; RV64I-NEXT:    slt a0, a3, a0
 ; RV64I-NEXT:    slti a1, a1, 0
-; RV64I-NEXT:    bne a1, a2, .LBB1_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    mv a0, a3
-; RV64I-NEXT:  .LBB1_4:
+; RV64I-NEXT:    bne a1, a0, .LBB1_5
+; RV64I-NEXT:  # %bb.4:
+; RV64I-NEXT:    mv a2, a3
+; RV64I-NEXT:  .LBB1_5:
+; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbbNOZbt-LABEL: func2:
 ; RV32IZbbNOZbt:       # %bb.0:
 ; RV32IZbbNOZbt-NEXT:    mv a4, a1
 ; RV32IZbbNOZbt-NEXT:    mv a1, a0
 ; RV32IZbbNOZbt-NEXT:    add a5, a4, a3
 ; RV32IZbbNOZbt-NEXT:    add a0, a0, a2
 ; RV32IZbbNOZbt-NEXT:    sltu a1, a0, a1
 ; RV32IZbbNOZbt-NEXT:    add a2, a5, a1
 ; RV32IZbbNOZbt-NEXT:    lui a1, 524288

 ; RV32IZbbNOZbt-NEXT:    mv a1, a2
 ; RV32IZbbNOZbt-NEXT:    ret
 ; RV32IZbbNOZbt-NEXT:  .LBB1_4:
 ; RV32IZbbNOZbt-NEXT:    srai a0, a2, 31
 ; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbbNOZbt-LABEL: func2:
 ; RV64IZbbNOZbt:       # %bb.0:
-; RV64IZbbNOZbt-NEXT:    mv a2, a0
 ; RV64IZbbNOZbt-NEXT:    add a3, a0, a1
-; RV64IZbbNOZbt-NEXT:    addi a0, zero, -1
-; RV64IZbbNOZbt-NEXT:    slli a0, a0, 63
-; RV64IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV64IZbbNOZbt-NEXT:    addi a2, zero, -1
+; RV64IZbbNOZbt-NEXT:    bltz a3, .LBB1_2
 ; RV64IZbbNOZbt-NEXT:  # %bb.1:
-; RV64IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV64IZbbNOZbt-NEXT:    slli a2, a2, 63
+; RV64IZbbNOZbt-NEXT:    j .LBB1_3
 ; RV64IZbbNOZbt-NEXT:  .LBB1_2:
-; RV64IZbbNOZbt-NEXT:    slt a2, a3, a2
+; RV64IZbbNOZbt-NEXT:    srli a2, a2, 1
+; RV64IZbbNOZbt-NEXT:  .LBB1_3:
+; RV64IZbbNOZbt-NEXT:    slt a0, a3, a0
 ; RV64IZbbNOZbt-NEXT:    slti a1, a1, 0
-; RV64IZbbNOZbt-NEXT:    bne a1, a2, .LBB1_4
-; RV64IZbbNOZbt-NEXT:  # %bb.3:
-; RV64IZbbNOZbt-NEXT:    mv a0, a3
-; RV64IZbbNOZbt-NEXT:  .LBB1_4:
+; RV64IZbbNOZbt-NEXT:    bne a1, a0, .LBB1_5
+; RV64IZbbNOZbt-NEXT:  # %bb.4:
+; RV64IZbbNOZbt-NEXT:    mv a2, a3
+; RV64IZbbNOZbt-NEXT:  .LBB1_5:
+; RV64IZbbNOZbt-NEXT:    mv a0, a2
 ; RV64IZbbNOZbt-NEXT:    ret
 ;
 ; RV32IZbbZbt-LABEL: func2:
 ; RV32IZbbZbt:       # %bb.0:
 ; RV32IZbbZbt-NEXT:    add a4, a1, a3
 ; RV32IZbbZbt-NEXT:    add a2, a0, a2
 ; RV32IZbbZbt-NEXT:    sltu a0, a2, a0
 ; RV32IZbbZbt-NEXT:    add a0, a4, a0

 ; RV32IZbbZbt-NEXT:    cmov a0, a3, a0, a2
 ; RV32IZbbZbt-NEXT:    ret
 ;
 ; RV64IZbbZbt-LABEL: func2:
 ; RV64IZbbZbt:       # %bb.0:
 ; RV64IZbbZbt-NEXT:    add a2, a0, a1
 ; RV64IZbbZbt-NEXT:    slti a3, a2, 0
 ; RV64IZbbZbt-NEXT:    addi a4, zero, -1
-; RV64IZbbZbt-NEXT:    slli a4, a4, 63
-; RV64IZbbZbt-NEXT:    addi a5, a4, -1
-; RV64IZbbZbt-NEXT:    cmov a3, a3, a5, a4
+; RV64IZbbZbt-NEXT:    slli a5, a4, 63
+; RV64IZbbZbt-NEXT:    srli a4, a4, 1
+; RV64IZbbZbt-NEXT:    cmov a3, a3, a4, a5
 ; RV64IZbbZbt-NEXT:    slt a0, a2, a0
 ; RV64IZbbZbt-NEXT:    slti a1, a1, 0
 ; RV64IZbbZbt-NEXT:    xor a0, a1, a0
 ; RV64IZbbZbt-NEXT:    cmov a0, a0, a3, a2
 ; RV64IZbbZbt-NEXT:    ret
   %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }

llvm/test/CodeGen/RISCV/sadd_sat_plus.ll

 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB1_4:
 ; RV32I-NEXT:    srai a0, a3, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    add a3, a0, a2
-; RV64I-NEXT:    addi a0, zero, -1
-; RV64I-NEXT:    slli a0, a0, 63
-; RV64I-NEXT:    bgez a3, .LBB1_2
+; RV64I-NEXT:    addi a1, zero, -1
+; RV64I-NEXT:    bltz a3, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    slli a1, a1, 63
+; RV64I-NEXT:    j .LBB1_3
 ; RV64I-NEXT:  .LBB1_2:
-; RV64I-NEXT:    slt a1, a3, a1
+; RV64I-NEXT:    srli a1, a1, 1
+; RV64I-NEXT:  .LBB1_3:
+; RV64I-NEXT:    slt a0, a3, a0
 ; RV64I-NEXT:    slti a2, a2, 0
-; RV64I-NEXT:    bne a2, a1, .LBB1_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    mv a0, a3
-; RV64I-NEXT:  .LBB1_4:
+; RV64I-NEXT:    bne a2, a0, .LBB1_5
+; RV64I-NEXT:  # %bb.4:
+; RV64I-NEXT:    mv a1, a3
+; RV64I-NEXT:  .LBB1_5:
+; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbbNOZbt-LABEL: func64:
 ; RV32IZbbNOZbt:       # %bb.0:
 ; RV32IZbbNOZbt-NEXT:    mv a2, a1
 ; RV32IZbbNOZbt-NEXT:    mv a1, a0
 ; RV32IZbbNOZbt-NEXT:    add a3, a2, a5
 ; RV32IZbbNOZbt-NEXT:    add a0, a0, a4
 ; RV32IZbbNOZbt-NEXT:    sltu a1, a0, a1
 ; RV32IZbbNOZbt-NEXT:    add a3, a3, a1
 ; RV32IZbbNOZbt-NEXT:    lui a1, 524288

 ; RV32IZbbNOZbt-NEXT:    mv a1, a3
 ; RV32IZbbNOZbt-NEXT:    ret
 ; RV32IZbbNOZbt-NEXT:  .LBB1_4:
 ; RV32IZbbNOZbt-NEXT:    srai a0, a3, 31
 ; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbbNOZbt-LABEL: func64:
 ; RV64IZbbNOZbt:       # %bb.0:
-; RV64IZbbNOZbt-NEXT:    mv a1, a0
 ; RV64IZbbNOZbt-NEXT:    add a3, a0, a2
-; RV64IZbbNOZbt-NEXT:    addi a0, zero, -1
-; RV64IZbbNOZbt-NEXT:    slli a0, a0, 63
-; RV64IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV64IZbbNOZbt-NEXT:    addi a1, zero, -1
+; RV64IZbbNOZbt-NEXT:    bltz a3, .LBB1_2
 ; RV64IZbbNOZbt-NEXT:  # %bb.1:
-; RV64IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV64IZbbNOZbt-NEXT:    slli a1, a1, 63
+; RV64IZbbNOZbt-NEXT:    j .LBB1_3
 ; RV64IZbbNOZbt-NEXT:  .LBB1_2:
-; RV64IZbbNOZbt-NEXT:    slt a1, a3, a1
+; RV64IZbbNOZbt-NEXT:    srli a1, a1, 1
+; RV64IZbbNOZbt-NEXT:  .LBB1_3:
+; RV64IZbbNOZbt-NEXT:    slt a0, a3, a0
 ; RV64IZbbNOZbt-NEXT:    slti a2, a2, 0
-; RV64IZbbNOZbt-NEXT:    bne a2, a1, .LBB1_4
-; RV64IZbbNOZbt-NEXT:  # %bb.3:
-; RV64IZbbNOZbt-NEXT:    mv a0, a3
-; RV64IZbbNOZbt-NEXT:  .LBB1_4:
+; RV64IZbbNOZbt-NEXT:    bne a2, a0, .LBB1_5
+; RV64IZbbNOZbt-NEXT:  # %bb.4:
+; RV64IZbbNOZbt-NEXT:    mv a1, a3
+; RV64IZbbNOZbt-NEXT:  .LBB1_5:
+; RV64IZbbNOZbt-NEXT:    mv a0, a1
 ; RV64IZbbNOZbt-NEXT:    ret
 ;
 ; RV32IZbbZbt-LABEL: func64:
 ; RV32IZbbZbt:       # %bb.0:
 ; RV32IZbbZbt-NEXT:    add a2, a1, a5
 ; RV32IZbbZbt-NEXT:    add a3, a0, a4
 ; RV32IZbbZbt-NEXT:    sltu a0, a3, a0
 ; RV32IZbbZbt-NEXT:    add a0, a2, a0

 ; RV32IZbbZbt-NEXT:    cmov a0, a4, a0, a3
 ; RV32IZbbZbt-NEXT:    ret
 ;
 ; RV64IZbbZbt-LABEL: func64:
 ; RV64IZbbZbt:       # %bb.0:
 ; RV64IZbbZbt-NEXT:    add a1, a0, a2
 ; RV64IZbbZbt-NEXT:    slti a3, a1, 0
 ; RV64IZbbZbt-NEXT:    addi a4, zero, -1
-; RV64IZbbZbt-NEXT:    slli a4, a4, 63
-; RV64IZbbZbt-NEXT:    addi a5, a4, -1
-; RV64IZbbZbt-NEXT:    cmov a3, a3, a5, a4
+; RV64IZbbZbt-NEXT:    slli a5, a4, 63
+; RV64IZbbZbt-NEXT:    srli a4, a4, 1
+; RV64IZbbZbt-NEXT:    cmov a3, a3, a4, a5
 ; RV64IZbbZbt-NEXT:    slt a0, a1, a0
 ; RV64IZbbZbt-NEXT:    slti a2, a2, 0
 ; RV64IZbbZbt-NEXT:    xor a0, a2, a0
 ; RV64IZbbZbt-NEXT:    cmov a0, a0, a3, a1
 ; RV64IZbbZbt-NEXT:    ret
   %a = mul i64 %y, %z
   %tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %z)
   ret i64 %tmp

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

 ; RV64-NEXT:    sd s3, 24(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s4, 16(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s5, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    mv s0, a0
 ; RV64-NEXT:    lb a0, 12(a0)
 ; RV64-NEXT:    lwu a1, 8(s0)
 ; RV64-NEXT:    slli a0, a0, 32
 ; RV64-NEXT:    or a0, a1, a0
-; RV64-NEXT:    addi s4, zero, 1
-; RV64-NEXT:    slli a1, s4, 40
-; RV64-NEXT:    addi a1, a1, -1
+; RV64-NEXT:    addi s4, zero, -1
+; RV64-NEXT:    srli a1, s4, 24
 ; RV64-NEXT:    and a0, a0, a1
 ; RV64-NEXT:    ld a1, 0(s0)
 ; RV64-NEXT:    slli a2, a0, 29
 ; RV64-NEXT:    srai s1, a2, 31
 ; RV64-NEXT:    slli a0, a0, 31
 ; RV64-NEXT:    srli a2, a1, 33
 ; RV64-NEXT:    or a0, a2, a0
 ; RV64-NEXT:    slli a0, a0, 31

 ; RV64-NEXT:    neg a0, a0
 ; RV64-NEXT:    neg a2, a2
 ; RV64-NEXT:    neg a3, a1
 ; RV64-NEXT:    slli a4, s5, 32
 ; RV64-NEXT:    and a3, a3, a4
 ; RV64-NEXT:    srli a3, a3, 32
 ; RV64-NEXT:    sb a3, 12(s0)
 ; RV64-NEXT:    slli a1, a1, 2
-; RV64-NEXT:    slli a3, s4, 33
-; RV64-NEXT:    addi a3, a3, -1
+; RV64-NEXT:    srli a3, s4, 31
 ; RV64-NEXT:    and a2, a2, a3
 ; RV64-NEXT:    srli a4, a2, 31
 ; RV64-NEXT:    sub a1, a4, a1
 ; RV64-NEXT:    sw a1, 8(s0)
 ; RV64-NEXT:    and a0, a0, a3
 ; RV64-NEXT:    slli a1, a2, 33
 ; RV64-NEXT:    or a0, a0, a1
 ; RV64-NEXT:    sd a0, 0(s0)

 ; RV32M-NEXT:    ret
 ;
 ; RV64M-LABEL: test_srem_vec:
 ; RV64M:       # %bb.0:
 ; RV64M-NEXT:    lb a1, 12(a0)
 ; RV64M-NEXT:    lwu a2, 8(a0)
 ; RV64M-NEXT:    slli a1, a1, 32
 ; RV64M-NEXT:    or a2, a2, a1
-; RV64M-NEXT:    addi a6, zero, 1
-; RV64M-NEXT:    slli a3, a6, 40
-; RV64M-NEXT:    addi a3, a3, -1
+; RV64M-NEXT:    addi a6, zero, -1
+; RV64M-NEXT:    srli a3, a6, 24
 ; RV64M-NEXT:    and a2, a2, a3
 ; RV64M-NEXT:    ld a3, 0(a0)
 ; RV64M-NEXT:    slli a4, a2, 29
 ; RV64M-NEXT:    srai a4, a4, 31
 ; RV64M-NEXT:    slli a2, a2, 31
 ; RV64M-NEXT:    srli a5, a3, 33
 ; RV64M-NEXT:    or a2, a5, a2
 ; RV64M-NEXT:    slli a2, a2, 31

 ; RV64M-NEXT:    neg a4, a2
 ; RV64M-NEXT:    neg a3, a3
 ; RV64M-NEXT:    addi a5, zero, 7
 ; RV64M-NEXT:    slli a5, a5, 32
 ; RV64M-NEXT:    and a4, a4, a5
 ; RV64M-NEXT:    srli a4, a4, 32
 ; RV64M-NEXT:    sb a4, 12(a0)
 ; RV64M-NEXT:    slli a2, a2, 2
-; RV64M-NEXT:    slli a4, a6, 33
-; RV64M-NEXT:    addi a4, a4, -1
+; RV64M-NEXT:    srli a4, a6, 31
 ; RV64M-NEXT:    and a1, a1, a4
 ; RV64M-NEXT:    srli a5, a1, 31
 ; RV64M-NEXT:    sub a2, a5, a2
 ; RV64M-NEXT:    sw a2, 8(a0)
 ; RV64M-NEXT:    slli a1, a1, 33
 ; RV64M-NEXT:    and a2, a3, a4
 ; RV64M-NEXT:    or a1, a2, a1
 ; RV64M-NEXT:    sd a1, 0(a0)

 ; RV64MV-NEXT:    sd ra, 56(sp) # 8-byte Folded Spill
 ; RV64MV-NEXT:    sd s0, 48(sp) # 8-byte Folded Spill
 ; RV64MV-NEXT:    addi s0, sp, 64
 ; RV64MV-NEXT:    andi sp, sp, -32
 ; RV64MV-NEXT:    lb a1, 12(a0)
 ; RV64MV-NEXT:    lwu a2, 8(a0)
 ; RV64MV-NEXT:    slli a1, a1, 32
 ; RV64MV-NEXT:    or a2, a2, a1
-; RV64MV-NEXT:    addi a6, zero, 1
-; RV64MV-NEXT:    slli a3, a6, 40
-; RV64MV-NEXT:    ld a4, 0(a0)
-; RV64MV-NEXT:    addi a3, a3, -1
-; RV64MV-NEXT:    and a2, a2, a3
-; RV64MV-NEXT:    slli a3, a2, 31
-; RV64MV-NEXT:    srli a5, a4, 33
-; RV64MV-NEXT:    or a3, a5, a3
-; RV64MV-NEXT:    slli a3, a3, 31
-; RV64MV-NEXT:    srai a3, a3, 31
-; RV64MV-NEXT:    slli a2, a2, 29
-; RV64MV-NEXT:    srai a2, a2, 31
+; RV64MV-NEXT:    addi a6, zero, -1
+; RV64MV-NEXT:    ld a3, 0(a0)
+; RV64MV-NEXT:    srli a4, a6, 24
+; RV64MV-NEXT:    and a2, a2, a4
+; RV64MV-NEXT:    slli a4, a2, 31
+; RV64MV-NEXT:    srli a5, a3, 33
+; RV64MV-NEXT:    or a4, a5, a4
 ; RV64MV-NEXT:    slli a4, a4, 31
 ; RV64MV-NEXT:    srai a4, a4, 31
+; RV64MV-NEXT:    slli a2, a2, 29
+; RV64MV-NEXT:    srai a2, a2, 31
+; RV64MV-NEXT:    slli a3, a3, 31
+; RV64MV-NEXT:    srai a3, a3, 31
 ; RV64MV-NEXT:    lui a5, 10923
 ; RV64MV-NEXT:    addiw a5, a5, -1365
 ; RV64MV-NEXT:    slli a5, a5, 12
 ; RV64MV-NEXT:    addi a5, a5, -1365
 ; RV64MV-NEXT:    slli a5, a5, 12
 ; RV64MV-NEXT:    addi a5, a5, -1365
 ; RV64MV-NEXT:    slli a5, a5, 12
 ; RV64MV-NEXT:    addi a5, a5, -1365
-; RV64MV-NEXT:    mulh a5, a4, a5
+; RV64MV-NEXT:    mulh a5, a3, a5
 ; RV64MV-NEXT:    srli a1, a5, 63
 ; RV64MV-NEXT:    add a1, a5, a1
 ; RV64MV-NEXT:    addi a5, zero, 6
 ; RV64MV-NEXT:    mul a1, a1, a5
-; RV64MV-NEXT:    sub a1, a4, a1
+; RV64MV-NEXT:    sub a1, a3, a1
 ; RV64MV-NEXT:    sd a1, 0(sp)
 ; RV64MV-NEXT:    lui a1, 1035469
 ; RV64MV-NEXT:    addiw a1, a1, -819
 ; RV64MV-NEXT:    slli a1, a1, 12
 ; RV64MV-NEXT:    addi a1, a1, -819
 ; RV64MV-NEXT:    slli a1, a1, 12
 ; RV64MV-NEXT:    addi a1, a1, -819
 ; RV64MV-NEXT:    slli a1, a1, 13
 ; RV64MV-NEXT:    addi a1, a1, -1639
 ; RV64MV-NEXT:    mulh a1, a2, a1
-; RV64MV-NEXT:    srli a4, a1, 63
+; RV64MV-NEXT:    srli a3, a1, 63
 ; RV64MV-NEXT:    srai a1, a1, 1
-; RV64MV-NEXT:    add a1, a1, a4
-; RV64MV-NEXT:    slli a4, a1, 2
-; RV64MV-NEXT:    add a1, a4, a1
+; RV64MV-NEXT:    add a1, a1, a3
+; RV64MV-NEXT:    slli a3, a1, 2
+; RV64MV-NEXT:    add a1, a3, a1
 ; RV64MV-NEXT:    add a1, a2, a1
 ; RV64MV-NEXT:    sd a1, 16(sp)
 ; RV64MV-NEXT:    lui a1, 18725
 ; RV64MV-NEXT:    addiw a1, a1, -1755
 ; RV64MV-NEXT:    slli a1, a1, 12
 ; RV64MV-NEXT:    addi a1, a1, -1755
 ; RV64MV-NEXT:    slli a1, a1, 12
 ; RV64MV-NEXT:    addi a1, a1, -1755
 ; RV64MV-NEXT:    slli a1, a1, 12
 ; RV64MV-NEXT:    addi a1, a1, -1755
-; RV64MV-NEXT:    mulh a1, a3, a1
+; RV64MV-NEXT:    mulh a1, a4, a1
 ; RV64MV-NEXT:    srli a2, a1, 63
 ; RV64MV-NEXT:    srai a1, a1, 1
 ; RV64MV-NEXT:    add a1, a1, a2
 ; RV64MV-NEXT:    slli a2, a1, 3
 ; RV64MV-NEXT:    sub a1, a1, a2
-; RV64MV-NEXT:    add a1, a3, a1
+; RV64MV-NEXT:    add a1, a4, a1
 ; RV64MV-NEXT:    sd a1, 8(sp)
 ; RV64MV-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
 ; RV64MV-NEXT:    vle64.v v26, (sp)
 ; RV64MV-NEXT:    lui a1, %hi(.LCPI3_0)
 ; RV64MV-NEXT:    addi a1, a1, %lo(.LCPI3_0)
 ; RV64MV-NEXT:    vle64.v v28, (a1)
-; RV64MV-NEXT:    slli a1, a6, 33
-; RV64MV-NEXT:    addi a1, a1, -1
+; RV64MV-NEXT:    srli a1, a6, 31
 ; RV64MV-NEXT:    vand.vx v26, v26, a1
 ; RV64MV-NEXT:    vmsne.vv v0, v26, v28
 ; RV64MV-NEXT:    vmv.v.i v26, 0
 ; RV64MV-NEXT:    vmerge.vim v26, v26, -1, v0
 ; RV64MV-NEXT:    vsetivli a2, 1, e64,m2,ta,mu
 ; RV64MV-NEXT:    vslidedown.vi v28, v26, 2
 ; RV64MV-NEXT:    vmv.x.s a2, v28
 ; RV64MV-NEXT:    srli a3, a2, 30

llvm/test/CodeGen/RISCV/srem-vector-lkk.ll

 ; RV64IM-NEXT:    mulh a5, a1, a5
 ; RV64IM-NEXT:    add a5, a5, a1
 ; RV64IM-NEXT:    srli a2, a5, 63
 ; RV64IM-NEXT:    srli a5, a5, 6
 ; RV64IM-NEXT:    add a2, a5, a2
 ; RV64IM-NEXT:    addi a5, zero, 95
 ; RV64IM-NEXT:    mul a2, a2, a5
 ; RV64IM-NEXT:    sub a1, a1, a2
-; RV64IM-NEXT:    lui a2, 248
+; RV64IM-NEXT:    lui a2, 777976
 ; RV64IM-NEXT:    addiw a2, a2, -1057
 ; RV64IM-NEXT:    slli a2, a2, 15
 ; RV64IM-NEXT:    addi a2, a2, -1057
-; RV64IM-NEXT:    slli a2, a2, 15
-; RV64IM-NEXT:    addi a2, a2, -1057
-; RV64IM-NEXT:    slli a2, a2, 13
-; RV64IM-NEXT:    addi a2, a2, -265
+; RV64IM-NEXT:    slli a2, a2, 14
+; RV64IM-NEXT:    addi a2, a2, -529
+; RV64IM-NEXT:    srli a2, a2, 1
 ; RV64IM-NEXT:    mulh a2, a4, a2
 ; RV64IM-NEXT:    sub a2, a2, a4
 ; RV64IM-NEXT:    srli a5, a2, 63
 ; RV64IM-NEXT:    srli a2, a2, 6
 ; RV64IM-NEXT:    add a2, a2, a5
 ; RV64IM-NEXT:    addi a5, zero, -124
 ; RV64IM-NEXT:    mul a2, a2, a5
 ; RV64IM-NEXT:    sub a2, a4, a2

llvm/test/CodeGen/RISCV/ssub_sat.ll

 ; RV32I-NEXT:    mv a1, a5
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB1_4:
 ; RV32I-NEXT:    srai a0, a5, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a2, a0
 ; RV64I-NEXT:    sub a3, a0, a1
-; RV64I-NEXT:    addi a0, zero, -1
-; RV64I-NEXT:    slli a0, a0, 63
-; RV64I-NEXT:    bgez a3, .LBB1_2
+; RV64I-NEXT:    addi a2, zero, -1
+; RV64I-NEXT:    bltz a3, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    slli a2, a2, 63
+; RV64I-NEXT:    j .LBB1_3
 ; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    srli a2, a2, 1
+; RV64I-NEXT:  .LBB1_3:
 ; RV64I-NEXT:    sgtz a1, a1
-; RV64I-NEXT:    slt a2, a3, a2
-; RV64I-NEXT:    bne a1, a2, .LBB1_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    mv a0, a3
-; RV64I-NEXT:  .LBB1_4:
+; RV64I-NEXT:    slt a0, a3, a0
+; RV64I-NEXT:    bne a1, a0, .LBB1_5
+; RV64I-NEXT:  # %bb.4:
+; RV64I-NEXT:    mv a2, a3
+; RV64I-NEXT:  .LBB1_5:
+; RV64I-NEXT:    mv a0, a2
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbbNOZbt-LABEL: func2:
 ; RV32IZbbNOZbt:       # %bb.0:
 ; RV32IZbbNOZbt-NEXT:    mv a4, a1
 ; RV32IZbbNOZbt-NEXT:    sltu a1, a0, a2
 ; RV32IZbbNOZbt-NEXT:    sub a5, a4, a3
 ; RV32IZbbNOZbt-NEXT:    sub a5, a5, a1

 ; RV32IZbbNOZbt-NEXT:    mv a1, a5
 ; RV32IZbbNOZbt-NEXT:    ret
 ; RV32IZbbNOZbt-NEXT:  .LBB1_4:
 ; RV32IZbbNOZbt-NEXT:    srai a0, a5, 31
 ; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbbNOZbt-LABEL: func2:
 ; RV64IZbbNOZbt:       # %bb.0:
-; RV64IZbbNOZbt-NEXT:    mv a2, a0
 ; RV64IZbbNOZbt-NEXT:    sub a3, a0, a1
-; RV64IZbbNOZbt-NEXT:    addi a0, zero, -1
-; RV64IZbbNOZbt-NEXT:    slli a0, a0, 63
-; RV64IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV64IZbbNOZbt-NEXT:    addi a2, zero, -1
+; RV64IZbbNOZbt-NEXT:    bltz a3, .LBB1_2
 ; RV64IZbbNOZbt-NEXT:  # %bb.1:
-; RV64IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV64IZbbNOZbt-NEXT:    slli a2, a2, 63
+; RV64IZbbNOZbt-NEXT:    j .LBB1_3
 ; RV64IZbbNOZbt-NEXT:  .LBB1_2:
+; RV64IZbbNOZbt-NEXT:    srli a2, a2, 1
+; RV64IZbbNOZbt-NEXT:  .LBB1_3:
 ; RV64IZbbNOZbt-NEXT:    sgtz a1, a1
-; RV64IZbbNOZbt-NEXT:    slt a2, a3, a2
-; RV64IZbbNOZbt-NEXT:    bne a1, a2, .LBB1_4
-; RV64IZbbNOZbt-NEXT:  # %bb.3:
-; RV64IZbbNOZbt-NEXT:    mv a0, a3
-; RV64IZbbNOZbt-NEXT:  .LBB1_4:
+; RV64IZbbNOZbt-NEXT:    slt a0, a3, a0
+; RV64IZbbNOZbt-NEXT:    bne a1, a0, .LBB1_5
+; RV64IZbbNOZbt-NEXT:  # %bb.4:
+; RV64IZbbNOZbt-NEXT:    mv a2, a3
+; RV64IZbbNOZbt-NEXT:  .LBB1_5:
+; RV64IZbbNOZbt-NEXT:    mv a0, a2
 ; RV64IZbbNOZbt-NEXT:    ret
 ;
 ; RV32IZbbZbt-LABEL: func2:
 ; RV32IZbbZbt:       # %bb.0:
 ; RV32IZbbZbt-NEXT:    sltu a4, a0, a2
 ; RV32IZbbZbt-NEXT:    sub a5, a1, a3
 ; RV32IZbbZbt-NEXT:    sub a4, a5, a4
 ; RV32IZbbZbt-NEXT:    slti a7, a4, 0

 ; RV64IZbbZbt-LABEL: func2:
 ; RV64IZbbZbt:       # %bb.0:
 ; RV64IZbbZbt-NEXT:    sgtz a2, a1
 ; RV64IZbbZbt-NEXT:    sub a1, a0, a1
 ; RV64IZbbZbt-NEXT:    slt a0, a1, a0
 ; RV64IZbbZbt-NEXT:    xor a0, a2, a0
 ; RV64IZbbZbt-NEXT:    slti a2, a1, 0
 ; RV64IZbbZbt-NEXT:    addi a3, zero, -1
-; RV64IZbbZbt-NEXT:    slli a3, a3, 63
-; RV64IZbbZbt-NEXT:    addi a4, a3, -1
-; RV64IZbbZbt-NEXT:    cmov a2, a2, a4, a3
+; RV64IZbbZbt-NEXT:    slli a4, a3, 63
+; RV64IZbbZbt-NEXT:    srli a3, a3, 1
+; RV64IZbbZbt-NEXT:    cmov a2, a2, a3, a4
 ; RV64IZbbZbt-NEXT:    cmov a0, a0, a2, a1
 ; RV64IZbbZbt-NEXT:    ret
   %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %y);
   ret i64 %tmp;
 }
 
 define signext i16 @func16(i16 signext %x, i16 signext %y) nounwind {
 ; RV32I-LABEL: func16:

llvm/test/CodeGen/RISCV/ssub_sat_plus.ll

 ; RV32I-NEXT:    mv a1, a3
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB1_4:
 ; RV32I-NEXT:    srai a0, a3, 31
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: func64:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    mv a1, a0
 ; RV64I-NEXT:    sub a3, a0, a2
-; RV64I-NEXT:    addi a0, zero, -1
-; RV64I-NEXT:    slli a0, a0, 63
-; RV64I-NEXT:    bgez a3, .LBB1_2
+; RV64I-NEXT:    addi a1, zero, -1
+; RV64I-NEXT:    bltz a3, .LBB1_2
 ; RV64I-NEXT:  # %bb.1:
-; RV64I-NEXT:    addi a0, a0, -1
+; RV64I-NEXT:    slli a1, a1, 63
+; RV64I-NEXT:    j .LBB1_3
 ; RV64I-NEXT:  .LBB1_2:
+; RV64I-NEXT:    srli a1, a1, 1
+; RV64I-NEXT:  .LBB1_3:
 ; RV64I-NEXT:    sgtz a2, a2
-; RV64I-NEXT:    slt a1, a3, a1
-; RV64I-NEXT:    bne a2, a1, .LBB1_4
-; RV64I-NEXT:  # %bb.3:
-; RV64I-NEXT:    mv a0, a3
-; RV64I-NEXT:  .LBB1_4:
+; RV64I-NEXT:    slt a0, a3, a0
+; RV64I-NEXT:    bne a2, a0, .LBB1_5
+; RV64I-NEXT:  # %bb.4:
+; RV64I-NEXT:    mv a1, a3
+; RV64I-NEXT:  .LBB1_5:
+; RV64I-NEXT:    mv a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV32IZbbNOZbt-LABEL: func64:
 ; RV32IZbbNOZbt:       # %bb.0:
 ; RV32IZbbNOZbt-NEXT:    mv a2, a1
 ; RV32IZbbNOZbt-NEXT:    sltu a1, a0, a4
 ; RV32IZbbNOZbt-NEXT:    sub a3, a2, a5
 ; RV32IZbbNOZbt-NEXT:    sub a3, a3, a1

 ; RV32IZbbNOZbt-NEXT:    mv a1, a3
 ; RV32IZbbNOZbt-NEXT:    ret
 ; RV32IZbbNOZbt-NEXT:  .LBB1_4:
 ; RV32IZbbNOZbt-NEXT:    srai a0, a3, 31
 ; RV32IZbbNOZbt-NEXT:    ret
 ;
 ; RV64IZbbNOZbt-LABEL: func64:
 ; RV64IZbbNOZbt:       # %bb.0:
-; RV64IZbbNOZbt-NEXT:    mv a1, a0
 ; RV64IZbbNOZbt-NEXT:    sub a3, a0, a2
-; RV64IZbbNOZbt-NEXT:    addi a0, zero, -1
-; RV64IZbbNOZbt-NEXT:    slli a0, a0, 63
-; RV64IZbbNOZbt-NEXT:    bgez a3, .LBB1_2
+; RV64IZbbNOZbt-NEXT:    addi a1, zero, -1
+; RV64IZbbNOZbt-NEXT:    bltz a3, .LBB1_2
 ; RV64IZbbNOZbt-NEXT:  # %bb.1:
-; RV64IZbbNOZbt-NEXT:    addi a0, a0, -1
+; RV64IZbbNOZbt-NEXT:    slli a1, a1, 63
+; RV64IZbbNOZbt-NEXT:    j .LBB1_3
 ; RV64IZbbNOZbt-NEXT:  .LBB1_2:
+; RV64IZbbNOZbt-NEXT:    srli a1, a1, 1
+; RV64IZbbNOZbt-NEXT:  .LBB1_3:
 ; RV64IZbbNOZbt-NEXT:    sgtz a2, a2
-; RV64IZbbNOZbt-NEXT:    slt a1, a3, a1
-; RV64IZbbNOZbt-NEXT:    bne a2, a1, .LBB1_4
-; RV64IZbbNOZbt-NEXT:  # %bb.3:
-; RV64IZbbNOZbt-NEXT:    mv a0, a3
-; RV64IZbbNOZbt-NEXT:  .LBB1_4:
+; RV64IZbbNOZbt-NEXT:    slt a0, a3, a0
+; RV64IZbbNOZbt-NEXT:    bne a2, a0, .LBB1_5
+; RV64IZbbNOZbt-NEXT:  # %bb.4:
+; RV64IZbbNOZbt-NEXT:    mv a1, a3
+; RV64IZbbNOZbt-NEXT:  .LBB1_5:
+; RV64IZbbNOZbt-NEXT:    mv a0, a1
 ; RV64IZbbNOZbt-NEXT:    ret
 ;
 ; RV32IZbbZbt-LABEL: func64:
 ; RV32IZbbZbt:       # %bb.0:
 ; RV32IZbbZbt-NEXT:    sltu a2, a0, a4
 ; RV32IZbbZbt-NEXT:    sub a3, a1, a5
 ; RV32IZbbZbt-NEXT:    sub a2, a3, a2
 ; RV32IZbbZbt-NEXT:    slti a7, a2, 0

 ; RV64IZbbZbt-LABEL: func64:
 ; RV64IZbbZbt:       # %bb.0:
 ; RV64IZbbZbt-NEXT:    sgtz a1, a2
 ; RV64IZbbZbt-NEXT:    sub a2, a0, a2
 ; RV64IZbbZbt-NEXT:    slt a0, a2, a0
 ; RV64IZbbZbt-NEXT:    xor a0, a1, a0
 ; RV64IZbbZbt-NEXT:    slti a1, a2, 0
 ; RV64IZbbZbt-NEXT:    addi a3, zero, -1
-; RV64IZbbZbt-NEXT:    slli a3, a3, 63
-; RV64IZbbZbt-NEXT:    addi a4, a3, -1
-; RV64IZbbZbt-NEXT:    cmov a1, a1, a4, a3
+; RV64IZbbZbt-NEXT:    slli a4, a3, 63
+; RV64IZbbZbt-NEXT:    srli a3, a3, 1
+; RV64IZbbZbt-NEXT:    cmov a1, a1, a3, a4
 ; RV64IZbbZbt-NEXT:    cmov a0, a0, a1, a2
 ; RV64IZbbZbt-NEXT:    ret
   %a = mul i64 %y, %z
   %tmp = call i64 @llvm.ssub.sat.i64(i64 %x, i64 %z)
   ret i64 %tmp
 }
 
 define i16 @func16(i16 %x, i16 %y, i16 %z) nounwind {

llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll

 ; RV64-LABEL: test_urem_vec:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    addi sp, sp, -48
 ; RV64-NEXT:    sd ra, 40(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 32(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s1, 24(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s2, 16(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s3, 8(sp) # 8-byte Folded Spill
-; RV64-NEXT:    sd s4, 0(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    mv s0, a0
 ; RV64-NEXT:    lbu a0, 4(a0)
 ; RV64-NEXT:    lwu a1, 0(s0)
 ; RV64-NEXT:    slli a0, a0, 32
 ; RV64-NEXT:    or a0, a1, a0
 ; RV64-NEXT:    srli s2, a0, 11
 ; RV64-NEXT:    srli s1, a0, 22
 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    addi a1, zero, 683
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    slli a1, a0, 10
 ; RV64-NEXT:    andi a0, a0, 2046
 ; RV64-NEXT:    srli a0, a0, 1
 ; RV64-NEXT:    or a0, a0, a1
 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    addi a1, zero, 341
 ; RV64-NEXT:    sltu s3, a1, a0
 ; RV64-NEXT:    addi a1, zero, 819
 ; RV64-NEXT:    mv a0, s1
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    addi a0, a0, -1638
 ; RV64-NEXT:    andi a0, a0, 2047
-; RV64-NEXT:    addi s4, zero, 1
-; RV64-NEXT:    sltu s1, s4, a0
+; RV64-NEXT:    addi a1, zero, 1
+; RV64-NEXT:    sltu s1, a1, a0
 ; RV64-NEXT:    addi a1, zero, 1463
 ; RV64-NEXT:    mv a0, s2
 ; RV64-NEXT:    call __muldi3@plt
 ; RV64-NEXT:    addi a0, a0, -1463
 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    addi a1, zero, 292
 ; RV64-NEXT:    sltu a0, a1, a0
 ; RV64-NEXT:    neg a1, s3
 ; RV64-NEXT:    neg a0, a0
 ; RV64-NEXT:    andi a1, a1, 2047
 ; RV64-NEXT:    andi a0, a0, 2047
 ; RV64-NEXT:    slli a0, a0, 11
 ; RV64-NEXT:    or a0, a1, a0
 ; RV64-NEXT:    slli a1, s1, 22
 ; RV64-NEXT:    sub a0, a0, a1
 ; RV64-NEXT:    sw a0, 0(s0)
-; RV64-NEXT:    slli a1, s4, 33
-; RV64-NEXT:    addi a1, a1, -1
+; RV64-NEXT:    addi a1, zero, -1
+; RV64-NEXT:    srli a1, a1, 31
 ; RV64-NEXT:    and a0, a0, a1
 ; RV64-NEXT:    srli a0, a0, 32
 ; RV64-NEXT:    sb a0, 4(s0)
-; RV64-NEXT:    ld s4, 0(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s3, 8(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s2, 16(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s1, 24(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld s0, 32(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    ld ra, 40(sp) # 8-byte Folded Reload
 ; RV64-NEXT:    addi sp, sp, 48
 ; RV64-NEXT:    ret
 ;

 ; RV64M-NEXT:    addi a4, zero, 341
 ; RV64M-NEXT:    sltu a1, a4, a1
 ; RV64M-NEXT:    addi a4, zero, 819
 ; RV64M-NEXT:    mul a3, a3, a4
 ; RV64M-NEXT:    addi a3, a3, -1638
 ; RV64M-NEXT:    andi a3, a3, 2047
 ; RV64M-NEXT:    addi a4, zero, 1
 ; RV64M-NEXT:    sltu a3, a4, a3
-; RV64M-NEXT:    addi a5, zero, 1463
-; RV64M-NEXT:    mul a2, a2, a5
+; RV64M-NEXT:    addi a4, zero, 1463
+; RV64M-NEXT:    mul a2, a2, a4
 ; RV64M-NEXT:    addi a2, a2, -1463
 ; RV64M-NEXT:    andi a2, a2, 2047
-; RV64M-NEXT:    addi a5, zero, 292
-; RV64M-NEXT:    sltu a2, a5, a2
+; RV64M-NEXT:    addi a4, zero, 292
+; RV64M-NEXT:    sltu a2, a4, a2
 ; RV64M-NEXT:    neg a1, a1
 ; RV64M-NEXT:    neg a2, a2
 ; RV64M-NEXT:    andi a1, a1, 2047
 ; RV64M-NEXT:    andi a2, a2, 2047
 ; RV64M-NEXT:    slli a2, a2, 11
 ; RV64M-NEXT:    or a1, a1, a2
 ; RV64M-NEXT:    slli a2, a3, 22
 ; RV64M-NEXT:    sub a1, a1, a2
 ; RV64M-NEXT:    sw a1, 0(a0)
-; RV64M-NEXT:    slli a2, a4, 33
-; RV64M-NEXT:    addi a2, a2, -1
+; RV64M-NEXT:    addi a2, zero, -1
+; RV64M-NEXT:    srli a2, a2, 31
 ; RV64M-NEXT:    and a1, a1, a2
 ; RV64M-NEXT:    srli a1, a1, 32
 ; RV64M-NEXT:    sb a1, 4(a0)
 ; RV64M-NEXT:    ret
 ;
 ; RV32MV-LABEL: test_urem_vec:
 ; RV32MV:       # %bb.0:
 ; RV32MV-NEXT:    addi sp, sp, -16

 ; RV64MV-NEXT:    vmv.s.x v27, a1
 ; RV64MV-NEXT:    vsll.vv v26, v26, v27
 ; RV64MV-NEXT:    addi a1, zero, 2047
 ; RV64MV-NEXT:    vand.vx v25, v25, a1
 ; RV64MV-NEXT:    vmv.v.i v27, 0
 ; RV64MV-NEXT:    addi a2, zero, 1
 ; RV64MV-NEXT:    vmv1r.v v28, v27
 ; RV64MV-NEXT:    vmv.s.x v28, a2
-; RV64MV-NEXT:    lui a3, %hi(.LCPI4_1)
-; RV64MV-NEXT:    addi a3, a3, %lo(.LCPI4_1)
-; RV64MV-NEXT:    vle16.v v29, (a3)
+; RV64MV-NEXT:    lui a2, %hi(.LCPI4_1)
+; RV64MV-NEXT:    addi a2, a2, %lo(.LCPI4_1)
+; RV64MV-NEXT:    vle16.v v29, (a2)
 ; RV64MV-NEXT:    vsrl.vv v25, v25, v28
 ; RV64MV-NEXT:    vor.vv v25, v25, v26
 ; RV64MV-NEXT:    vand.vx v25, v25, a1
 ; RV64MV-NEXT:    vmsltu.vv v0, v29, v25
 ; RV64MV-NEXT:    vmerge.vim v25, v27, -1, v0
 ; RV64MV-NEXT:    vmv.x.s a1, v25
 ; RV64MV-NEXT:    andi a1, a1, 2047
-; RV64MV-NEXT:    vsetivli a3, 1, e16,m1,ta,mu
+; RV64MV-NEXT:    vsetivli a2, 1, e16,m1,ta,mu
 ; RV64MV-NEXT:    vslidedown.vi v26, v25, 1
-; RV64MV-NEXT:    vmv.x.s a3, v26
-; RV64MV-NEXT:    andi a3, a3, 2047
-; RV64MV-NEXT:    slli a3, a3, 11
-; RV64MV-NEXT:    or a1, a1, a3
+; RV64MV-NEXT:    vmv.x.s a2, v26
+; RV64MV-NEXT:    andi a2, a2, 2047
+; RV64MV-NEXT:    slli a2, a2, 11
+; RV64MV-NEXT:    or a1, a1, a2
 ; RV64MV-NEXT:    vslidedown.vi v25, v25, 2
-; RV64MV-NEXT:    vmv.x.s a3, v25
-; RV64MV-NEXT:    slli a3, a3, 22
-; RV64MV-NEXT:    or a1, a1, a3
+; RV64MV-NEXT:    vmv.x.s a2, v25
+; RV64MV-NEXT:    slli a2, a2, 22
+; RV64MV-NEXT:    or a1, a1, a2
 ; RV64MV-NEXT:    sw a1, 0(a0)
-; RV64MV-NEXT:    slli a2, a2, 33
-; RV64MV-NEXT:    addi a2, a2, -1
+; RV64MV-NEXT:    addi a2, zero, -1
+; RV64MV-NEXT:    srli a2, a2, 31
 ; RV64MV-NEXT:    and a1, a1, a2
 ; RV64MV-NEXT:    srli a1, a1, 32
 ; RV64MV-NEXT:    sb a1, 4(a0)
 ; RV64MV-NEXT:    addi sp, sp, 16
 ; RV64MV-NEXT:    ret
   %ld = load <3 x i11>, <3 x i11>* %X
   %urem = urem <3 x i11> %ld, <i11 6, i11 7, i11 -5>
   %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
   %ext = sext <3 x i1> %cmp to <3 x i11>
   store <3 x i11> %ext, <3 x i11>* %X
   ret void
 }

llvm/test/MC/RISCV/rv64c-aliases-valid.s

 # CHECK-EXPAND: lui a2, 524288
 li x12, -2147483648
 # CHECK-EXPAND: lui a2, 524288
 li x12, -0x80000000
 
 # CHECK-EXPAND: c.li a2, 1
 # CHECK-EXPAND: c.slli a2, 31
 li x12, 0x80000000
-# CHECK-EXPAND: c.li a2, 1
-# CHECK-EXPAND: c.slli a2, 32
-# CHECK-EXPAND: c.addi a2, -1
+# CHECK-EXPAND: c.li a2, -1
+# CHECK-EXPAND: c.srli a2, 32
 li x12, 0xFFFFFFFF
 
 # CHECK-EXPAND: c.li t0, 1
 # CHECK-EXPAND: c.slli t0, 32
 li t0, 0x100000000
 # CHECK-EXPAND: c.li t1, -1
 # CHECK-EXPAND: c.slli t1, 63
 li t1, 0x8000000000000000

llvm/test/MC/RISCV/rv64i-aliases-valid.s

 # CHECK-EXPAND: lui a2, 524288
 li x12, -2147483648
 # CHECK-EXPAND: lui a2, 524288
 li x12, -0x80000000
 
 # CHECK-EXPAND: addi a2, zero, 1
 # CHECK-EXPAND: slli a2, a2, 31
 li x12, 0x80000000
-# CHECK-EXPAND: addi a2, zero, 1
-# CHECK-EXPAND: slli a2, a2, 32
-# CHECK-EXPAND: addi a2, a2, -1
+# CHECK-EXPAND: addi a2, zero, -1
+# CHECK-EXPAND: srli a2, a2, 32
 li x12, 0xFFFFFFFF
 
 # CHECK-EXPAND: addi t0, zero, 1
 # CHECK-EXPAND: slli t0, t0, 32
 li t0, 0x100000000
 # CHECK-EXPAND: addi t1, zero, -1
 # CHECK-EXPAND: slli t1, t1, 63
 li t1, 0x8000000000000000

 # CHECK-EXPAND: lui t0, 64
 # CHECK-EXPAND: addiw t0, t0, 1
 # CHECK-EXPAND: slli t0, t0, 14
 li x5, 0x100004000
 # CHECK-EXPAND: lui t1, 1
 # CHECK-EXPAND: addiw t1, t1, 1
 # CHECK-EXPAND: slli t1, t1, 32
 li x6, 0x100100000000
-# CHECK-EXPAND: addi t2, zero, 1
-# CHECK-EXPAND: slli t2, t2, 36
-# CHECK-EXPAND: addi t2, t2, -1
-# CHECK-EXPAND: slli t2, t2, 12
-# CHECK-EXPAND: addi t2, t2, 1
+# CHECK-EXPAND: lui t2, 983072
+# CHECK-EXPAND: srli t2, t2, 16
 li x7, 0xFFFFFFFFF001
 # CHECK-EXPAND: lui s0, 65536
 # CHECK-EXPAND: addiw s0, s0, -1
 # CHECK-EXPAND: slli s0, s0, 12
 # CHECK-EXPAND: addi s0, s0, 1
 li x8, 0xFFFFFFF001
 # CHECK-EXPAND: lui s1, 1
 # CHECK-EXPAND: addiw s1, s1, 1