[NFC][RISCV] Add test showing wrong stack slot for GPR and RVV spilled registers

[rogfer01]

Summary

This testcase shows that we attempt to assign the same offset sp + 16 to two different stack objects.

The fix will come in a later change.

[rogfer01]

ChangeLog:

• Simplify the MIR input
• Split test in two for RV32 and RV64

[frasercrmck]

I'm wondering if the commit message should indicate it's adding a test for the issue (though I realise space is at a premium). I was a bit confused at first.

llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot-rv32.mir

21 ↗

(On Diff #331545)

nit: opening brace on a new line is a bit unusual?

[rogfer01]

ChangeLog:

• Clarify the purpose of the change.
• Adjust syntax of the IR input.

[frasercrmck]

LGTM though (sorry) maybe the tests could have a short comment explaining what they're testing (since they'll be fixed by a future patch anyway) and what to be wary of when the output changes.

[rogfer01]

ChangeLog:

• Describe a bit better the purpose of the test.

[rogfer01]

In D98801#2644290, @frasercrmck wrote:

LGTM though (sorry) maybe the tests could have a short comment explaining what they're testing (since they'll be fixed by a future patch anyway) and what to be wary of when the output changes.

Sure, no problem. Thanks!

llvm/test/CodeGen/RISCV/rvv/wrong-stack-slot.mir

+# RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-v  -o - %s \
+# RUN:   -start-before=prologepilog | FileCheck %s
+--- |
+  define void @foo()
+  {
+  entry:
+    ret void
+  }
+...
+---
+name:            foo
+alignment:       2
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:
+  - { reg: '$x10', virtual-reg: '' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    8
+  adjustsStack:    false
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: spill-slot, offset: 0, size: 8, alignment: 8,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+  - { id: 1, name: '', type: spill-slot, offset: 0, size: 16, alignment: 8,
+      stack-id: scalable-vector, callee-saved-register: '', callee-saved-restored: true,
+      debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    ; CHECK-LABEL: foo:
+    ; CHECK:    sd a0, 16(sp)
+    ; CHECK-NEXT:    addi a0, sp, 16
+    ; CHECK-NEXT:    vs2r.v v30, (a0)
+    liveins: $x10, $v30m2
+
+    $x25 = COPY $x10
+    SD renamable $x25, %stack.0, 0 :: (store 8 into %stack.0)
+    PseudoVSPILL_M2 renamable $v30m2, %stack.1 :: (store unknown-size into %stack.1, align 8)
+    PseudoRET
+
+...
+