This is an archive of the discontinued LLVM Phabricator instance.

[ARM] Tone down the MVE scalarization overhead
ClosedPublic

Authored by dmgreen on Mar 9 2021, 3:09 AM.

Details

Summary

The scalarization overhead was set deliberately high for MVE, whilst the codegen was new. It helps protect us against the negative ramifications of mixing scalar and vector instructions. This decreases that, especially for floating point where the cost of extracting/inserting lane elements can be low. For integer the cost is still fairly high due to the cross-register-bank copy, but is not longer n^2 in the length of the vector.

In general, this will decrease the cost of scalarizing floats and long integer vectors. i64 increase in cost, having a high cost before and after this patch. For floats this allows up to start doing things like vectorizing fdiv instructions, even if they are scalarized.

It requires some fixups from D98243 and D98210 to adjust other inefficiencies that this exposes.

Diff Detail

Event Timeline

dmgreen created this revision.Mar 9 2021, 3:09 AM
dmgreen requested review of this revision.Mar 9 2021, 3:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 9 2021, 3:09 AM
SjoerdMeijer accepted this revision.Mar 16 2021, 6:28 AM

And the i64 costs go up because they are not legal ops? LGTM.

llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
820–825

Typo: that

This revision is now accepted and ready to land.Mar 16 2021, 6:28 AM
This revision was landed with ongoing or failed builds.Mar 19 2021, 11:30 AM
This revision was automatically updated to reflect the committed changes.