[MLIR][SPIRV] Rename `spv.loop` to `spv.mlir.loop`.

[ergawy]

Summary

To unify the naming scheme across all ops in the SPIR-V dialect, we are
moving from spv.camelCase to spv.CamelCase everywhere.

[antiagainst]

Coudl you change it to spv.mlir.loop actually? In general we use the spv.CamelCase for anything that has correspondence to an instruction in the SPIR-V spec. For other ops introduced for MLIR's requirement/purpose (like spv.mlir.merge, etc.), it should be spv.mlir.snake_case.

[ergawy]

Rename to spv.mlir.loop.

[ergawy]

Fix comments.

[ergawy]

Fix doc string.

mlir/docs/Dialects/SPIR-V.md

 flow subsequently converges. These blocks delimit constructs that must nest, and
 can only be entered and exited in structured ways.
 
 In the SPIR-V dialect, we use regions to mark the boundary of a structured
 control flow construct. With this approach, it's easier to discover all blocks
 belonging to a structured control flow construct. It is also more idiomatic to
 MLIR system.
 
-We introduce a `spv.selection` and `spv.loop` op for structured selections and
+We introduce a `spv.selection` and `spv.mlir.loop` op for structured selections and
 loops, respectively. The merge targets are the next ops following them. Inside
 their regions, a special terminator, `spv.mlir.merge` is introduced for branching to
 the merge target.
 
 ### Selection
 
 `spv.selection` defines a selection construct. It contains one region. The
 region should contain at least two blocks: one selection header block and one
func @selection(%cond: i1) -> () {
 
   // ...
 }
 
 ```
 
 ### Loop
 
-`spv.loop` defines a loop construct. It contains one region. The region should
+`spv.mlir.loop` defines a loop construct. It contains one region. The region should
 contain at least four blocks: one entry block, one loop header block, one loop
 continue block, one merge block.
 
 *   The entry block should be the first block and it should jump to the loop
     header block, which is the second block.
 *   The merge block should be the last block. The merge block should only
     contain a `spv.mlir.merge` op. Any block except the entry block can branch to
     the merge block for early exit.

 It will be represented as
 
 ```mlir
 func @loop(%count : i32) -> () {
   %zero = spv.constant 0: i32
   %one = spv.constant 1: i32
   %var = spv.Variable init(%zero) : !spv.ptr<i32, Function>
 
-  spv.loop {
+  spv.mlir.loop {
     spv.Branch ^header
 
   ^header:
     %val0 = spv.Load "Function" %var : i32
     %cmp = spv.SLessThan %val0, %count : i32
     spv.BranchConditional %cmp, ^body, ^merge
 
   ^body:
*   Attributes on `spv.module` are emitted as their corresponding SPIR-V
     instructions.
 *   Types are serialized into `OpType*` instructions in the SPIR-V binary module
     section for types, constants, and global variables.
 *   `spv.constant`s are unified and placed in the SPIR-V binary module section
     for types, constants, and global variables.
 *   Attributes on ops, if not part of the op's binary encoding, are emitted as
     `OpDecorate*` instructions in the SPIR-V binary module section for
     decorations.
-*   `spv.selection`s and `spv.loop`s are emitted as basic blocks with `Op*Merge`
+*   `spv.selection`s and `spv.mlir.loop`s are emitted as basic blocks with `Op*Merge`
     instructions in the header block as required by the binary format.
 *   Block arguments are materialized as `OpPhi` instructions at the beginning of
     the corresponding blocks.
 
 Similarly, a few transformations are performed during deserialization:
 
 *   Instructions for execution environment requirements (extensions,
     capabilities, extended instruction sets, etc.) will be placed as attributes
     on `spv.module`.
 *   `OpType*` instructions will be converted into proper `mlir::Type`s.
 *   `OpConstant*` instructions are materialized as `spv.constant` at each use
     site.
 *   `OpVariable` instructions will be converted to `spv.globalVariable` ops if
     in module-level; otherwise they will be converted into `spv.Variable` ops.
 *   Every use of a module-level `OpVariable` instruction will materialize a
     `spv.mlir.addressof` op to turn the symbol of the corresponding
     `spv.globalVariable` into an SSA value.
 *   Every use of a `OpSpecConstant` instruction will materialize a
     `spv.mlir.referenceof` op to turn the symbol of the corresponding
     `spv.specConstant` into an SSA value.
 *   `OpPhi` instructions are converted to block arguments.
-*   Structured control flow are placed inside `spv.selection` and `spv.loop`.
+*   Structured control flow are placed inside `spv.selection` and `spv.mlir.loop`.
 
 ## Conversions
 
 One of the main features of MLIR is the ability to progressively lower from
 dialects that capture programmer abstraction into dialects that are closer to a
 machine representation, like SPIR-V dialect. This progressive lowering through
 multiple dialects is enabled through the use of the
 [DialectConversion][MlirDialectConversion] framework in MLIR. To simplify

mlir/docs/SPIRVToLLVMDialectConversion.md

 
 `spv.FunctionCall` maps to `llvm.call`. For example:
 
 ```mlir
 %0 = spv.FunctionCall @foo() : () -> i32    =>    %0 = llvm.call @foo() : () -> f32
 spv.FunctionCall @bar(%0) : (i32) -> ()     =>    llvm.call @bar(%0) : (f32) -> ()
 ```
 
-### `spv.selection` and `spv.loop`
+### `spv.selection` and `spv.mlir.loop`
 
-Control flow within `spv.selection` and `spv.loop` is lowered directly to LLVM
+Control flow within `spv.selection` and `spv.mlir.loop` is lowered directly to LLVM
 via branch ops. The conversion can only be applied to selection or loop with all
 blocks being reachable. Moreover, selection and loop control attributes (such as
 `Flatten` or `Unroll`) are not supported at the moment.
 
 ```mlir
 // Conversion of selection
 %cond = spv.constant true                               %cond = llvm.mlir.constant(true) : i1
 spv.selection {

 }
 // Remaining code                                                                           ^continue:
                                                         // Remaining code
 ```
 
 ```mlir
 // Conversion of loop
 %cond = spv.constant true                               %cond = llvm.mlir.constant(true) : i1
-spv.loop {
+spv.mlir.loop {
   spv.Branch ^header                                    llvm.br ^header
 
 ^header:                                              ^header:
   // Header code                                        // Header code
   spv.BranchConditional %cond, ^body, ^merge    =>      llvm.cond_br %cond, ^body, ^merge
 
 ^body:                                                ^body:
   // Body code                                          // Body code

mlir/include/mlir/Dialect/SPIRV/IR/SPIRVControlFlowOps.td

def SPV_FunctionCallOp : SPV_Op<"FunctionCall", [
   let assemblyFormat = [{
     $callee `(` $arguments `)` attr-dict `:`
     functional-type($arguments, results)
   }];
 }
 
 // -----
 
-def SPV_LoopOp : SPV_Op<"loop", [InFunctionScope]> {
+def SPV_LoopOp : SPV_Op<"mlir.loop", [InFunctionScope]> {
   let summary = "Define a structured loop.";
 
   let description = [{
     SPIR-V can explicitly declare structured control-flow constructs using merge
     instructions. These explicitly declare a header block before the control
     flow diverges and a merge block where control flow subsequently converges.
     These blocks delimit constructs that must nest, and can only be entered
     and exited in structured ways. See "2.11. Structured Control Flow" of the
     SPIR-V spec for more details.
 
-    Instead of having a `spv.LoopMerge` op to directly model loop merge
+    Instead of having a `spv.mlir.loopMerge` op to directly model loop merge
     instruction for indicating the merge and continue target, we use regions
     to delimit the boundary of the loop: the merge target is the next op
-    following the `spv.loop` op and the continue target is the block that
-    has a back-edge pointing to the entry block inside the `spv.loop`'s region.
+    following the `spv.mlir.loop` op and the continue target is the block that
+    has a back-edge pointing to the entry block inside the `spv.mlir.loop`'s region.
     This way it's easier to discover all blocks belonging to a construct and
     it plays nicer with the MLIR system.
 
-    The `spv.loop` region should contain at least four blocks: one entry block,
+    The `spv.mlir.loop` region should contain at least four blocks: one entry block,
     one loop header block, one loop continue block, one loop merge block.
     The entry block should be the first block and it should jump to the loop
     header block, which is the second block. The loop merge block should be the
     last block. The merge block should only contain a `spv.mlir.merge` op.
     The continue block should be the second to last block and it should have a
     branch to the loop header block. The loop continue block should be the only
     block, except the entry block, branching to the header block.
   }];

 }
 
 // -----
 
 def SPV_MergeOp : SPV_Op<"mlir.merge", [NoSideEffect, Terminator]> {
   let summary = "A special terminator for merging a structured selection/loop.";
 
   let description = [{
-    We use `spv.selection`/`spv.loop` for modelling structured selection/loop.
+    We use `spv.selection`/`spv.mlir.loop` for modelling structured selection/loop.
     This op is a terminator used inside their regions to mean jumping to the
     merge point, which is the next op following the `spv.selection` or
-    `spv.loop` op. This op does not have a corresponding instruction in the
+    `spv.mlir.loop` op. This op does not have a corresponding instruction in the
     SPIR-V binary format; it's solely for structural purpose.
   }];
 
   let arguments = (ins);
 
   let results = (outs);
 
   let assemblyFormat = "attr-dict";

mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp

 using namespace mlir;
 
 //===----------------------------------------------------------------------===//
 // Context
 //===----------------------------------------------------------------------===//
 
 namespace mlir {
 struct ScfToSPIRVContextImpl {
-  // Map between the spirv region control flow operation (spv.loop or
+  // Map between the spirv region control flow operation (spv.mlir.loop or
   // spv.selection) to the VariableOp created to store the region results. The
   // order of the VariableOp matches the order of the results.
   DenseMap<Operation *, SmallVector<spirv::VariableOp, 8>> outputVars;
 };
 } // namespace mlir
 
 /// We use ScfToSPIRVContext to store information about the lowering of the scf
 /// region that need to be used later on. When we lower scf.for/scf.if we create
public:
   LogicalResult
   matchAndRewrite(scf::YieldOp terminatorOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override;
 };
 } // namespace
 
 /// Helper function to replaces SCF op outputs with SPIR-V variable loads.
 /// We create VariableOp to handle the results value of the control flow region.
-/// spv.loop/spv.selection currently don't yield value. Right after the loop
-/// we load the value from the allocation and use it as the SCF op result.
+/// spv.mlir.loop/spv.selection currently don't yield value. Right after the
+/// loop we load the value from the allocation and use it as the SCF op result.
 template <typename ScfOp, typename OpTy>
 static void replaceSCFOutputValue(ScfOp scfOp, OpTy newOp,
                                   ConversionPatternRewriter &rewriter,
                                   ScfToSPIRVContextImpl *scfToSPIRVContext,
                                   ArrayRef<Type> returnTypes) {
 
   Location loc = scfOp.getLoc();
   auto &allocas = scfToSPIRVContext->outputVars[newOp];

mlir/lib/Conversion/SPIRVToLLVM/SPIRVToLLVM.cpp

public:
   matchAndRewrite(spirv::ReturnValueOp returnValueOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     rewriter.replaceOpWithNewOp<LLVM::ReturnOp>(returnValueOp, ArrayRef<Type>(),
                                                 operands);
     return success();
   }
 };
 
-/// Converts `spv.loop` to LLVM dialect. All blocks within selection should be
-/// reachable for conversion to succeed.
-/// The structure of the loop in LLVM dialect will be the following:
+/// Converts `spv.mlir.loop` to LLVM dialect. All blocks within selection should
+/// be reachable for conversion to succeed. The structure of the loop in LLVM
+/// dialect will be the following:
 ///
 ///      +------------------------------------+
-///      | <code before spv.loop>             |
+///      | <code before spv.mlir.loop>             |
 ///      | llvm.br ^header                    |
 ///      +------------------------------------+
 ///                           |
 ///   +----------------+      |
 ///   |                |      |
 ///   |                V      V
 ///   |  +------------------------------------+
 ///   |  | ^header:                           |

 ///      +------------------------------------+
 ///      | ^exit:                             |
 ///      |   llvm.br ^remaining               |
 ///      +------------------------------------+
 ///                        |
 ///                        V
 ///      +------------------------------------+
 ///      | ^remaining:                        |
-///      |   <code after spv.loop>            |
+///      |   <code after spv.mlir.loop>            |
 ///      +------------------------------------+
 ///
 class LoopPattern : public SPIRVToLLVMConversion<spirv::LoopOp> {
 public:
   using SPIRVToLLVMConversion<spirv::LoopOp>::SPIRVToLLVMConversion;
 
   LogicalResult
   matchAndRewrite(spirv::LoopOp loopOp, ArrayRef<Value> operands,
                   ConversionPatternRewriter &rewriter) const override {
     // There is no support of loop control at the moment.
     if (loopOp.loop_control() != spirv::LoopControl::None)
       return failure();
 
     Location loc = loopOp.getLoc();
 
-    // Split the current block after `spv.loop`. The remaining ops will be used
-    // in `endBlock`.
+    // Split the current block after `spv.mlir.loop`. The remaining ops will be
+    // used in `endBlock`.
     Block *currentBlock = rewriter.getBlock();
     auto position = Block::iterator(loopOp);
     Block *endBlock = rewriter.splitBlock(currentBlock, position);
 
     // Remove entry block and create a branch in the current block going to the
     // header block.
     Block *entryBlock = loopOp.getEntryBlock();
     assert(entryBlock->getOperations().size() == 1);

mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp

bool isLegalToInline(Operation *call, Operation *callable,
     return true;
   }
 
   /// Returns true if the given region 'src' can be inlined into the region
   /// 'dest' that is attached to an operation registered to the current dialect.
   bool isLegalToInline(Region *dest, Region *src, bool wouldBeCloned,
                        BlockAndValueMapping &) const final {
     // Return true here when inlining into spv.func, spv.selection, and
-    // spv.loop operations.
+    // spv.mlir.loop operations.
     auto *op = dest->getParentOp();
     return isa<spirv::FuncOp, spirv::SelectionOp, spirv::LoopOp>(op);
   }
 
   /// Returns true if the given operation 'op', that is registered to this
   /// dialect, can be inlined into the region 'dest' that is attached to an
   /// operation registered to the current dialect.
   bool isLegalToInline(Operation *op, Region *dest, bool wouldBeCloned,

mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp

static LogicalResult verify(spirv::LoadOp loadOp) {
   if (failed(verifyLoadStorePtrAndValTypes(loadOp, loadOp.ptr(),
                                            loadOp.value()))) {
     return failure();
   }
   return verifyMemoryAccessAttribute(loadOp);
 }
 
 //===----------------------------------------------------------------------===//
-// spv.loop
+// spv.mlir.loop
 //===----------------------------------------------------------------------===//
 
 void spirv::LoopOp::build(OpBuilder &builder, OperationState &state) {
   state.addAttribute("loop_control",
                      builder.getI32IntegerAttr(
                          static_cast<uint32_t>(spirv::LoopControl::None)));
   state.addRegion();
 }

 //===----------------------------------------------------------------------===//
 // spv.mlir.merge
 //===----------------------------------------------------------------------===//
 
 static LogicalResult verify(spirv::MergeOp mergeOp) {
   auto *parentOp = mergeOp->getParentOp();
   if (!parentOp || !isa<spirv::SelectionOp, spirv::LoopOp>(parentOp))
     return mergeOp.emitOpError(
-        "expected parent op to be 'spv.selection' or 'spv.loop'");
+        "expected parent op to be 'spv.selection' or 'spv.mlir.loop'");
 
   Block &parentLastBlock = mergeOp->getParentRegion()->back();
   if (mergeOp.getOperation() != parentLastBlock.getTerminator())
-    return mergeOp.emitOpError(
-        "can only be used in the last block of 'spv.selection' or 'spv.loop'");
+    return mergeOp.emitOpError("can only be used in the last block of "
+                               "'spv.selection' or 'spv.mlir.loop'");
   return success();
 }
 
 //===----------------------------------------------------------------------===//
 // spv.module
 //===----------------------------------------------------------------------===//
 
 void spirv::ModuleOp::build(OpBuilder &builder, OperationState &state,

mlir/lib/Target/SPIRV/Deserialization/Deserializer.h

 
 //===----------------------------------------------------------------------===//
 // Utility Definitions
 //===----------------------------------------------------------------------===//
 
 /// A struct for containing a header block's merge and continue targets.
 ///
 /// This struct is used to track original structured control flow info from
-/// SPIR-V blob. This info will be used to create spv.selection/spv.loop
+/// SPIR-V blob. This info will be used to create spv.selection/spv.mlir.loop
 /// later.
 struct BlockMergeInfo {
   Block *mergeBlock;
   Block *continueBlock; // nullptr for spv.selection
   Location loc;
   uint32_t control;
 
   BlockMergeInfo(Location location, uint32_t control)
private:
   // Control flow
   //===--------------------------------------------------------------------===//
 
   /// Returns the block for the given label <id>.
   Block *getBlock(uint32_t id) const { return blockMap.lookup(id); }
 
   // In SPIR-V, structured control flow is explicitly declared using merge
   // instructions (OpSelectionMerge and OpLoopMerge). In the SPIR-V dialect,
-  // we use spv.selection and spv.loop to group structured control flow.
+  // we use spv.selection and spv.mlir.loop to group structured control flow.
   // The deserializer need to turn structured control flow marked with merge
-  // instructions into using spv.selection/spv.loop ops.
+  // instructions into using spv.selection/spv.mlir.loop ops.
   //
   // Because structured control flow can nest and the basic block order have
   // flexibility, we cannot isolate a structured selection/loop without
   // deserializing all the blocks. So we use the following approach:
   //
   // 1. Deserialize all basic blocks in a function and create MLIR blocks for
   //    them into the function's region. In the meanwhile, keep a map between
   //    selection/loop header blocks to their corresponding merge (and continue)
   //    target blocks.
   // 2. For each selection/loop header block, recursively get all basic blocks
   //    reachable (except the merge block) and put them in a newly created
-  //    spv.selection/spv.loop's region. Structured control flow guarantees
+  //    spv.selection/spv.mlir.loop's region. Structured control flow guarantees
   //    that we enter and exit in structured ways and the construct is nestable.
-  // 3. Put the new spv.selection/spv.loop op at the beginning of the old merge
+  // 3. Put the new spv.selection/spv.mlir.loop op at the beginning of the old
+  // merge
   //    block and redirect all branches to the old header block to the old
-  //    merge block (which contains the spv.selection/spv.loop op now).
+  //    merge block (which contains the spv.selection/spv.mlir.loop op now).
 
   /// For OpPhi instructions, we use block arguments to represent them. OpPhi
   /// encodes a list of (value, predecessor) pairs. At the time of handling the
   /// block containing an OpPhi instruction, the predecessor block might not be
   /// processed yet, also the value sent by it. So we need to defer handling
   /// the block argument from the predecessors. We use the following approach:
   ///
   /// 1. For each OpPhi instruction, add a block argument to the current block
private:
   /// Processes a SPIR-V OpPhi instruction with the given `operands`.
   LogicalResult processPhi(ArrayRef<uint32_t> operands);
 
   /// Creates block arguments on predecessors previously recorded when handling
   /// OpPhi instructions.
   LogicalResult wireUpBlockArgument();
 
   /// Extracts blocks belonging to a structured selection/loop into a
-  /// spv.selection/spv.loop op. This method iterates until all blocks
+  /// spv.selection/spv.mlir.loop op. This method iterates until all blocks
   /// declared as selection/loop headers are handled.
   LogicalResult structurizeControlFlow();
 
   //===--------------------------------------------------------------------===//
   // Instruction
   //===--------------------------------------------------------------------===//
 
   /// Get the Value associated with a result <id>.

mlir/lib/Target/SPIRV/Deserialization/Deserializer.cpp

 LogicalResult
 spirv::Deserializer::processFunctionEnd(ArrayRef<uint32_t> operands) {
   // Process OpFunctionEnd.
   if (!operands.empty()) {
     return emitError(unknownLoc, "unexpected operands for OpFunctionEnd");
   }
 
   // Wire up block arguments from OpPhi instructions.
-  // Put all structured control flow in spv.selection/spv.loop ops.
+  // Put all structured control flow in spv.selection/spv.mlir.loop ops.
   if (failed(wireUpBlockArgument()) || failed(structurizeControlFlow())) {
     return failure();
   }
 
   curBlock = nullptr;
   curFunction = llvm::None;
 
   return success();

 Block *spirv::Deserializer::getOrCreateBlock(uint32_t id) {
   if (auto *block = getBlock(id)) {
     LLVM_DEBUG(llvm::dbgs() << "[block] got exiting block for id = " << id
                             << " @ " << block << "\n");
     return block;
   }
 
   // We don't know where this block will be placed finally (in a spv.selection
-  // or spv.loop or function). Create it into the function for now and sort
+  // or spv.mlir.loop or function). Create it into the function for now and sort
   // out the proper place later.
   auto *block = curFunction->addBlock();
   LLVM_DEBUG(llvm::dbgs() << "[block] created block for id = " << id << " @ "
                           << block << "\n");
   return blockMap[id] = block;
 }
 
 LogicalResult spirv::Deserializer::processBranch(ArrayRef<uint32_t> operands) {
LLVM_DEBUG(llvm::dbgs() << "[phi] predecessor @ " << predecessor
                             << " with arg id = " << value << '\n');
   }
 
   return success();
 }
 
 namespace {
 /// A class for putting all blocks in a structured selection/loop in a
-/// spv.selection/spv.loop op.
+/// spv.selection/spv.mlir.loop op.
 class ControlFlowStructurizer {
 public:
   /// Structurizes the loop at the given `headerBlock`.
   ///
-  /// This method will create an spv.loop op in the `mergeBlock` and move all
-  /// blocks in the structured loop into the spv.loop's region. All branches to
-  /// the `headerBlock` will be redirected to the `mergeBlock`.
-  /// This method will also update `mergeInfo` by remapping all blocks inside to
-  /// the newly cloned ones inside structured control flow op's regions.
+  /// This method will create an spv.mlir.loop op in the `mergeBlock` and move
+  /// all blocks in the structured loop into the spv.mlir.loop's region. All
+  /// branches to the `headerBlock` will be redirected to the `mergeBlock`. This
+  /// method will also update `mergeInfo` by remapping all blocks inside to the
+  /// newly cloned ones inside structured control flow op's regions.
   static LogicalResult structurize(Location loc, uint32_t control,
                                    spirv::BlockMergeInfoMap &mergeInfo,
                                    Block *headerBlock, Block *mergeBlock,
                                    Block *continueBlock) {
     return ControlFlowStructurizer(loc, control, mergeInfo, headerBlock,
                                    mergeBlock, continueBlock)
         .structurizeImpl();
   }
 
 private:
   ControlFlowStructurizer(Location loc, uint32_t control,
                           spirv::BlockMergeInfoMap &mergeInfo, Block *header,
                           Block *merge, Block *cont)
       : location(loc), control(control), blockMergeInfo(mergeInfo),
         headerBlock(header), mergeBlock(merge), continueBlock(cont) {}
 
   /// Creates a new spv.selection op at the beginning of the `mergeBlock`.
   spirv::SelectionOp createSelectionOp(uint32_t selectionControl);
 
-  /// Creates a new spv.loop op at the beginning of the `mergeBlock`.
+  /// Creates a new spv.mlir.loop op at the beginning of the `mergeBlock`.
   spirv::LoopOp createLoopOp(uint32_t loopControl);
 
   /// Collects all blocks reachable from `headerBlock` except `mergeBlock`.
   void collectBlocksInConstruct();
 
   LogicalResult structurizeImpl();
 
   Location location;

mlir/lib/Target/SPIRV/Serialization/Serializer.cpp

if (auto loopOp = dyn_cast<spirv::LoopOp>(op))
     return loopOp.getMergeBlock();
   return nullptr;
 }
 
 /// Given a predecessor `block` for a block with arguments, returns the block
 /// that should be used as the parent block for SPIR-V OpPhi instructions
 /// corresponding to the block arguments.
 static Block *getPhiIncomingBlock(Block *block) {
-  // If the predecessor block in question is the entry block for a spv.loop,
-  // we jump to this spv.loop from its enclosing block.
+  // If the predecessor block in question is the entry block for a
+  // spv.mlir.loop, we jump to this spv.mlir.loop from its enclosing block.
   if (block->isEntryBlock()) {
     if (auto loopOp = dyn_cast<spirv::LoopOp>(block->getParentOp())) {
       // Then the incoming parent block for OpPhi should be the merge block of
       // the structured control flow op before this loop.
       Operation *op = loopOp.getOperation();
       while ((op = op->getPrevNode()) != nullptr)
         if (Block *incomingBlock = getStructuredControlFlowOpMergeBlock(op))
           return incomingBlock;
LogicalResult Serializer::emitPhiForBlockArguments(Block *block) {
   // to this block.
   SmallVector<std::pair<Block *, Operation::operand_iterator>, 4> predecessors;
   for (Block *predecessor : block->getPredecessors()) {
     auto *terminator = predecessor->getTerminator();
     // The predecessor here is the immediate one according to MLIR's IR
     // structure. It does not directly map to the incoming parent block for the
     // OpPhi instructions at SPIR-V binary level. This is because structured
     // control flow ops are serialized to multiple SPIR-V blocks. If there is a
-    // spv.selection/spv.loop op in the MLIR predecessor block, the branch op
-    // jumping to the OpPhi's block then resides in the previous structured
+    // spv.selection/spv.mlir.loop op in the MLIR predecessor block, the branch
+    // op jumping to the OpPhi's block then resides in the previous structured
     // control flow op's merge block.
     predecessor = getPhiIncomingBlock(predecessor);
     if (auto branchOp = dyn_cast<spirv::BranchOp>(terminator)) {
       predecessors.emplace_back(predecessor, branchOp.operand_begin());
     } else {
       return terminator->emitError("unimplemented terminator for Phi creation");
     }
   }

mlir/test/Conversion/SCFToSPIRV/for.mlir

 // RUN: mlir-opt -convert-scf-to-spirv %s -o - | FileCheck %s
 
 module attributes {
   spv.target_env = #spv.target_env<
     #spv.vce<v1.0, [Shader], [SPV_KHR_storage_buffer_storage_class]>, {}>
 } {
 
 func @loop_kernel(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>) {
   // CHECK: %[[LB:.*]] = spv.constant 4 : i32
   %lb = constant 4 : index
   // CHECK: %[[UB:.*]] = spv.constant 42 : i32
   %ub = constant 42 : index
   // CHECK: %[[STEP:.*]] = spv.constant 2 : i32
   %step = constant 2 : index
-  // CHECK:      spv.loop {
+  // CHECK:      spv.mlir.loop {
   // CHECK-NEXT:   spv.Branch ^[[HEADER:.*]](%[[LB]] : i32)
   // CHECK:      ^[[HEADER]](%[[INDVAR:.*]]: i32):
   // CHECK:        %[[CMP:.*]] = spv.SLessThan %[[INDVAR]], %[[UB]] : i32
   // CHECK:        spv.BranchConditional %[[CMP]], ^[[BODY:.*]], ^[[MERGE:.*]]
   // CHECK:      ^[[BODY]]:
   // CHECK:        %[[ZERO1:.*]] = spv.constant 0 : i32
   // CHECK:        %[[OFFSET1:.*]] = spv.constant 0 : i32
   // CHECK:        %[[STRIDE1:.*]] = spv.constant 1 : i32
func @loop_yield(%arg2 : memref<10xf32>, %arg3 : memref<10xf32>) {
   // CHECK: %[[STEP:.*]] = spv.constant 2 : i32
   %step = constant 2 : index
   // CHECK: %[[INITVAR1:.*]] = spv.constant 0.000000e+00 : f32
   %s0 = constant 0.0 : f32
   // CHECK: %[[INITVAR2:.*]] = spv.constant 1.000000e+00 : f32
   %s1 = constant 1.0 : f32
   // CHECK: %[[VAR1:.*]] = spv.Variable : !spv.ptr<f32, Function>
   // CHECK: %[[VAR2:.*]] = spv.Variable : !spv.ptr<f32, Function>
-  // CHECK: spv.loop {
+  // CHECK: spv.mlir.loop {
   // CHECK:   spv.Branch ^[[HEADER:.*]](%[[LB]], %[[INITVAR1]], %[[INITVAR2]] : i32, f32, f32)
   // CHECK: ^[[HEADER]](%[[INDVAR:.*]]: i32, %[[CARRIED1:.*]]: f32, %[[CARRIED2:.*]]: f32):
   // CHECK:   %[[CMP:.*]] = spv.SLessThan %[[INDVAR]], %[[UB]] : i32
   // CHECK:   spv.BranchConditional %[[CMP]], ^[[BODY:.*]], ^[[MERGE:.*]]
   // CHECK: ^[[BODY]]:
   // CHECK:   %[[UPDATED:.*]] = spv.FAdd %[[CARRIED1]], %[[CARRIED1]] : f32
   // CHECK-DAG:   %[[INCREMENT:.*]] = spv.IAdd %[[INDVAR]], %[[STEP]] : i32
   // CHECK-DAG:   spv.Store "Function" %[[VAR1]], %[[UPDATED]] : f32

mlir/test/Conversion/SPIRVToLLVM/control-flow-ops-to-llvm.mlir

spv.module Logical GLSL450 {
   ^false:
     spv.Return
   }
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
-// spv.loop
+// spv.mlir.loop
 //===----------------------------------------------------------------------===//
 
 spv.module Logical GLSL450 {
   // CHECK-LABEL: @infinite_loop
   spv.func @infinite_loop(%count : i32) -> () "None" {
     // CHECK:   llvm.br ^[[BB1:.*]]
     // CHECK: ^[[BB1]]:
     // CHECK:   %[[COND:.*]] = llvm.mlir.constant(true) : i1
     // CHECK:   llvm.cond_br %[[COND]], ^[[BB2:.*]], ^[[BB4:.*]]
     // CHECK: ^[[BB2]]:
     // CHECK:   llvm.br ^[[BB3:.*]]
     // CHECK: ^[[BB3]]:
     // CHECK:   llvm.br ^[[BB1:.*]]
     // CHECK: ^[[BB4]]:
     // CHECK:   llvm.br ^[[BB5:.*]]
     // CHECK: ^[[BB5]]:
     // CHECK:   llvm.return
-    spv.loop {
+    spv.mlir.loop {
       spv.Branch ^header
     ^header:
       %cond = spv.constant true
       spv.BranchConditional %cond, ^body, ^merge
     ^body:
       // Do nothing
       spv.Branch ^continue
     ^continue:

mlir/test/Dialect/SPIRV/IR/control-flow-ops.mlir

spv.func @f_foo(%arg0 : i32, %arg1 : i32) -> i32 "None" {
     %0 = spv.FunctionCall @f_undefined(%arg0, %arg0) : (i32, i32) -> i32
     spv.ReturnValue %0: i32
   }
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
-// spv.loop
+// spv.mlir.loop
 //===----------------------------------------------------------------------===//
 
 // for (int i = 0; i < count; ++i) {}
 func @loop(%count : i32) -> () {
   %zero = spv.constant 0: i32
   %one = spv.constant 1: i32
   %var = spv.Variable init(%zero) : !spv.ptr<i32, Function>
 
-  // CHECK: spv.loop {
-  spv.loop {
+  // CHECK: spv.mlir.loop {
+  spv.mlir.loop {
     // CHECK-NEXT: spv.Branch ^bb1
     spv.Branch ^header
 
   // CHECK-NEXT: ^bb1:
   ^header:
     %val0 = spv.Load "Function" %var : i32
     %cmp = spv.SLessThan %val0, %count : i32
     // CHECK: spv.BranchConditional %{{.*}}, ^bb2, ^bb4
func @loop(%count : i32) -> () {
   }
   return
 }
 
 // -----
 
 // CHECK-LABEL: @empty_region
 func @empty_region() -> () {
-  // CHECK: spv.loop
-  spv.loop {
+  // CHECK: spv.mlir.loop
+  spv.mlir.loop {
   }
   return
 }
 
 // -----
 
 // CHECK-LABEL: @loop_with_control
 func @loop_with_control() -> () {
-  // CHECK: spv.loop control(Unroll)
-  spv.loop control(Unroll) {
+  // CHECK: spv.mlir.loop control(Unroll)
+  spv.mlir.loop control(Unroll) {
   }
   return
 }
 
 // -----
 
 func @wrong_merge_block() -> () {
   // expected-error @+1 {{last block must be the merge block with only one 'spv.mlir.merge' op}}
-  spv.loop {
+  spv.mlir.loop {
     spv.Return
   }
   return
 }
 
 // -----
 
 func @missing_entry_block() -> () {
   // expected-error @+1 {{must have an entry block branching to the loop header block}}
-  spv.loop {
+  spv.mlir.loop {
     spv.mlir.merge
   }
   return
 }
 
 // -----
 
 func @missing_header_block() -> () {
   // expected-error @+1 {{must have a loop header block branched from the entry block}}
-  spv.loop {
+  spv.mlir.loop {
   ^entry:
     spv.Branch ^merge
   ^merge:
     spv.mlir.merge
   }
   return
 }
 
 // -----
 
 func @entry_should_branch_to_header() -> () {
   // expected-error @+1 {{entry block must only have one 'spv.Branch' op to the second block}}
-  spv.loop {
+  spv.mlir.loop {
   ^entry:
     spv.Branch ^merge
   ^header:
     spv.Branch ^merge
   ^merge:
     spv.mlir.merge
   }
   return
 }
 
 // -----
 
 func @missing_continue_block() -> () {
   // expected-error @+1 {{requires a loop continue block branching to the loop header block}}
-  spv.loop {
+  spv.mlir.loop {
   ^entry:
     spv.Branch ^header
   ^header:
     spv.Branch ^merge
   ^merge:
     spv.mlir.merge
   }
   return
 }
 
 // -----
 
 func @continue_should_branch_to_header() -> () {
   // expected-error @+1 {{second to last block must be the loop continue block that branches to the loop header block}}
-  spv.loop {
+  spv.mlir.loop {
   ^entry:
     spv.Branch ^header
   ^header:
     spv.Branch ^continue
   ^continue:
     spv.Branch ^merge
   ^merge:
     spv.mlir.merge
   }
   return
 }
 
 // -----
 
 func @only_entry_and_continue_branch_to_header() -> () {
   // expected-error @+1 {{can only have the entry and loop continue block branching to the loop header block}}
-  spv.loop {
+  spv.mlir.loop {
   ^entry:
     spv.Branch ^header
   ^header:
     spv.Branch ^cont1
   ^cont1:
     spv.Branch ^header
   ^cont2:
     spv.Branch ^header
   ^merge:
     spv.mlir.merge
   }
   return
 }
 
 // -----
 
 //===----------------------------------------------------------------------===//
 // spv.mlir.merge
 //===----------------------------------------------------------------------===//
 
 func @merge() -> () {
-  // expected-error @+1 {{expected parent op to be 'spv.selection' or 'spv.loop'}}
+  // expected-error @+1 {{expected parent op to be 'spv.selection' or 'spv.mlir.loop'}}
   spv.mlir.merge
 }
 
 // -----
 
 func @only_allowed_in_last_block(%cond : i1) -> () {
   %zero = spv.constant 0: i32
   %one = spv.constant 1: i32
   %var = spv.Variable init(%zero) : !spv.ptr<i32, Function>
 
   spv.selection {
     spv.BranchConditional %cond, ^then, ^merge
 
   ^then:
     spv.Store "Function" %var, %one : i32
-    // expected-error @+1 {{can only be used in the last block of 'spv.selection' or 'spv.loop'}}
+    // expected-error @+1 {{can only be used in the last block of 'spv.selection' or 'spv.mlir.loop'}}
     spv.mlir.merge
 
   ^merge:
     spv.mlir.merge
   }
 
   spv.Return
 }
 
 // -----
 
 func @only_allowed_in_last_block() -> () {
   %true = spv.constant true
-  spv.loop {
+  spv.mlir.loop {
     spv.Branch ^header
   ^header:
     spv.BranchConditional %true, ^body, ^merge
   ^body:
-    // expected-error @+1 {{can only be used in the last block of 'spv.selection' or 'spv.loop'}}
+    // expected-error @+1 {{can only be used in the last block of 'spv.selection' or 'spv.mlir.loop'}}
     spv.mlir.merge
   ^continue:
     spv.Branch ^header
   ^merge:
     spv.mlir.merge
   }
   return
 }
func @in_selection(%cond : i1) -> () {
   ^merge:
     spv.mlir.merge
   }
   spv.Return
 }
 
 // CHECK-LABEL: func @in_loop
 func @in_loop(%cond : i1) -> () {
-  spv.loop {
+  spv.mlir.loop {
     spv.Branch ^header
   ^header:
     spv.BranchConditional %cond, ^body, ^merge
   ^body:
     // CHECK: spv.Return
     spv.Return
   ^continue:
     spv.Branch ^header
^merge:
     spv.mlir.merge
   }
   %one = spv.constant 1 : i32
   spv.ReturnValue %one : i32
 }
 
 // CHECK-LABEL: func @in_loop
 func @in_loop(%cond : i1) -> (i32) {
-  spv.loop {
+  spv.mlir.loop {
     spv.Branch ^header
   ^header:
     spv.BranchConditional %cond, ^body, ^merge
   ^body:
     %zero = spv.constant 0 : i32
     // CHECK: spv.ReturnValue
     spv.ReturnValue %zero : i32
   ^continue:

mlir/test/Dialect/SPIRV/Transforms/inlining.mlir

spv.func @calling_selection_no_ret_func() "None" {
     spv.Return
   }
 }
 
 // -----
 
 spv.module Logical GLSL450 {
   spv.func @callee(%cond : i1) -> () "None" {
-    spv.loop {
+    spv.mlir.loop {
       spv.Branch ^header
     ^header:
       spv.BranchConditional %cond, ^body, ^merge
     ^body:
       spv.Return
     ^continue:
       spv.Branch ^header
     ^merge:
spv.func @calling_loop_ret_func() "None" {
     spv.Return
   }
 }
 
 // -----
 
 spv.module Logical GLSL450 {
   spv.func @callee(%cond : i1) -> () "None" {
-    spv.loop {
+    spv.mlir.loop {
       spv.Branch ^header
     ^header:
       spv.BranchConditional %cond, ^body, ^merge
     ^body:
       spv.Branch ^continue
     ^continue:
       spv.Branch ^header
     ^merge:
       spv.mlir.merge
     }
     spv.Return
   }
 
   // CHECK-LABEL: @calling_loop_no_ret_func
   spv.func @calling_loop_no_ret_func() "None" {
     // CHECK-NEXT: %[[TRUE:.*]] = spv.constant true
     %0 = spv.constant true
-    // CHECK-NEXT: spv.loop
+    // CHECK-NEXT: spv.mlir.loop
     // CHECK-NEXT:   spv.Branch ^bb1
     // CHECK-NEXT: ^bb1:
     // CHECK-NEXT:   spv.BranchConditional %[[TRUE]], ^bb2, ^bb4
     // CHECK-NEXT: ^bb2:
     // CHECK-NEXT:   spv.Branch ^bb3
     // CHECK-NEXT: ^bb3:
     // CHECK-NEXT:   spv.Branch ^bb1
     // CHECK-NEXT: ^bb4:

mlir/test/Target/SPIRV/debug.mlir

spv.func @memory_accesses(%arg0 : !spv.ptr<!spv.array<4x!spv.array<4xf32>>, StorageBuffer>, %arg1 : i32, %arg2 : i32) "None" {
     spv.Return
   }
 
   spv.func @loop(%count : i32) -> () "None" {
     %zero = spv.constant 0: i32
     %one = spv.constant 1: i32
     %ivar = spv.Variable init(%zero) : !spv.ptr<i32, Function>
     %jvar = spv.Variable init(%zero) : !spv.ptr<i32, Function>
-    spv.loop {
+    spv.mlir.loop {
       // CHECK: loc({{".*debug.mlir"}}:75:5)
       spv.Branch ^header
     ^header:
       %ival0 = spv.Load "Function" %ivar : i32
       %icmp = spv.SLessThan %ival0, %count : i32
       // CHECK: loc({{".*debug.mlir"}}:75:5)
       spv.BranchConditional %icmp, ^body, ^merge
     ^body:
       spv.Store "Function" %jvar, %zero : i32
-      spv.loop {
+      spv.mlir.loop {
         // CHECK: loc({{".*debug.mlir"}}:85:7)
         spv.Branch ^header
       ^header:
         %jval0 = spv.Load "Function" %jvar : i32
         %jcmp = spv.SLessThan %jval0, %count : i32
         // CHECK: loc({{".*debug.mlir"}}:85:7)
         spv.BranchConditional %jcmp, ^body, ^merge
       ^body:

mlir/test/Target/SPIRV/function-call.mlir

spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
   }
   spv.func @f_2(%arg0 : !spv.ptr<!spv.array<4xf32>, Input>) -> !spv.ptr<!spv.array<4xf32>, Input> "None" {
     spv.ReturnValue %arg0 : !spv.ptr<!spv.array<4xf32>, Input>
   }
 
   spv.func @f_loop_with_function_call(%count : i32) -> () "None" {
     %zero = spv.constant 0: i32
     %var = spv.Variable init(%zero) : !spv.ptr<i32, Function>
-    spv.loop {
+    spv.mlir.loop {
       spv.Branch ^header
     ^header:
       %val0 = spv.Load "Function" %var : i32
       %cmp = spv.SLessThan %val0, %count : i32
       spv.BranchConditional %cmp, ^body, ^merge
     ^body:
       spv.Branch ^continue
     ^continue:

mlir/test/Target/SPIRV/loop.mlir

 // RUN: mlir-translate -split-input-file -test-spirv-roundtrip %s | FileCheck %s
 
 // Single loop
 
 spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
   // for (int i = 0; i < count; ++i) {}
   spv.func @loop(%count : i32) -> () "None" {
     %zero = spv.constant 0: i32
     %one = spv.constant 1: i32
     %var = spv.Variable init(%zero) : !spv.ptr<i32, Function>
 
 // CHECK:        spv.Branch ^bb1
 // CHECK-NEXT: ^bb1:
-// CHECK-NEXT:   spv.loop
-    spv.loop {
+// CHECK-NEXT:   spv.mlir.loop
+    spv.mlir.loop {
 // CHECK-NEXT:     spv.Branch ^bb1
       spv.Branch ^header
 
 // CHECK-NEXT:   ^bb1:
     ^header:
 // CHECK-NEXT:     spv.Load
       %val0 = spv.Load "Function" %var : i32
 // CHECK-NEXT:     spv.SLessThan
spv.func @loop_kernel() "None" {
     %2 = spv.AccessChain %0[%1] : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>, i32
     %3 = spv.mlir.addressof @GV2 : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>
     %5 = spv.AccessChain %3[%1] : !spv.ptr<!spv.struct<(!spv.array<10 x f32, stride=4> [0])>, StorageBuffer>, i32
     %6 = spv.constant 4 : i32
     %7 = spv.constant 42 : i32
     %8 = spv.constant 2 : i32
 // CHECK:        spv.Branch ^bb1(%{{.*}} : i32)
 // CHECK-NEXT: ^bb1(%[[OUTARG:.*]]: i32):
-// CHECK-NEXT:   spv.loop {
-    spv.loop {
+// CHECK-NEXT:   spv.mlir.loop {
+    spv.mlir.loop {
 // CHECK-NEXT:     spv.Branch ^bb1(%[[OUTARG]] : i32)
       spv.Branch ^header(%6 : i32)
 // CHECK-NEXT:   ^bb1(%[[HEADARG:.*]]: i32):
     ^header(%9: i32):
       %10 = spv.SLessThan %9, %7 : i32
 // CHECK:          spv.BranchConditional %{{.*}}, ^bb2, ^bb3
       spv.BranchConditional %10, ^body, ^merge
 // CHECK-NEXT:   ^bb2:     // pred: ^bb1
spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
   spv.func @loop(%count : i32) -> () "None" {
     %zero = spv.constant 0: i32
     %one = spv.constant 1: i32
     %ivar = spv.Variable init(%zero) : !spv.ptr<i32, Function>
     %jvar = spv.Variable init(%zero) : !spv.ptr<i32, Function>
 
 // CHECK:        spv.Branch ^bb1
 // CHECK-NEXT: ^bb1:
-// CHECK-NEXT:   spv.loop control(Unroll)
-    spv.loop control(Unroll) {
+// CHECK-NEXT:   spv.mlir.loop control(Unroll)
+    spv.mlir.loop control(Unroll) {
 // CHECK-NEXT:     spv.Branch ^bb1
       spv.Branch ^header
 
 // CHECK-NEXT:   ^bb1:
     ^header:
 // CHECK-NEXT:     spv.Load
       %ival0 = spv.Load "Function" %ivar : i32
 // CHECK-NEXT:     spv.SLessThan
       %icmp = spv.SLessThan %ival0, %count : i32
 // CHECK-NEXT:     spv.BranchConditional %{{.*}}, ^bb2, ^bb5
       spv.BranchConditional %icmp, ^body, ^merge
 
 // CHECK-NEXT:   ^bb2:
     ^body:
 // CHECK-NEXT:     spv.constant 0
 // CHECK-NEXT:     spv.Store
       spv.Store "Function" %jvar, %zero : i32
 // CHECK-NEXT:     spv.Branch ^bb3
 // CHECK-NEXT:   ^bb3:
-// CHECK-NEXT:     spv.loop control(DontUnroll)
-      spv.loop control(DontUnroll) {
+// CHECK-NEXT:     spv.mlir.loop control(DontUnroll)
+      spv.mlir.loop control(DontUnroll) {
 // CHECK-NEXT:       spv.Branch ^bb1
         spv.Branch ^header
 
 // CHECK-NEXT:     ^bb1:
       ^header:
 // CHECK-NEXT:       spv.Load
         %jval0 = spv.Load "Function" %jvar : i32
 // CHECK-NEXT:       spv.SLessThan

mlir/test/Target/SPIRV/phi.mlir

spv.func @fmul_kernel() "None" {
     %21 = spv.mlir.addressof @__builtin_var_NumWorkgroups__ : !spv.ptr<vector<3xi32>, Input>
     %22 = spv.Load "Input" %21 : vector<3xi32>
     %23 = spv.CompositeExtract %22[1 : i32] : vector<3xi32>
     %30 = spv.IMul %11, %4 : i32
     %31 = spv.IMul %23, %4 : i32
 
 // CHECK:   spv.Branch ^[[FN_BB:.*]](%{{.*}} : i32)
 // CHECK: ^[[FN_BB]](%[[FN_BB_ARG:.*]]: i32):
-// CHECK:   spv.loop {
-    spv.loop {
+// CHECK:   spv.mlir.loop {
+    spv.mlir.loop {
 // CHECK:     spv.Branch ^bb1(%[[FN_BB_ARG]] : i32)
       spv.Branch ^bb1(%30 : i32)
 // CHECK:   ^[[LP1_HDR:.*]](%[[LP1_HDR_ARG:.*]]: i32):
     ^bb1(%32: i32):
 // CHECK:     spv.SLessThan
       %33 = spv.SLessThan %32, %3 : i32
 // CHECK:     spv.BranchConditional %{{.*}}, ^[[LP1_BDY:.*]], ^[[LP1_MG:.*]]
       spv.BranchConditional %33, ^bb2, ^bb3
 // CHECK:   ^[[LP1_BDY]]:
     ^bb2:
 // CHECK:     %[[MUL:.*]] = spv.IMul
       %34 = spv.IMul %8, %5 : i32
 // CHECK:     spv.IMul
       %35 = spv.IMul %20, %5 : i32
 // CHECK:     spv.Branch ^[[LP1_CNT:.*]](%[[MUL]] : i32)
 // CHECK:   ^[[LP1_CNT]](%[[LP1_CNT_ARG:.*]]: i32):
-// CHECK:     spv.loop {
-      spv.loop {
+// CHECK:     spv.mlir.loop {
+      spv.mlir.loop {
 // CHECK:       spv.Branch ^[[LP2_HDR:.*]](%[[LP1_CNT_ARG]] : i32)
         spv.Branch ^bb1(%34 : i32)
 // CHECK:     ^[[LP2_HDR]](%[[LP2_HDR_ARG:.*]]: i32):
       ^bb1(%37: i32):
 // CHECK:       spv.SLessThan %[[LP2_HDR_ARG]]
         %38 = spv.SLessThan %37, %5 : i32
 // CHECK:       spv.BranchConditional %{{.*}}, ^[[LP2_BDY:.*]], ^[[LP2_MG:.*]]
         spv.BranchConditional %38, ^bb2, ^bb3
spv.func @fmul_kernel() "None" {
     %cst4 = spv.constant 4 : i32
 
     %val1 = spv.constant 43 : i32
     %val2 = spv.constant 44 : i32
 
 // CHECK:        spv.constant 43
 // CHECK-NEXT:   spv.Branch ^[[BB1:.+]](%{{.+}} : i32)
 // CHECK-NEXT: ^[[BB1]](%{{.+}}: i32):
-// CHECK-NEXT:   spv.loop
-    spv.loop { // loop 1
+// CHECK-NEXT:   spv.mlir.loop
+    spv.mlir.loop { // loop 1
       spv.Branch ^bb1(%val1 : i32)
     ^bb1(%loop1_bb_arg: i32):
       %loop1_lt = spv.SLessThan %loop1_bb_arg, %cst4 : i32
       spv.BranchConditional %loop1_lt, ^bb2, ^bb3
     ^bb2:
       %loop1_add = spv.IAdd %loop1_bb_arg, %cst4 : i32
       spv.Branch ^bb1(%loop1_add : i32)
     ^bb3:
       spv.mlir.merge
     }
 
 // CHECK:        spv.constant 44
 // CHECK-NEXT:   spv.Branch ^[[BB2:.+]](%{{.+}} : i32)
 // CHECK-NEXT: ^[[BB2]](%{{.+}}: i32):
-// CHECK-NEXT:   spv.loop
-    spv.loop { // loop 2
+// CHECK-NEXT:   spv.mlir.loop
+    spv.mlir.loop { // loop 2
       spv.Branch ^bb1(%val2 : i32)
     ^bb1(%loop2_bb_arg: i32):
       %loop2_lt = spv.SLessThan %loop2_bb_arg, %cst4 : i32
       spv.BranchConditional %loop2_lt, ^bb2, ^bb3
     ^bb2:
       %loop2_add = spv.IAdd %loop2_bb_arg, %cst4 : i32
       spv.Branch ^bb1(%loop2_add : i32)
     ^bb3: