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[ARM] Move double vector insert patterns using vins to DAG combine
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Authored by dmgreen on Feb 17 2021, 9:31 AM.

Details

Summary

This removes the existing patterns for inserting two lanes into an f16/i16 vector register using VINS, instead using a DAG combine to pattern match the same code sequences. The tablegen patterns were already on the large side (foreach LANE = [0, 2, 4, 6]) and were not handling all the cases they could. Moving that to a DAG combine, whilst not less code, allows us to more easily control and expand the selections on VINSs. For example this allows us to remove the AddedComplexity on VCVTT.

The extra trick that this has learned in the process is to move two adjacent lanes using a single f32 vmov, allowing some extra inefficiencies to be removed.

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Event Timeline

dmgreen created this revision.Feb 17 2021, 9:31 AM
dmgreen requested review of this revision.Feb 17 2021, 9:31 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 17 2021, 9:31 AM
This revision is now accepted and ready to land.Feb 19 2021, 12:17 AM
RKSimon added inline comments.
llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
3115

@dmgreen I'm seeing unused variable warnings for Val1Copy, Val2Copy + VecCopy

Yeah, I saw from the bots. Removed in 188f15d973101649f7172e353f85727b41f2ffa8. Sorry for the noise.

dmgreen closed this revision.Feb 22 2021, 6:19 AM