[PowerPC][AIX] Enable the default AltiVec ABI on AIX

[ZarkoCA]

Summary

This patch adds support for the default AltiVec ABI for AIX.

Vector registers 20 through 31 are marked as reserved and cannot
be used in the default ABI. This patch adds handling for this case
and also remove the default AltiVec ABI errors.

[sfertile]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

202–203

Can we instead structure it this way?

if (TM.isPPC64()) {
  if (Subtarget.hasAltivec() &&
      (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
    return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
                  : CSR_PPC64_Altivec_SaveList;
  }
  return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
}

344

Use a range based for loop.

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

215

The patch adds a lot of whitespace errors. I'm betting its from this mir output. Please highlight trailing whitespace and fix it up.

[ZarkoCA]

Address comments:

1. Remove trailing whitespaces
2. Use a range based loop
3. Clean up if use

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

202–203

I think your suggestion is simpler. Thanks, I was looking for ways to make it cleaner.

344

Thanks for catching this oversight by me.

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

215

They should hopefully be gone now.

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

59

Is this considered to "modify" the reserved registers that are marked as clobbers? I don't think D93659 should generate a traceback table that indicates that the reserved registers are saved in the save area if they are not.

[hubert.reinterpretcast]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

59

Looping back here:

• We are okay to omit both the save and the restore here when a user insists on using the reserved registers (even though they are not supposed to). Note: XL oddly generates the save but not the restore.
• We will try to generate a warning when the user specifies the reserved registers for inline assembly/explicit register variables.

Separately from this patch:

• We need to fix the vector save/restore to save all of the registers in the range for the unwinder to restore.
• We need to update the traceback table emission to signal cases where the field indicating the number of saved vector registers is reliable.
• D93659 should be updated to not indicate any saved non-volatile vector registers when the default AIX vector ABI is used.

[ZarkoCA]

• Add warning when using reserved vector registers in the default AltiVec ABI

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15174–15175

Is there a lot of precedent for "raw output" to stderr for warnings from the back-end? Can we diagnose this closer to where err_asm_unknown_register_name is handled in the front-end?

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

344

I'm not seeing a range-based for loop here.

[nemanjai]

I personally don't feel that the included test case changes are adequate for testing this patch. First of all, the test case probably does too much without equivalent checks - there is 32/64 bit, default/extended ABI and MIR/ASM testing all in a single file and the checks for default/extended at least do not appear to line up. There is no explicit checks that no spills/reloads exist for the reserved regs with default ABI.

Furthermore, I think you should have a test case where you clobber all FPR's and VSR's except the ones in the vr20 - vr31 range in functions that perform FP/vector computations with checks that show the affected registers are not allocated.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15173

Seems like this should be producing a warning for a range of registers, but the condition covers an unterminated range. That seems odd and potentially wrong. Why is this not:

if ((R.first >= PPC::V20 && R.first <= PPC::V31) ||
    (R.first >= PPC::VF20 && R.first <= PPC::VF31))

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

348

Since this effectively shrinks the register class by 12 registers, it is worth double checking that marking these registers as reserved without providing an alternate allocation order does not adversely affect register pressure estimates.

[ZarkoCA]

Address comments:

• split extended and default Altivec ABI tests in different files
• add a test case to check that reserved vector registers are not used even when all fprs and vector regs are clobbered

[ZarkoCA]

In D96351#2580598, @nemanjai wrote:

Furthermore, I think you should have a test case where you clobber all FPR's and VSR's except the ones in the vr20 - vr31 range in functions that perform FP/vector computations with checks that show the affected registers are not allocated.

I added all_fprs_and_vecregs and then checked to see that vr20-31 are not allocated. The check is only in MIR since there is no way to distinguish float, vector, and gprs in assembly on AIX by register number alone (we don't have ppc-full-reg-names on AIX yet).

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15174–15175

I've seen some cases in other targets but, no, there is not a lot of precedent for this in PPC subtarget.

I investigated with making the suggested change where err_asm_unknown_register_name is handled in clang but it seems to me making the changes there is at least a patch of its own. I wasn't able to find an efficient way to do it for now using that method.

If you feel strongly about this, I could remove the warning here and then make a follow on patch to add the warning the front end. My own feeling is that the warning should come from the frond end and this is a comprise for now.

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

348

Is the way to test this to check the number of spills we get when using the different Altivec ABIs? In the test case all_fprs_and_vecregs I just added in llvm/test/CodeGen/PowerPC/aix-csr-vector.ll I didn't notice a difference in the number of registers spills. Would adding a check for that be sufficient?

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15174–15175

I think having something here for now is better than having nothing. Please add a FIXME comment to implement the warning in the front-end to replace this one (and do the follow up patch after dealing with the functional issues on your plate for vector support right now).

Also, can you point me to the test for this?

[ZarkoCA]

Add a test case for the warning message and add a FIXME to implement the warning in the front end.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15174–15175

Thanks Hubert, I added a FIXME and the test case for the warning message.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15161

llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll

1 ↗

(On Diff #326075)

If I'm getting the gist of this correctly, there's a plain rename that could be done instead. I suggest checking in the rename of the extabi test separately from this patch.

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

345–348

If the code worked before the switch to the range-based for loop, then I suspect it doesn't now.

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

There's no need to have the DFL prefix is it is always used with the corresponding "base" prefix.

[ZarkoCA]

• Remove test added in NFC commit
• fix loop code so now it works

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-csr-vector-extabi.ll

1 ↗

(On Diff #326075)

Thanks, this makes this patch simpler. Did this in commit 1c051b7b704257ed9a7

[sfertile]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

3

Minor nit: when there is a single check prefix use --check-prefix=

26

Ideally we would either have check-nots for v20/v26/v31 before and after the INLINEASM instruction(or APP/NO_APP). Or maybe if you check for the basic-block label then check-next the following instructions to the blr might be an equivalent way to show the same understanding.

llvm/test/CodeGen/PowerPC/aix-inlineasm-reserved-reg-dflt-warn.ll

3

Minor nit: Just use 'CHECK:' so we can drop the --check-prefixes

[ZarkoCA]

Added CHECK-NOT in test cases.
changed "check-prefixes" to "check-prefix"
Reworded one comment

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

26

I tried to address your comment as best as I could. Made it check for whether we load and store to those vector registers. In some cases it was not possible to reliably check for the vector registers since, for now, we can only check for the register number in assembly.

[sfertile]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

15161

I don't see this update.

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

348

This comment made me realize we need to update PPCRegisterInfo::getRegPressureLimit

[ZarkoCA]

Update PPCRegisterInfo::getRegPressureLimit
Fixed comment typo missed previously

[sfertile]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

446

With this change we will need to split up these cases.

The pre VSX register sets are the easiest to explain:

F8RC --> This is the F0-F31, which represents the 32 fprs with type f64.
F4RC --> This is the same as F8RC but with type f32.

These register sets won't change in the default ABI and will still have 32 available registers.

VRRC --> This is V0-V31 and represents the vector registers. With the extended ABI we can access all of them, with the default ABI we have the limited set of the first 20.

Once we add VSX it gets complicated: the other register sets are how we represent the registers with VSX. VSX has 64 128-bit wide registers. The fprs are mapped into element 0 of the first 32 VSX registers (VSR0-VSR31), with the vrs are mapped into the the second set of 32 VSX registers (VSR32-VSR64).

VFRC --> This is the set of 32 64-bit floating point sub registers not overlapped by the fprs (vsr32-vsr64). Used in instructions like lxsd/stxsd where we encode a register number N between 0-31 in the instruction but the instruction targets the sub register 32 + N.

VSLRC --> The 32 128-bit registers that the fprs overlap (vs0-vsr31).

VSRC --> VSLRC U VR vsr0-vsr31 + vsr31-vsr63 = vsr0-vsr63, or all the vsx vector registers.
VSFRC --> VFRC U F8RC all the 64-bit sub registers of the vsx vector registers.
VSSRC --> Same as VSFRC but the with type f32.

The qvecnvol option doesn't mention vsx registers but I would assume any that overlap the VRs are affected the same way, and the scalar registers which overlap vsr0-vsr31 are unaffectedly by the option. I'm not sure if there is any restriction on the vector registers vsr0-vsr31 in the default ABI.

[ZarkoCA]

Try to correct register pressure determination.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

446

Thanks for this detailed explanation.
I updated the switch cases to reflect my understanding of this.

case PPC::VRRCRegClassID: {
    const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
    if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
      return 20 - DefaultSafety;
  }
    LLVM_FALLTHROUGH;

The above seems straightforward to me but I can also change the fallthrough if it's not preferred.

I am less certain about this:

case PPC::VSRCRegClassID: {
  const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
  if (!TM.getAIXExtendedAltivecABI() && Subtarget.isAIXABI())
    return 64 - 12 - DefaultSafety;
}
  return 64 - DefaultSafety;

In the default ABI, VSX registers vsr54-63 should map to default abi registers v20-v31 and be reserved, and it's what I get from looking at PPCRegisterInfo.td.

343 def VRRC : RegisterClass<"PPC",
344                          [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32,v2f64, f128],
345                          128,
346                          (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
347                              V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
348                              V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
...
355 def VSRC  : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
356                           (add VSLRC, VRRC)>;

[sfertile]

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

445

VFRC is the sub registers of the vsx registers that 'overlap' the VRs, so when we only have 20 vr, then we only have 20 subregistes as well.

447

I think it best to avoid the fallthrough.

451

All three of these reg classes will have the same count, since if we reduce the vector registers by 12, then we also lose the sub registers of those vector registers.

[ZarkoCA]

Correct switch case

[sfertile]

One minor comment but otherwise LGTM.

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

454

Really minor nit: Either just use available register count like the other cases (ie 52 - DefaultSafety) or name the constant 12 something descriptive like 'DefaultAIXABIReservedVRCount` and use it in both places we have reduced register counts.

[ZarkoCA]

Use reduce register count.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
                    CCState &State) {
 
   const PPCSubtarget &Subtarget = static_cast<const PPCSubtarget &>(
       State.getMachineFunction().getSubtarget());
   const bool IsPPC64 = Subtarget.isPPC64();
   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
 
-  if (ValVT.isVector() && !State.getMachineFunction()
-                               .getTarget()
-                               .Options.EnableAIXExtendedAltivecABI)
-    report_fatal_error("the default Altivec AIX ABI is not yet supported");
-
   if (ValVT == MVT::f128)
     report_fatal_error("f128 is unimplemented on AIX.");
 
   if (ArgFlags.isNest())
     report_fatal_error("Nest arguments are unimplemented.");
 
   static const MCPhysReg GPR_32[] = {// 32-bit registers.
                                      PPC::R3, PPC::R4, PPC::R5, PPC::R6,
return std::make_pair(TRI->getMatchingSuperReg(R.first,
                             PPC::sub_32, &PPC::G8RCRegClass),
                           &PPC::G8RCRegClass);
 
   // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
   if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
     R.first = PPC::CR0;
     R.second = &PPC::CRRCRegClass;
   }
+//FIXME: This warning should ideally emitted in the front end.
+  const auto &TM = getTargetMachine();
+  if (Subtarget.isAIXABI() && !TM.getAIXExtendedAltivecABI()) {
+    if (((R.first >= PPC::V20 && R.first <= PPC::V31) ||
+         (R.first >= PPC::VF20 && R.first <= PPC::VF31)) &&
+        (R.second == &PPC::VSRCRegClass || R.second == &PPC::VSFRCRegClass))
+      errs() << "warning: vector registers 20 to 32 are reserved in the "
+                "default AIX AltiVec ABI and cannot be used\n";
+  }
 
   return R;
 }
 
 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
 /// vector.  If it is invalid, don't add anything to Ops.
 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
                                                      std::string &Constraint,
                                                      std::vector<SDValue>&Ops,
                                                      SelectionDAG &DAG) const {
   SDValue Result;
 
   // Only support length 1 constraints.
   if (Constraint.length() > 1) return;

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

PPCRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
   if (TM.isPPC64())
     return &PPC::G8RCRegClass;
   return &PPC::GPRCRegClass;
 }
 
 const MCPhysReg*
 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
   const PPCSubtarget &Subtarget = MF->getSubtarget<PPCSubtarget>();
-  if (Subtarget.isAIXABI() &&
-      (Subtarget.hasAltivec() && !TM.getAIXExtendedAltivecABI()))
-    report_fatal_error("the default AIX Altivec ABI is not yet "
-                       "supported.");
   if (MF->getFunction().getCallingConv() == CallingConv::AnyReg) {
     if (!TM.isPPC64() && Subtarget.isAIXABI())
       report_fatal_error("AnyReg unimplemented on 32-bit AIX.");
     if (Subtarget.hasVSX())
       return CSR_64_AllRegs_VSX_SaveList;
     if (Subtarget.hasAltivec())
       return CSR_64_AllRegs_Altivec_SaveList;
     return CSR_64_AllRegs_SaveList;
if (MF->getFunction().getCallingConv() == CallingConv::Cold) {
     if (Subtarget.hasAltivec())
       return CSR_SVR32_ColdCC_Altivec_SaveList;
     else if (Subtarget.hasSPE())
       return CSR_SVR32_ColdCC_SPE_SaveList;
     return CSR_SVR32_ColdCC_SaveList;
   }
   // Standard calling convention CSRs.
   if (TM.isPPC64()) {
-    if (Subtarget.hasAltivec())
+    if (Subtarget.hasAltivec() &&
+        (!Subtarget.isAIXABI() || TM.getAIXExtendedAltivecABI())) {
       return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
                     : CSR_PPC64_Altivec_SaveList;
+    }
     return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
   }
   // 32-bit targets.
   if (Subtarget.isAIXABI()) {
     if (Subtarget.hasAltivec())
-      return CSR_AIX32_Altivec_SaveList;
+      return TM.getAIXExtendedAltivecABI() ? CSR_AIX32_Altivec_SaveList
+                                           : CSR_AIX32_SaveList;
     return CSR_AIX32_SaveList;
   }
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
   else if (Subtarget.hasSPE())
     return CSR_SVR432_SPE_SaveList;
   return CSR_SVR432_SaveList;
 }
 
 const uint32_t *
 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
                                       CallingConv::ID CC) const {
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   if (CC == CallingConv::AnyReg) {
     if (Subtarget.hasVSX())
       return CSR_64_AllRegs_VSX_RegMask;
     if (Subtarget.hasAltivec())
       return CSR_64_AllRegs_Altivec_RegMask;
     return CSR_64_AllRegs_RegMask;
   }
 
   if (Subtarget.isAIXABI()) {
-    return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
-                                                  : CSR_PPC64_RegMask)
-                        : (Subtarget.hasAltivec() ? CSR_AIX32_Altivec_RegMask
-                                                  : CSR_AIX32_RegMask);
+    return TM.isPPC64()
+               ? ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
+                      ? CSR_PPC64_Altivec_RegMask
+               : ((Subtarget.hasAltivec() && TM.getAIXExtendedAltivecABI())
+                      ? CSR_AIX32_Altivec_RegMask
   }
 
   if (CC == CallingConv::Cold) {
     return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
                                                   : CSR_SVR64_ColdCC_RegMask)
                         : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
                                                   : (Subtarget.hasSPE()
                                                   ? CSR_SVR32_ColdCC_SPE_RegMask
if (Subtarget.is32BitELFABI() && IsPositionIndependent)
     markSuperRegs(Reserved, PPC::R30);
 
   // Reserve Altivec registers when Altivec is unavailable.
   if (!Subtarget.hasAltivec())
     for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
          IE = PPC::VRRCRegClass.end(); I != IE; ++I)
       markSuperRegs(Reserved, *I);
 
+  if (Subtarget.isAIXABI() && Subtarget.hasAltivec() &&
+      !TM.getAIXExtendedAltivecABI()) {
+    // When the AIX default Vector enabled mode is used, VR20-VR31 are
+    // reserved and cannot be used.
+    for (auto Reg : CSR_Altivec_SaveList) {
+      if (Reg == 0)
+        break;
+      markSuperRegs(Reserved, Reg);
+    }
+  }
+
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 
 bool PPCRegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF) const {
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   const PPCInstrInfo *InstrInfo =  Subtarget.getInstrInfo();
   const MachineFrameInfo &MFI = MF.getFrameInfo();
unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
   case PPC::G8RCRegClassID:
   case PPC::GPRCRegClassID: {
     unsigned FP = TFI->hasFP(MF) ? 1 : 0;
     return 32 - FP - DefaultSafety;
   }
   case PPC::F8RCRegClassID:
   case PPC::F4RCRegClassID:
   case PPC::VRRCRegClassID:
   case PPC::VFRCRegClassID:
   case PPC::VSLRCRegClassID:
     return 32 - DefaultSafety;
   case PPC::VSRCRegClassID:
   case PPC::VSFRCRegClassID:
   case PPC::VSSRCRegClassID:
     return 64 - DefaultSafety;
   case PPC::CRRCRegClassID:
     return 8 - DefaultSafety;
   }
 }
 
 const TargetRegisterClass *
 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
                                            const MachineFunction &MF) const {
   const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>();
   if (Subtarget.hasVSX()) {
     // With VSX, we can inflate various sub-register classes to the full VSX

llvm/test/CodeGen/PowerPC/aix-csr-vector.ll

+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs -mcpu=pwr7 \
+; RUN:     -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefixes=MIR32 %s
+
+; RUN: llc -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefix=ASM32 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec -stop-after=prologepilog < %s | \
+; RUN:   FileCheck --check-prefixes=MIR64 %s
+
+; RUN: llc -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec < %s | \
+; RUN:   FileCheck --check-prefixes=ASM64 %s
+
+define dso_local void @vec_regs() {
+  entry:
+    call void asm sideeffect "", "~{v13},~{v20},~{v26},~{v31}"()
+      ret void
+}
+
+; MIR32-LABEL:   name:            vec_regs
+
+; MIR32:         fixedStack:      []
+; MIR32:         INLINEASM
+; MIR32:         BLR implicit $lr, implicit $rm
+
+; MIR64-LABEL:   name:            vec_regs
+
+; MIR64:         fixedStack:      []
+; MIR64-LABEL:   INLINEASM
+; MIR64:         BLR8 implicit $lr8, implicit $rm
+
+; ASM32-LABEL:   .vec_regs:
+
+; ASM32-DAG:     #APP
+; ASM32-DAG:     #NO_APP
+; ASM32:         blr
+
+; ASM64-LABEL:   .vec_regs:
+
+; ASM64-DAG:     #APP
+; ASM64-DAG:     #NO_APP
+; ASM64:         blr
+
+define dso_local void @fprs_gprs_vecregs() {
+    call void asm sideeffect "", "~{r14},~{r25},~{r31},~{f14},~{f21},~{f31},~{v20},~{v26},~{v31}"()
+      ret void
+}
+
+; MIR32-LABEL:   name:            fprs_gprs_vecregs
+
+; MIR32:         fixedStack:
+
+; MIR32:         liveins: $r14, $r25, $r31, $f14, $f21, $f31
+
+; MIR32-DAG:     STW killed $r14, -216, $r1 :: (store 4 into %fixed-stack.5, align 8)
+; MIR32-DAG:     STW killed $r25, -172, $r1 :: (store 4 into %fixed-stack.4)
+; MIR32-DAG:     STW killed $r31, -148, $r1 :: (store 4 into %fixed-stack.3)
+; MIR32-DAG:     STFD killed $f14, -144, $r1 :: (store 8 into %fixed-stack.2, align 16)
+; MIR32-DAG:     STFD killed $f21, -88, $r1 :: (store 8 into %fixed-stack.1)
+; MIR32-DAG:     STFD killed $f31, -8, $r1 :: (store 8 into %fixed-stack.0)
+
+; MIR32-LABEL:   INLINEASM
+
+; MIR32-DAG:     $r14 = LWZ -216, $r1 :: (load 4 from %fixed-stack.5, align 8)
+; MIR32-DAG:     $r25 = LWZ -172, $r1 :: (load 4 from %fixed-stack.4)
+; MIR32-DAG:     $r31 = LWZ -148, $r1 :: (load 4 from %fixed-stack.3)
+; MIR32-DAG:     $f14 = LFD -144, $r1 :: (load 8 from %fixed-stack.2, align 16)
+; MIR32-DAG:     $f21 = LFD -88, $r1 :: (load 8 from %fixed-stack.1)
+; MIR32-DAG:     $f31 = LFD -8, $r1 :: (load 8 from %fixed-stack.0)
+; MIR32-DAG:     BLR implicit $lr, implicit $rm
+
+; MIR64:         fixedStack:
+
+; MIR64:         liveins: $x14, $x25, $x31, $f14, $f21, $f31
+
+; MIR64-DAG:     STD killed $x14, -288, $x1 :: (store 8 into %fixed-stack.5, align 16)
+; MIR64-DAG:     STD killed $x25, -200, $x1 :: (store 8 into %fixed-stack.4)
+; MIR64-DAG:     STD killed $x31, -152, $x1 :: (store 8 into %fixed-stack.3)
+; MIR64-DAG:     STFD killed $f14, -144, $x1 :: (store 8 into %fixed-stack.2, align 16)
+; MIR64-DAG:     STFD killed $f21, -88, $x1 :: (store 8 into %fixed-stack.1)
+; MIR64-DAG:     STFD killed $f31, -8, $x1 :: (store 8 into %fixed-stack.0)
+
+; MIR64-LABEL:   INLINEASM
+
+; MIR64-DAG:     $x14 = LD -288, $x1 :: (load 8 from %fixed-stack.5, align 16)
+; MIR64-DAG:     $x25 = LD -200, $x1 :: (load 8 from %fixed-stack.4)
+; MIR64-DAG:     $x31 = LD -152, $x1 :: (load 8 from %fixed-stack.3)
+; MIR64-DAG:     $f14 = LFD -144, $x1 :: (load 8 from %fixed-stack.2, align 16)
+; MIR64-DAG:     $f21 = LFD -88, $x1 :: (load 8 from %fixed-stack.1)
+; MIR64-DAG:     $f31 = LFD -8, $x1 :: (load 8 from %fixed-stack.0)
+; MIR64:         BLR8 implicit $lr8, implicit $rm
+
+; ASM32-LABEL:   .fprs_gprs_vecregs:
+
+; ASM32-DAG:     stw 14, -216(1)                         # 4-byte Folded Spill
+; ASM32-DAG:     stw 25, -172(1)                         # 4-byte Folded Spill
+; ASM32-DAG:     stw 31, -148(1)                         # 4-byte Folded Spill
+; ASM32-DAG:     stfd 14, -144(1)                        # 8-byte Folded Spill
+; ASM32-DAG:     stfd 21, -88(1)                         # 8-byte Folded Spill
+; ASM32-DAG:     stfd 31, -8(1)                          # 8-byte Folded Spill
+; ASM32-DAG:     #APP
+; ASM32-DAG:     #NO_APP
+; ASM32-DAG:     lfd 31, -8(1)                           # 8-byte Folded Reload
+; ASM32-DAG:     lfd 21, -88(1)                          # 8-byte Folded Reload
+; ASM32-DAG:     lfd 14, -144(1)                         # 8-byte Folded Reload
+; ASM32-DAG:     lwz 31, -148(1)                         # 4-byte Folded Reload
+; ASM32-DAG:     lwz 25, -172(1)                         # 4-byte Folded Reload
+; ASM32-DAG:     lwz 14, -216(1)                         # 4-byte Folded Reload
+; ASM32:         blr
+
+; ASM64-LABEL    .fprs_gprs_vecregs:
+
+; ASM64-DAG:     std 14, -288(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     std 25, -200(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     std 31, -152(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stfd 14, -144(1)                        # 8-byte Folded Spill
+; ASM64-DAG:     stfd 21, -88(1)                         # 8-byte Folded Spill
+; ASM64-DAG:     stfd 31, -8(1)                          # 8-byte Folded Spill
+; ASM64-DAG:     #APP
+; ASM64-DAG:     #NO_APP
+; ASM64-DAG:     lfd 31, -8(1)                           # 8-byte Folded Reload
+; ASM64-DAG:     lfd 21, -88(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     lfd 14, -144(1)                         # 8-byte Folded Reload
+; ASM64-DAG:     ld 31, -152(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     ld 25, -200(1)                          # 8-byte Folded Reload
+; ASM64-DAG:     ld 14, -288(1)                          # 8-byte Folded Reload
+; ASM64:         blr
+
+define dso_local void @all_fprs_and_vecregs() {
+    call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31},~{v0},~{v1},~{v2},~{v3},~{v4},~{v5},~{v6}~{v7},~{v8},~{v9},~{v10},~{v11},~{v12},~{v13},~{v14},~{v15},~{v16},~{v17},~{v18},~{v19}"()
+      ret void
+}
+
+;; Check that reserved vectors are not used.
+; MIR32-LABEL:   all_fprs_and_vecregs
+
+; MIR32-NOT:     v20
+; MIR32-NOT:     v21
+; MIR32-NOT:     v22
+; MIR32-NOT:     v23
+; MIR32-NOT:     v24
+; MIR32-NOT:     v25
+; MIR32-NOT:     v26
+; MIR32-NOT:     v27
+; MIR32-NOT:     v28
+; MIR32-NOT:     v29
+; MIR32-NOT:     v30
+; MIR32-NOT:     v31
+
+; MIR64-LABEL:   all_fprs_and_vecregs
+
+; MIR64-NOT:     v20
+; MIR64-NOT:     v21
+; MIR64-NOT:     v22
+; MIR64-NOT:     v23
+; MIR64-NOT:     v24
+; MIR64-NOT:     v25
+; MIR64-NOT:     v26
+; MIR64-NOT:     v27
+; MIR64-NOT:     v28
+; MIR64-NOT:     v29
+; MIR64-NOT:     v30
+; MIR64-NOT:     v31

llvm/test/CodeGen/PowerPC/aix-inlineasm-reserved-reg-dflt-warn.ll

+; RUN: llc < %s -mtriple=powerpc-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec 2>&1 | \
+; RUN:   FileCheck --check-prefixes=DFLTWRN %s
+
+; RUN: llc < %s -mtriple=powerpc64-unknown-aix-xcoff -verify-machineinstrs \
+; RUN:     -mcpu=pwr7 -mattr=+altivec 2>&1 | \
+; RUN:   FileCheck --check-prefixes=DFLTWRN %s
+define dso_local void @vec_warn() {
+entry:
+  call void asm sideeffect "", "~{v23}"()
+  ret void
+}
+
+; DFLTWRN: warning: vector registers 20 to 32 are reserved in the default AIX AltiVec ABI and cannot be used

llvm/test/CodeGen/PowerPC/aix-vec-abi.ll

-; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
-; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s --check-prefix=DFLTERROR
-
-define void @vec_callee(<4 x i32> %vec1) {
-    ret void 
-}
-
-; DFLTERROR:  LLVM ERROR: the default Altivec AIX ABI is not yet supported