GlobalISel: Try to combine G_[SU]DIV and G_[SU]REM

[cdevadas]

Summary

It is good to have a combined divrem instruction when the
div and rem are computed from identical input operands.
Some targets can lower them through a single expansion that
computes both division and remainder. It effectively reduces
the number of instructions than individually expanding them.

[arsenm]

The legalizer should also get the code to split this back into the separate opcodes

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

946

This needs to have some kind of legalization check. We should only do this if either the combined divrem is legal or legalizable, or before legaliation

948–950

This can probably be an assert, the opcode should come from the tablegen opcode list

976

Should not construct single use MIRBuilders. There should be one available in the combiner state

llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp

72–76 ↗

(On Diff #321374)

Should be called by the generic tablegen code in include/llvm/Target/GlobalISel/Combine.td

llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir

5

Should add some vector tests. Also cases with other uses, and negative cases with mismatched signed/unsigned pairs

[paquette]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

948

Maybe something like this?

switch(Opcode) {
  default:
     llvm_unreachable("Unexpected opcode!");
  case TargetOpcode::G_SDIV:
  case TargetOpcode::G_UDIV:
      IsSigned = Opcode == TargetOpcode::G_SDIV;
      IsDiv = true;
      break;
  case TargetOpcode::G_SREM:
  case TargetOpcode::G_UREM:
     ...
}

957

Why not use Opcode? If it's a div, then Opcode == DivOpcode. If it's a rem, then Opcode == RemOpcode.

979

This part should go in a MatchInfo parameter like in the other combines. That should be passed along to an apply function which should perform the actual combine.

986

I think this should go in an applyCombineDivRem function like the other combines.

[cdevadas]

I am making it a generic pattern that comes from the Combine.td. Will update the patch soon.

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

957

Based on the signness of MI, here I am trying to get the other opcode to match.
And the check below matches the (sdiv, srem) or (udiv, urem) pair irrespective of their position.

[cdevadas]

Addressed the review comments:

Made the combiner pattern generic.
Added the necessary legalization check.
Legalized the G_[SU]DIVREM instruction.
Added vector tests and some negative tests.
Added two new tests for post-legalizer and legalizer-helper.

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1008–1009

Should just use the regular getVRegDef

1028

I'm worried about what happens if multiple div/rem users exist. Can you add some tests for that?

[paquette]

Can you add an entry for G_SDIVREM and G_UDIVREM to docs/GlobalISel/GenericOpcode.rst?

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

6304

Can the Legalizer changes come in a follow-up patch?

[cdevadas]

I will make an entry for the new opcodes in docs/GlobalISel/GenericOpcode.rst

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1028

This patch currently performs a one-to-one match. It doesn't look for multiple div/rem users.
For example, it won't optimally match the following pattern:
G_SDIV x, y, G_SREM x, y and an extra G_SDIV x, y
The first div/rem pair will be combined and the second div will be retained.
Instead, it should have generated d, r = G_SDIVREM x, y ; replace all users of the second G_SDIV with 'd' and then delete the extra G_SDIV as well.
I will rework this part.

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

6304

I thought about it initially. But it makes more sense to legalize the operations along with the patch that introduces the opcodes.

[cdevadas]

Improved the matcher function to identify a div/rem pair and any number of matching div and/or rem instructions.
Documented the new instructions in docs/GlobalISel/GenericOpcode.rst

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1028

I don't think this should be collecting a vector of other instructions and looking for redundant div/rems. It just needs to not crash if one of these extras exist

[cdevadas]

Reverting the recent changes to combine any matching extra div and rem instructions alongside the divrem instruction. The presence of the extra instruction shouldn't crash. Added tests to ensure that.

[cdevadas]

Used MachineInstr as the MatchInfo instead of the Register.
With this, the other matching MI will be directly available in the apply function.

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1021

I still suspect something is wrong with the insertion. I don't believe it's guaranteed that the first instruction you find will dominate the second, so you don't know where to place the insert point.

llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir

382–383

You can shorten the test by just copying tuple registers, we just lower arguments with the separate copies

[cdevadas]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1021

The instructions are visited in the top-down order and MI will always dominate the otherMI.

[cdevadas]

Addressed the review comments:
Used the dominance check to find the Insertion point.
Added a negative test when the dominance check fails to identify the insertion point.
Simplified the vector tests.

[arsenm]

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

1021

The combiner visits bottom up.

Actually if you check that these are in the same block, you can just use OtherMI as the insert point

1027

I'd rather keep all legality checks in the match function. But also I realized it should work if you check if the parent blocks are the same and then you can assume otherMI is earlier

[cdevadas]

The div/rem pair coming from different BB will have many scenarios that can complicate the match/apply functions and it is beyond the scope of the Combiner.
I will limit the pattern to match it for the pair coming from the same BB.

[cdevadas]

Match the div & rem only when they are from the same Basic Block.

[cdevadas]

ping

llvm/docs/GlobalISel/GenericOpcode.rst

 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 These each perform their respective integer arithmetic on a scalar.
 
 .. code-block:: none
 
   %2:_(s32) = G_ADD %0:_(s32), %1:_(s32)
 
+G_SDIVREM, G_UDIVREM
+^^^^^^^^^^^^^^^^^^^^
+
+Perform integer division and remainder thereby producing two results.
+
+.. code-block:: none
+
+  %div:_(s32), %rem:_(s32) = G_SDIVREM %0:_(s32), %1:_(s32)
+
 G_SADDSAT, G_UADDSAT, G_SSUBSAT, G_USUBSAT, G_SSHLSAT, G_USHLSAT
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
 Signed and unsigned addition, subtraction and left shift with saturation.
 
 .. code-block:: none
 
   %2:_(s32) = G_SADDSAT %0:_(s32), %1:_(s32)

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

public:
 
   bool matchSextTruncSextLoad(MachineInstr &MI);
   bool applySextTruncSextLoad(MachineInstr &MI);
 
   /// Match sext_inreg(load p), imm -> sextload p
   bool matchSextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
   bool applySextInRegOfLoad(MachineInstr &MI, std::tuple<Register, unsigned> &MatchInfo);
 
+  /// Try to combine G_[SU]DIV and G_[SU]REM into a single G_[SU]DIVREM
+  /// when their source operands are identical.
+  bool matchCombineDivRem(MachineInstr &MI, Register &Reg);
+  void applyCombineDivRem(MachineInstr &MI, Register &Reg);
+
   /// If a brcond's true block is not the fallthrough, make it so by inverting
   /// the condition and swapping operands.
   bool matchOptBrCondByInvertingCond(MachineInstr &MI);
   void applyOptBrCondByInvertingCond(MachineInstr &MI);
 
   /// If \p MI is G_CONCAT_VECTORS, try to combine it.
   /// Returns true if MI changed.
   /// Right now, we support:

llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h

public:
   LegalizeResult lowerAddSubSatToMinMax(MachineInstr &MI);
   LegalizeResult lowerAddSubSatToAddoSubo(MachineInstr &MI);
   LegalizeResult lowerShlSat(MachineInstr &MI);
   LegalizeResult lowerBswap(MachineInstr &MI);
   LegalizeResult lowerBitreverse(MachineInstr &MI);
   LegalizeResult lowerReadWriteRegister(MachineInstr &MI);
   LegalizeResult lowerSMULH_UMULH(MachineInstr &MI);
   LegalizeResult lowerSelect(MachineInstr &MI);
-
+  LegalizeResult lowerDIVREM(MachineInstr &MI);
 };
 
 /// Helper function that creates a libcall to the given \p Name using the given
 /// calling convention \p CC.
 LegalizerHelper::LegalizeResult
 createLibcall(MachineIRBuilder &MIRBuilder, const char *Name,
               const CallLowering::ArgInfo &Result,
               ArrayRef<CallLowering::ArgInfo> Args, CallingConv::ID CC);

llvm/include/llvm/Support/TargetOpcodes.def

 HANDLE_TARGET_OPCODE(G_UDIV)
 
 // Generic signed remainder instruction.
 HANDLE_TARGET_OPCODE(G_SREM)
 
 // Generic unsigned remainder instruction.
 HANDLE_TARGET_OPCODE(G_UREM)
 
+// Generic signed divrem instruction.
+HANDLE_TARGET_OPCODE(G_SDIVREM)
+
+// Generic unsigned divrem instruction.
+HANDLE_TARGET_OPCODE(G_UDIVREM)
+
 /// Generic bitwise and instruction.
 HANDLE_TARGET_OPCODE(G_AND)
 
 /// Generic bitwise or instruction.
 HANDLE_TARGET_OPCODE(G_OR)
 
 /// Generic bitwise exclusive-or instruction.
 HANDLE_TARGET_OPCODE(G_XOR)

llvm/include/llvm/Target/GenericOpcodes.td

 // Generic unsigned remainder.
 def G_UREM : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1, type0:$src2);
   let hasSideEffects = false;
   let isCommutable = false;
 }
 
+// Generic signed division and remainder.
+def G_SDIVREM : GenericInstruction {
+  let OutOperandList = (outs type0:$div, type0:$rem);
+  let InOperandList = (ins type0:$src1, type0:$src2);
+  let hasSideEffects = false;
+  let isCommutable = false;
+}
+
+// Generic unsigned division and remainder.
+def G_UDIVREM : GenericInstruction {
+  let OutOperandList = (outs type0:$div, type0:$rem);
+  let InOperandList = (ins type0:$src1, type0:$src2);
+  let hasSideEffects = false;
+  let isCommutable = false;
+}
+
 // Generic bitwise and.
 def G_AND : GenericInstruction {
   let OutOperandList = (outs type0:$dst);
   let InOperandList = (ins type0:$src1, type0:$src2);
   let hasSideEffects = false;
   let isCommutable = true;
 }
 

llvm/include/llvm/Target/GlobalISel/Combine.td

 
 def urem_pow2_to_mask : GICombineRule<
   (defs root:$root),
   (match (wip_match_opcode G_UREM):$root,
     [{ return Helper.matchOperandIsKnownToBeAPowerOfTwo(*${root}, 2); }]),
   (apply [{ return Helper.applySimplifyURemByPow2(*${root}); }])
 >;
 
+// Transform d = [su]div(x, y) and r = [su]rem(x, y) - > d, r = [su]divrem(x, y)
+def div_rem_to_divrem_matchdata : GIDefMatchData<"Register">;
+def div_rem_to_divrem : GICombineRule<
+  (defs root:$root, div_rem_to_divrem_matchdata:$matchinfo),
+  (match (wip_match_opcode G_SDIV, G_UDIV, G_SREM, G_UREM):$root,
+    [{ return Helper.matchCombineDivRem(*${root}, ${matchinfo}); }]),
+  (apply [{ Helper.applyCombineDivRem(*${root}, ${matchinfo}); }])
+>;
+
 // Fold (x op 0) - > 0
 def binop_right_to_zero: GICombineRule<
   (defs root:$root),
   (match (wip_match_opcode G_MUL):$root,
     [{ return Helper.matchOperandIsZero(*${root}, 2); }]),
   (apply [{ return Helper.replaceSingleDefInstWithOperand(*${root}, 2); }])
 >;
 
def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
     hoist_logic_op_with_same_opcode_hands,
     shl_ashr_to_sext_inreg, sext_inreg_of_load,
     width_reduction_combines, select_combines,
     known_bits_simplifications, ext_ext_fold,
     not_cmp_fold, opt_brcond_by_inverting_cond,
     unmerge_merge, fabs_fabs_fold, unmerge_cst, unmerge_dead_to_trunc,
     unmerge_zext_to_zext, trunc_ext_fold, trunc_shl,
     const_combines, xor_of_and_with_same_reg, ptr_add_with_zero,
-    shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine]>;
+    shift_immed_chain, shift_of_shifted_logic_chain, load_or_combine,
+    div_rem_to_divrem]>;

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

void CombinerHelper::applyCombineIndexedLoadStore(
   MIB.addUse(MatchInfo.Offset);
   MIB.addImm(MatchInfo.IsPre);
   MI.eraseFromParent();
   AddrDef.eraseFromParent();
 
   LLVM_DEBUG(dbgs() << "    Combinined to indexed operation");
 }
 
+bool CombinerHelper::matchCombineDivRem(MachineInstr &MI, Register &Reg) {
+  unsigned Opcode = MI.getOpcode();
+  bool IsDiv, IsSigned;
+
+  switch (Opcode) {
+  default:
+    llvm_unreachable("Unexpected opcode!");
+  case TargetOpcode::G_SDIV:
+  case TargetOpcode::G_UDIV: {
+    IsDiv = true;
+    IsSigned = Opcode == TargetOpcode::G_SDIV;
+    break;
+  }
+  case TargetOpcode::G_SREM:
+  case TargetOpcode::G_UREM: {
+    IsDiv = false;
+    IsSigned = Opcode == TargetOpcode::G_SREM;
+    break;
+  }
+  }
+
+  Register Src1 = MI.getOperand(1).getReg();
+  unsigned DivOpcode, RemOpcode, DivremOpcode;
+  if (IsSigned) {
+    DivOpcode = TargetOpcode::G_SDIV;
+    RemOpcode = TargetOpcode::G_SREM;
+    DivremOpcode = TargetOpcode::G_SDIVREM;
+  } else {
+    DivOpcode = TargetOpcode::G_UDIV;
+    RemOpcode = TargetOpcode::G_UREM;
+    DivremOpcode = TargetOpcode::G_UDIVREM;
+  }
+
+  if (!isLegalOrBeforeLegalizer({DivremOpcode, {MRI.getType(Src1)}}))
+    return false;
+
+  // Combine:
+  //   %div:_ = G_[SU]DIV %src1:_, %src2:_
+  //   %rem:_ = G_[SU]REM %src1:_, %src2:_
+  // into:
+  //  %div:_, %rem:_ = G_[SU]DIVREM %src1:_, %src2:_
+
+  // Combine:
+  //   %rem:_ = G_[SU]REM %src1:_, %src2:_
+  //   %div:_ = G_[SU]DIV %src1:_, %src2:_
+  // into:
+  //  %div:_, %rem:_ = G_[SU]DIVREM %src1:_, %src2:_
+
+  for (auto &UseMI : MRI.use_nodbg_instructions(Src1)) {
+    if (((IsDiv && UseMI.getOpcode() == RemOpcode) ||
+         (!IsDiv && UseMI.getOpcode() == DivOpcode)) &&
+        matchEqualDefs(MI.getOperand(2), UseMI.getOperand(2))) {
+      Reg = UseMI.getOperand(0).getReg();
+      return true;
+    }
+  }
+
+  return false;
+}
+
+void CombinerHelper::applyCombineDivRem(MachineInstr &MI, Register &Reg) {
+  unsigned Opcode = MI.getOpcode();
+  MachineInstr *OtherMI = MRI.getUniqueVRegDef(Reg);
+  assert(OtherMI && "No defining instruction for Reg.");
+
+  Register DestDivReg, DestRemReg;
+  if (Opcode == TargetOpcode::G_SDIV || Opcode == TargetOpcode::G_UDIV) {
+    DestDivReg = MI.getOperand(0).getReg();
+    DestRemReg = Reg;
+  } else {
+    DestDivReg = Reg;
+    DestRemReg = MI.getOperand(0).getReg();
+  }
+
+  bool IsSigned =
+      Opcode == TargetOpcode::G_SDIV || Opcode == TargetOpcode::G_SREM;
+  Builder.setInstrAndDebugLoc(MI);
+  Builder.buildInstr(IsSigned ? TargetOpcode::G_SDIVREM
+                              : TargetOpcode::G_UDIVREM,
+                     {DestDivReg, DestRemReg},
+                     {MI.getOperand(1).getReg(), MI.getOperand(2).getReg()});
+  MI.eraseFromParent();
+  OtherMI->eraseFromParent();
+}
+
 bool CombinerHelper::matchOptBrCondByInvertingCond(MachineInstr &MI) {
   if (MI.getOpcode() != TargetOpcode::G_BR)
     return false;
 
   // Try to match the following:
   // bb1:
   //   G_BRCOND %c1, %bb2
   //   G_BR %bb3

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

auto Shift =
         MIRBuilder.buildAShr(DstTy, OpReg, ShiftAmt);
     auto Add = MIRBuilder.buildAdd(DstTy, OpReg, Shift);
     MIRBuilder.buildXor(MI.getOperand(0).getReg(), Add, Shift);
     MI.eraseFromParent();
     return Legalized;
   }
   case G_SELECT:
     return lowerSelect(MI);
+  case G_SDIVREM:
+  case G_UDIVREM:
+    return lowerDIVREM(MI);
   }
 }
 
 Align LegalizerHelper::getStackTemporaryAlignment(LLT Ty,
                                                   Align MinAlign) const {
   // FIXME: We're missing a way to go back from LLT to llvm::Type to query the
   // datalayout for the preferred alignment. Also there should be a target hook
   // for this to allow targets to reduce the alignment and ignore the
LegalizerHelper::LegalizeResult LegalizerHelper::lowerSelect(MachineInstr &MI) {
 
   auto NotMask = MIRBuilder.buildNot(MaskTy, MaskReg);
   auto NewOp1 = MIRBuilder.buildAnd(MaskTy, Op1Reg, MaskReg);
   auto NewOp2 = MIRBuilder.buildAnd(MaskTy, Op2Reg, NotMask);
   MIRBuilder.buildOr(DstReg, NewOp1, NewOp2);
   MI.eraseFromParent();
   return Legalized;
 }
+
+LegalizerHelper::LegalizeResult LegalizerHelper::lowerDIVREM(MachineInstr &MI) {
+  // Split DIVREM into individual instructions.
+  unsigned Opcode = MI.getOpcode();
+
+  MIRBuilder.buildInstr(
+      Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SDIV
+                                        : TargetOpcode::G_UDIV,
+      {MI.getOperand(0).getReg()}, {MI.getOperand(2), MI.getOperand(3)});
+  MIRBuilder.buildInstr(
+      Opcode == TargetOpcode::G_SDIVREM ? TargetOpcode::G_SREM
+                                        : TargetOpcode::G_UREM,
+      {MI.getOperand(1).getReg()}, {MI.getOperand(2), MI.getOperand(3)});
+  MI.eraseFromParent();
+  return Legalized;
+}

llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir

 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 #
 # DEBUG-NEXT: G_UREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 #
+# DEBUG-NEXT: G_SDIVREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+#
+# DEBUG-NEXT: G_UDIVREM (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+#
 # DEBUG-NEXT: G_AND (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
 #
 # DEBUG-NEXT: G_OR (opcode {{[0-9]+}}): 1 type index, 0 imm indices
 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
 # DEBUG-NEXT: .. the first uncovered type index: 1, OK

llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-divrem.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+
+# Post-legalizer should not generate divrem instruction.
+---
+name: test_sdiv_srem
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_sdiv_srem
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %div:_(s32) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem:_(s32) = G_SREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_srem_sdiv
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_srem_sdiv
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %rem:_(s32) = G_SREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %div:_(s32) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_udiv_urem
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_udiv_urem
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %div:_(s32) = G_UDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem:_(s32) = G_UREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %div:_(s32) = G_UDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_UREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_urem_udiv
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_urem_udiv
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %rem:_(s32) = G_UREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %div:_(s32) = G_UDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %rem:_(s32) = G_UREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %div:_(s32) = G_UDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_v2
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_sdiv_srem_v2
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %y0:_(s32) = COPY $vgpr2
+    ; CHECK: %y1:_(s32) = COPY $vgpr3
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32)
+    ; CHECK: %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32)
+    ; CHECK: %div:_(<2 x s32>) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div(<2 x s32>), %ptr1(p1) :: (store 8, align 4, addrspace 1)
+    ; CHECK: %rem:_(<2 x s32>) = G_SREM %src1, %src2
+    ; CHECK: G_STORE %rem(<2 x s32>), %ptr2(p1) :: (store 8, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %y0:_(s32) = COPY $vgpr2
+    %y1:_(s32) = COPY $vgpr3
+    %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32)
+    %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32)
+    %div:_(<2 x s32>) = G_SDIV %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %div:_(<2 x s32>), %ptr1:_(p1) :: (store 8, addrspace 1, align 4)
+    %rem:_(<2 x s32>) = G_SREM %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %rem:_(<2 x s32>), %ptr2:_(p1) :: (store 8, addrspace 1, align 4)
+...
+---
+name: test_udiv_urem_v2
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_udiv_urem_v2
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %y0:_(s32) = COPY $vgpr2
+    ; CHECK: %y1:_(s32) = COPY $vgpr3
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32)
+    ; CHECK: %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32)
+    ; CHECK: %div:_(<2 x s32>) = G_UDIV %src1, %src2
+    ; CHECK: G_STORE %div(<2 x s32>), %ptr1(p1) :: (store 8, align 4, addrspace 1)
+    ; CHECK: %rem:_(<2 x s32>) = G_UREM %src1, %src2
+    ; CHECK: G_STORE %rem(<2 x s32>), %ptr2(p1) :: (store 8, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %y0:_(s32) = COPY $vgpr2
+    %y1:_(s32) = COPY $vgpr3
+    %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32)
+    %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32)
+    %div:_(<2 x s32>) = G_UDIV %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %div:_(<2 x s32>), %ptr1:_(p1) :: (store 8, addrspace 1, align 4)
+    %rem:_(<2 x s32>) = G_UREM %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %rem:_(<2 x s32>), %ptr2:_(p1) :: (store 8, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_extra_sdiv
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_sdiv_srem_extra_sdiv
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr3:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %div:_(s32) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem:_(s32) = G_SREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    ; CHECK: %div2:_(s32) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div2(s32), %ptr3(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %ptr3:_(p1) = COPY $vgpr6_vgpr7
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+    %div2:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div2:_(s32), %ptr3:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_extra_srem
+tracksRegLiveness: true
+legalized: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_sdiv_srem_extra_srem
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr3:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %div:_(s32) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem:_(s32) = G_SREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem2:_(s32) = G_SREM %src1, %src2
+    ; CHECK: G_STORE %rem2(s32), %ptr3(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %ptr3:_(p1) = COPY $vgpr6_vgpr7
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem2:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem2:_(s32), %ptr3:_(p1) :: (store 4, addrspace 1, align 4)
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
+
+---
+name: test_sdiv_srem
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_sdiv_srem
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %div:_(s32), %rem:_ = G_SDIVREM %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_v2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_sdiv_srem_v2
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %y0:_(s32) = COPY $vgpr2
+    ; CHECK: %y1:_(s32) = COPY $vgpr3
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32)
+    ; CHECK: %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32)
+    ; CHECK: %div:_(<2 x s32>), %rem:_ = G_SDIVREM %src1, %src2
+    ; CHECK: G_STORE %div(<2 x s32>), %ptr1(p1) :: (store 8, align 4, addrspace 1)
+    ; CHECK: G_STORE %rem(<2 x s32>), %ptr2(p1) :: (store 8, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %y0:_(s32) = COPY $vgpr2
+    %y1:_(s32) = COPY $vgpr3
+    %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32)
+    %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32)
+    %div:_(<2 x s32>) = G_SDIV %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %div:_(<2 x s32>), %ptr1:_(p1) :: (store 8, addrspace 1, align 4)
+    %rem:_(<2 x s32>) = G_SREM %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %rem:_(<2 x s32>), %ptr2:_(p1) :: (store 8, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_v4
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11
+    ; CHECK-LABEL: name: test_sdiv_srem_v4
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %x2:_(s32) = COPY $vgpr2
+    ; CHECK: %x3:_(s32) = COPY $vgpr3
+    ; CHECK: %y0:_(s32) = COPY $vgpr4
+    ; CHECK: %y1:_(s32) = COPY $vgpr5
+    ; CHECK: %y2:_(s32) = COPY $vgpr6
+    ; CHECK: %y3:_(s32) = COPY $vgpr7
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr8_vgpr9
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr10_vgpr11
+    ; CHECK: %src1:_(<4 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32), %x2(s32), %x3(s32)
+    ; CHECK: %src2:_(<4 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32), %y2(s32), %y3(s32)
+    ; CHECK: %div:_(<4 x s32>), %rem:_ = G_SDIVREM %src1, %src2
+    ; CHECK: G_STORE %div(<4 x s32>), %ptr1(p1) :: (store 16, align 4, addrspace 1)
+    ; CHECK: G_STORE %rem(<4 x s32>), %ptr2(p1) :: (store 16, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %x2:_(s32) = COPY $vgpr2
+    %x3:_(s32) = COPY $vgpr3
+    %y0:_(s32) = COPY $vgpr4
+    %y1:_(s32) = COPY $vgpr5
+    %y2:_(s32) = COPY $vgpr6
+    %y3:_(s32) = COPY $vgpr7
+    %ptr1:_(p1) = COPY $vgpr8_vgpr9
+    %ptr2:_(p1) = COPY $vgpr10_vgpr11
+    %src1:_(<4 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32), %x2:_(s32), %x3:_(s32)
+    %src2:_(<4 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32), %y2:_(s32), %y3:_(s32)
+    %div:_(<4 x s32>) = G_SDIV %src1:_(<4 x s32>), %src2:_(<4 x s32>)
+    G_STORE %div:_(<4 x s32>), %ptr1:_(p1) :: (store 16, addrspace 1, align 4)
+    %rem:_(<4 x s32>) = G_SREM %src1:_(<4 x s32>), %src2:_(<4 x s32>)
+    G_STORE %rem:_(<4 x s32>), %ptr2:_(p1) :: (store 16, addrspace 1, align 4)
+...
+---
+name: test_srem_sdiv
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_srem_sdiv
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %div:_(s32), %rem:_ = G_SDIVREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: G_STORE %div(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_srem_sdiv_v2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_srem_sdiv_v2
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %y0:_(s32) = COPY $vgpr2
+    ; CHECK: %y1:_(s32) = COPY $vgpr3
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32)
+    ; CHECK: %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32)
+    ; CHECK: %div:_(<2 x s32>), %rem:_ = G_SDIVREM %src1, %src2
+    ; CHECK: G_STORE %rem(<2 x s32>), %ptr1(p1) :: (store 8, align 4, addrspace 1)
+    ; CHECK: G_STORE %div(<2 x s32>), %ptr2(p1) :: (store 8, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %y0:_(s32) = COPY $vgpr2
+    %y1:_(s32) = COPY $vgpr3
+    %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32)
+    %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32)
+    %rem:_(<2 x s32>) = G_SREM %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %rem:_(<2 x s32>), %ptr1:_(p1) :: (store 8, addrspace 1, align 4)
+    %div:_(<2 x s32>) = G_SDIV %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %div:_(<2 x s32>), %ptr2:_(p1) :: (store 8, addrspace 1, align 4)
+...
+---
+name: test_srem_sdiv_v4
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11
+    ; CHECK-LABEL: name: test_srem_sdiv_v4
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %x2:_(s32) = COPY $vgpr2
+    ; CHECK: %x3:_(s32) = COPY $vgpr3
+    ; CHECK: %y0:_(s32) = COPY $vgpr4
+    ; CHECK: %y1:_(s32) = COPY $vgpr5
+    ; CHECK: %y2:_(s32) = COPY $vgpr6
+    ; CHECK: %y3:_(s32) = COPY $vgpr7
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr8_vgpr9
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr10_vgpr11
+    ; CHECK: %src1:_(<4 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32), %x2(s32), %x3(s32)
+    ; CHECK: %src2:_(<4 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32), %y2(s32), %y3(s32)
+    ; CHECK: %div:_(<4 x s32>), %rem:_ = G_SDIVREM %src1, %src2
+    ; CHECK: G_STORE %rem(<4 x s32>), %ptr1(p1) :: (store 16, align 4, addrspace 1)
+    ; CHECK: G_STORE %div(<4 x s32>), %ptr2(p1) :: (store 16, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %x2:_(s32) = COPY $vgpr2
+    %x3:_(s32) = COPY $vgpr3
+    %y0:_(s32) = COPY $vgpr4
+    %y1:_(s32) = COPY $vgpr5
+    %y2:_(s32) = COPY $vgpr6
+    %y3:_(s32) = COPY $vgpr7
+    %ptr1:_(p1) = COPY $vgpr8_vgpr9
+    %ptr2:_(p1) = COPY $vgpr10_vgpr11
+    %src1:_(<4 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32), %x2:_(s32), %x3:_(s32)
+    %src2:_(<4 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32), %y2:_(s32), %y3:_(s32)
+    %rem:_(<4 x s32>) = G_SREM %src1:_(<4 x s32>), %src2:_(<4 x s32>)
+    G_STORE %rem:_(<4 x s32>), %ptr1:_(p1) :: (store 16, addrspace 1, align 4)
+    %div:_(<4 x s32>) = G_SDIV %src1:_(<4 x s32>), %src2:_(<4 x s32>)
+    G_STORE %div:_(<4 x s32>), %ptr2:_(p1) :: (store 16, addrspace 1, align 4)
+...
+---
+name: test_udiv_urem
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_udiv_urem
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %div:_(s32), %rem:_ = G_UDIVREM %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %div:_(s32) = G_UDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_UREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_udiv_urem_v2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_udiv_urem_v2
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %y0:_(s32) = COPY $vgpr2
+    ; CHECK: %y1:_(s32) = COPY $vgpr3
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32)
+    ; CHECK: %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32)
+    ; CHECK: %div:_(<2 x s32>), %rem:_ = G_UDIVREM %src1, %src2
+    ; CHECK: G_STORE %div(<2 x s32>), %ptr1(p1) :: (store 8, align 4, addrspace 1)
+    ; CHECK: G_STORE %rem(<2 x s32>), %ptr2(p1) :: (store 8, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %y0:_(s32) = COPY $vgpr2
+    %y1:_(s32) = COPY $vgpr3
+    %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32)
+    %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32)
+    %div:_(<2 x s32>) = G_UDIV %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %div:_(<2 x s32>), %ptr1:_(p1) :: (store 8, addrspace 1, align 4)
+    %rem:_(<2 x s32>) = G_UREM %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %rem:_(<2 x s32>), %ptr2:_(p1) :: (store 8, addrspace 1, align 4)
+...
+---
+name: test_udiv_urem_v4
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11
+    ; CHECK-LABEL: name: test_udiv_urem_v4
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %x2:_(s32) = COPY $vgpr2
+    ; CHECK: %x3:_(s32) = COPY $vgpr3
+    ; CHECK: %y0:_(s32) = COPY $vgpr4
+    ; CHECK: %y1:_(s32) = COPY $vgpr5
+    ; CHECK: %y2:_(s32) = COPY $vgpr6
+    ; CHECK: %y3:_(s32) = COPY $vgpr7
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr8_vgpr9
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr10_vgpr11
+    ; CHECK: %src1:_(<4 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32), %x2(s32), %x3(s32)
+    ; CHECK: %src2:_(<4 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32), %y2(s32), %y3(s32)
+    ; CHECK: %div:_(<4 x s32>), %rem:_ = G_UDIVREM %src1, %src2
+    ; CHECK: G_STORE %div(<4 x s32>), %ptr1(p1) :: (store 16, align 4, addrspace 1)
+    ; CHECK: G_STORE %rem(<4 x s32>), %ptr2(p1) :: (store 16, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %x2:_(s32) = COPY $vgpr2
+    %x3:_(s32) = COPY $vgpr3
+    %y0:_(s32) = COPY $vgpr4
+    %y1:_(s32) = COPY $vgpr5
+    %y2:_(s32) = COPY $vgpr6
+    %y3:_(s32) = COPY $vgpr7
+    %ptr1:_(p1) = COPY $vgpr8_vgpr9
+    %ptr2:_(p1) = COPY $vgpr10_vgpr11
+    %src1:_(<4 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32), %x2:_(s32), %x3:_(s32)
+    %src2:_(<4 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32), %y2:_(s32), %y3:_(s32)
+    %div:_(<4 x s32>) = G_UDIV %src1:_(<4 x s32>), %src2:_(<4 x s32>)
+    G_STORE %div:_(<4 x s32>), %ptr1:_(p1) :: (store 16, addrspace 1, align 4)
+    %rem:_(<4 x s32>) = G_UREM %src1:_(<4 x s32>), %src2:_(<4 x s32>)
+    G_STORE %rem:_(<4 x s32>), %ptr2:_(p1) :: (store 16, addrspace 1, align 4)
+...
+---
+name: test_urem_udiv
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_urem_udiv
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %div:_(s32), %rem:_ = G_UDIVREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: G_STORE %div(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %rem:_(s32) = G_UREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %div:_(s32) = G_UDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_urem_udiv_v2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK-LABEL: name: test_urem_udiv_v2
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %y0:_(s32) = COPY $vgpr2
+    ; CHECK: %y1:_(s32) = COPY $vgpr3
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32)
+    ; CHECK: %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32)
+    ; CHECK: %div:_(<2 x s32>), %rem:_ = G_UDIVREM %src1, %src2
+    ; CHECK: G_STORE %rem(<2 x s32>), %ptr1(p1) :: (store 8, align 4, addrspace 1)
+    ; CHECK: G_STORE %div(<2 x s32>), %ptr2(p1) :: (store 8, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %y0:_(s32) = COPY $vgpr2
+    %y1:_(s32) = COPY $vgpr3
+    %ptr1:_(p1) = COPY $vgpr4_vgpr5
+    %ptr2:_(p1) = COPY $vgpr6_vgpr7
+    %src1:_(<2 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32)
+    %src2:_(<2 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32)
+    %rem:_(<2 x s32>) = G_UREM %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %rem:_(<2 x s32>), %ptr1:_(p1) :: (store 8, addrspace 1, align 4)
+    %div:_(<2 x s32>) = G_UDIV %src1:_(<2 x s32>), %src2:_(<2 x s32>)
+    G_STORE %div:_(<2 x s32>), %ptr2:_(p1) :: (store 8, addrspace 1, align 4)
+...
+---
+name: test_urem_udiv_v4
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11
+    ; CHECK-LABEL: name: test_urem_udiv_v4
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8_vgpr9, $vgpr10_vgpr11
+    ; CHECK: %x0:_(s32) = COPY $vgpr0
+    ; CHECK: %x1:_(s32) = COPY $vgpr1
+    ; CHECK: %x2:_(s32) = COPY $vgpr2
+    ; CHECK: %x3:_(s32) = COPY $vgpr3
+    ; CHECK: %y0:_(s32) = COPY $vgpr4
+    ; CHECK: %y1:_(s32) = COPY $vgpr5
+    ; CHECK: %y2:_(s32) = COPY $vgpr6
+    ; CHECK: %y3:_(s32) = COPY $vgpr7
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr8_vgpr9
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr10_vgpr11
+    ; CHECK: %src1:_(<4 x s32>) = G_BUILD_VECTOR %x0(s32), %x1(s32), %x2(s32), %x3(s32)
+    ; CHECK: %src2:_(<4 x s32>) = G_BUILD_VECTOR %y0(s32), %y1(s32), %y2(s32), %y3(s32)
+    ; CHECK: %div:_(<4 x s32>), %rem:_ = G_UDIVREM %src1, %src2
+    ; CHECK: G_STORE %rem(<4 x s32>), %ptr1(p1) :: (store 16, align 4, addrspace 1)
+    ; CHECK: G_STORE %div(<4 x s32>), %ptr2(p1) :: (store 16, align 4, addrspace 1)
+    %x0:_(s32) = COPY $vgpr0
+    %x1:_(s32) = COPY $vgpr1
+    %x2:_(s32) = COPY $vgpr2
+    %x3:_(s32) = COPY $vgpr3
+    %y0:_(s32) = COPY $vgpr4
+    %y1:_(s32) = COPY $vgpr5
+    %y2:_(s32) = COPY $vgpr6
+    %y3:_(s32) = COPY $vgpr7
+    %ptr1:_(p1) = COPY $vgpr8_vgpr9
+    %ptr2:_(p1) = COPY $vgpr10_vgpr11
+    %src1:_(<4 x s32>) = G_BUILD_VECTOR %x0:_(s32), %x1:_(s32), %x2:_(s32), %x3:_(s32)
+    %src2:_(<4 x s32>) = G_BUILD_VECTOR %y0:_(s32), %y1:_(s32), %y2:_(s32), %y3:_(s32)
+    %rem:_(<4 x s32>) = G_UREM %src1:_(<4 x s32>), %src2:_(<4 x s32>)
+    G_STORE %rem:_(<4 x s32>), %ptr1:_(p1) :: (store 16, addrspace 1, align 4)
+    %div:_(<4 x s32>) = G_UDIV %src1:_(<4 x s32>), %src2:_(<4 x s32>)
+    G_STORE %div:_(<4 x s32>), %ptr2:_(p1) :: (store 16, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_extra_use
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_sdiv_srem_extra_use
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = G_IMPLICIT_DEF
+    ; CHECK: %ptr2:_(p1) = G_IMPLICIT_DEF
+    ; CHECK: %ptr3:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr4:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: G_STORE %src1(s32), %ptr1(p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+    ; CHECK: G_STORE %src2(s32), %ptr2(p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+    ; CHECK: %div:_(s32), %rem:_ = G_SDIVREM %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr3(p1) :: (store 4, addrspace 1)
+    ; CHECK: G_STORE %rem(s32), %ptr4(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = G_IMPLICIT_DEF
+    %ptr2:_(p1) = G_IMPLICIT_DEF
+    %ptr3:_(p1) = COPY $vgpr2_vgpr3
+    %ptr4:_(p1) = COPY $vgpr4_vgpr5
+    G_STORE %src1:_(s32), %ptr1:_(p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+    G_STORE %src2:_(s32), %ptr2:_(p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr3:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr4:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_different_blocks
+tracksRegLiveness: true
+body: |
+  ; CHECK-LABEL: name: test_sdiv_srem_different_blocks
+  ; CHECK: bb.0:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+  ; CHECK:   %src1:_(s32) = COPY $vgpr0
+  ; CHECK:   %src2:_(s32) = COPY $vgpr1
+  ; CHECK:   %ptr1:_(p1) = COPY $vgpr2_vgpr3
+  ; CHECK:   %div:_(s32), %rem:_ = G_SDIVREM %src1, %src2
+  ; CHECK:   G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+  ; CHECK:   S_BRANCH %bb.1
+  ; CHECK: bb.1:
+  ; CHECK:   liveins: $vgpr4_vgpr5
+  ; CHECK:   %ptr2:_(p1) = COPY $vgpr4_vgpr5
+  ; CHECK:   G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    S_BRANCH %bb.1
+  bb.1:
+    liveins: $vgpr4_vgpr5
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_extra_sdiv
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; Combine the first sdiv/srem pair into sdivrem and retain the extra
+    ; sdiv instruction.
+    ; CHECK-LABEL: name: test_sdiv_srem_extra_sdiv
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr3:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %div:_(s32), %rem:_ = G_SDIVREM %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    ; CHECK: %div2:_(s32) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div2(s32), %ptr3(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %ptr3:_(p1) = COPY $vgpr6_vgpr7
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+    %div2:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div2:_(s32), %ptr3:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_extra_srem
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; Combine the first sdiv/srem pair into sdivrem and retain the extra
+    ; srem instruction.
+    ; CHECK-LABEL: name: test_sdiv_srem_extra_srem
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5, $vgpr6_vgpr7
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %ptr3:_(p1) = COPY $vgpr6_vgpr7
+    ; CHECK: %div:_(s32), %rem:_ = G_SDIVREM %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem2:_(s32) = G_SREM %src1, %src2
+    ; CHECK: G_STORE %rem2(s32), %ptr3(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %ptr3:_(p1) = COPY $vgpr6_vgpr7
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem2:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem2:_(s32), %ptr3:_(p1) :: (store 4, addrspace 1, align 4)
+...
+# Some negative tests.
+---
+name: test_sdiv_srem_different_src_opnd2
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3_vgpr4, $vgpr5_vgpr6
+    ; CHECK-LABEL: name: test_sdiv_srem_different_src_opnd2
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3_vgpr4, $vgpr5_vgpr6
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %src3:_(s32) = COPY $vgpr2
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr3_vgpr4
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr5_vgpr6
+    ; CHECK: %div:_(s32) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem:_(s32) = G_SREM %src1, %src3
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %src3:_(s32) = COPY $vgpr2
+    %ptr1:_(p1) = COPY $vgpr3_vgpr4
+    %ptr2:_(p1) = COPY $vgpr5_vgpr6
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src1:_(s32), %src3:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_sdiv_srem_src_opnds_swapped
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_sdiv_srem_src_opnds_swapped
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %div:_(s32) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem:_(s32) = G_SREM %src2, %src1
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src2:_(s32), %src1:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_sdiv_urem
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_sdiv_urem
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %div:_(s32) = G_SDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem:_(s32) = G_UREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %div:_(s32) = G_SDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_UREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...
+---
+name: test_udiv_srem
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK-LABEL: name: test_udiv_srem
+    ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2_vgpr3, $vgpr4_vgpr5
+    ; CHECK: %src1:_(s32) = COPY $vgpr0
+    ; CHECK: %src2:_(s32) = COPY $vgpr1
+    ; CHECK: %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    ; CHECK: %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    ; CHECK: %div:_(s32) = G_UDIV %src1, %src2
+    ; CHECK: G_STORE %div(s32), %ptr1(p1) :: (store 4, addrspace 1)
+    ; CHECK: %rem:_(s32) = G_SREM %src1, %src2
+    ; CHECK: G_STORE %rem(s32), %ptr2(p1) :: (store 4, addrspace 1)
+    %src1:_(s32) = COPY $vgpr0
+    %src2:_(s32) = COPY $vgpr1
+    %ptr1:_(p1) = COPY $vgpr2_vgpr3
+    %ptr2:_(p1) = COPY $vgpr4_vgpr5
+    %div:_(s32) = G_UDIV %src1:_(s32), %src2:_(s32)
+    G_STORE %div:_(s32), %ptr1:_(p1) :: (store 4, addrspace 1, align 4)
+    %rem:_(s32) = G_SREM %src1:_(s32), %src2:_(s32)
+    G_STORE %rem:_(s32), %ptr2:_(p1) :: (store 4, addrspace 1, align 4)
+...

llvm/unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp

TEST_F(AArch64GISelMITest, LowerBSWAP) {
   CHECK: [[AND1:%[0-9]+]]:_(<2 x s32>) = G_AND [[SHR1]]:_, [[SPLATMASK]]:_
   CHECK: [[BSWAP:%[0-9]+]]:_(<2 x s32>) = G_OR [[OR1]]:_, [[AND1]]:_
   )";
 
   // Check
   EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
 }
 
+// Test lowering of G_SDIVREM into G_SDIV and G_SREM
+TEST_F(AArch64GISelMITest, LowerSDIVREM) {
+  setUp();
+  if (!TM)
+    return;
+
+  // Declare your legalization info
+  DefineLegalizerInfo(
+      A, { getActionDefinitionsBuilder(G_SDIVREM).lowerFor({s64}); });
+
+  LLT S64{LLT::scalar(64)};
+
+  // Build Instr
+  auto SDivrem =
+      B.buildInstr(TargetOpcode::G_SDIVREM, {S64, S64}, {Copies[0], Copies[1]});
+  AInfo Info(MF->getSubtarget());
+  DummyGISelObserver Observer;
+  LegalizerHelper Helper(*MF, Info, Observer, B);
+  // Perform Legalization
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.lower(*SDivrem, 0, S64));
+
+  auto *CheckStr = R"(
+  CHECK: [[DIV:%[0-9]+]]:_(s64) = G_SDIV %0:_, %1:_
+  CHECK: [[REM:%[0-9]+]]:_(s64) = G_SREM %0:_, %1:_
+  )";
+
+  // Check
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
+// Test lowering of G_UDIVREM into G_UDIV and G_UREM
+TEST_F(AArch64GISelMITest, LowerUDIVREM) {
+  setUp();
+  if (!TM)
+    return;
+
+  // Declare your legalization info
+  DefineLegalizerInfo(
+      A, { getActionDefinitionsBuilder(G_UDIVREM).lowerFor({s64}); });
+
+  LLT S64{LLT::scalar(64)};
+
+  // Build Instr
+  auto UDivrem =
+      B.buildInstr(TargetOpcode::G_UDIVREM, {S64, S64}, {Copies[0], Copies[1]});
+  AInfo Info(MF->getSubtarget());
+  DummyGISelObserver Observer;
+  LegalizerHelper Helper(*MF, Info, Observer, B);
+  // Perform Legalization
+  EXPECT_EQ(LegalizerHelper::LegalizeResult::Legalized,
+            Helper.lower(*UDivrem, 0, S64));
+
+  auto *CheckStr = R"(
+  CHECK: [[DIV:%[0-9]+]]:_(s64) = G_UDIV %0:_, %1:_
+  CHECK: [[REM:%[0-9]+]]:_(s64) = G_UREM %0:_, %1:_
+  )";
+
+  // Check
+  EXPECT_TRUE(CheckMachineFunction(*MF, CheckStr)) << *MF;
+}
+
 // Test widening of G_UNMERGE_VALUES
 TEST_F(AArch64GISelMITest, WidenUnmerge) {
   setUp();
   if (!TM)
     return;
 
   DefineLegalizerInfo(A, {});