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[AArch64] Add vector saturating add intrinsic costs
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Authored by dmgreen on Jan 23 2021, 12:25 PM.

Details

Summary

This adds sadd.sat, uadd.sat, ssub.sat and usub.sat costs for AArch64, similar to how they were recently added for ARM.

Diff Detail

Event Timeline

dmgreen created this revision.Jan 23 2021, 12:25 PM
dmgreen requested review of this revision.Jan 23 2021, 12:25 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 23 2021, 12:25 PM
RKSimon accepted this revision.Jan 24 2021, 3:27 AM

LGTM

llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll
33–34

I know you're just handling legal costs in this patch but these appear to be very high!

This revision is now accepted and ready to land.Jan 24 2021, 3:27 AM
dmgreen updated this revision to Diff 318837.Jan 24 2021, 5:21 AM
dmgreen added inline comments.
llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll
33–34

Whoops! Thanks for noticing. These should be legal, I apparently wasn't paying enough attention to how the tests changed.

fhahn added inline comments.Jan 24 2021, 1:13 PM
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
249

are there test cases for that?

llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll
79

perhaps throw in an odd number of vector elements as well?

dmgreen added inline comments.Jan 27 2021, 2:33 AM
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
249

For the Instrs == 4 case? Yeah, those are cases like:
; RECIP-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2I16 = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> undef, <2 x i16> undef)

llvm/test/Analysis/CostModel/AArch64/arith-ssat.ll
79

Will do.

This revision was automatically updated to reflect the committed changes.