[RISCV] Add isel patterns to optimize slli.uw patterns without Zba extension.

[craig.topper]

Summary

This pattern can occur when an unsigned is used to index an array
on RV64.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

336

This is just NegImm and ImmSub32 composed?

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

336

(also a shorter name that doesn't require spelling 32 in words would be ImmSubFrom32)

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

336

SDNodeXForms can't be composed can they?

[craig.topper]

Rename to ImmSubFrom32
Remove ImmROTL2RW which was identical to ImmSubFrom32 in another file
Rename ImmROTL2R to ImmSubFromXLen for consistency

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfo.td

336

Hmm, you can in the patterns but seems there's no way to declare an alias for that.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

48–49

Probably worth just moving this now; no doubt something will come along later that needs it.

[craig.topper]

Move ImmSubFromXLen to RISCVInstrInfo.td

[luismarques]

LGTM. Nice!

llvm/lib/Target/RISCV/RISCVInstrInfo.td

 }]>;
 
 // Return an immediate value minus 32.
 def ImmSub32 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(N->getSExtValue() - 32, SDLoc(N),
                                    N->getValueType(0));
 }]>;
 
+// Return an immediate subtracted from XLen.
+def ImmSubFromXLen : SDNodeXForm<imm, [{
+  uint64_t XLen = Subtarget->getXLen();
+  return CurDAG->getTargetConstant(XLen - N->getZExtValue(), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
+// Return an immediate subtracted from 32.
+def ImmSubFrom32 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
+                                   N->getValueType(0));
+}]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Formats
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrFormats.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Class Templates
def zexti32 : PatFrags<(ops node:$src),
                        [(and node:$src, 0xffffffff),
                         (assertzexti32 node:$src)]>;
 
 def SRLIWPat : PatFrag<(ops node:$A, node:$B),
                        (srl (and node:$A, imm), node:$B), [{
   return MatchSRLIW(N);
 }]>;
 
+// Check that it is a SLLIUW (Shift Logical Left Immediate Unsigned i32
+// on RV64). Also used to optimize the same sequence without SLLIUW.
+def SLLIUWPat : PatFrag<(ops node:$A, node:$B),
+                        (and (shl node:$A, node:$B), imm), [{
+  return MatchSLLIUW(N);
+}]>;
+
 /// Immediates
 
 def : Pat<(simm12:$imm), (ADDI X0, simm12:$imm)>;
 def : Pat<(simm32hi20:$imm), (LUI (HI20 imm:$imm))>;
 def : Pat<(simm32:$imm), (ADDI (LUI (HI20 imm:$imm)), (LO12Sext imm:$imm))>,
       Requires<[IsRV32]>;
 
 /// Simple arithmetic operations

 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(callseq_start timm:$amt1, timm:$amt2)]>;
 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
                               [(callseq_end timm:$amt1, timm:$amt2)]>;
 } // Defs = [X2], Uses = [X2]
 
 /// RV64 patterns
 
-let Predicates = [IsRV64, NotHasStdExtZba] in
+let Predicates = [IsRV64, NotHasStdExtZba] in {
 def : Pat<(and GPR:$rs1, 0xffffffff), (SRLI (SLLI GPR:$rs1, 32), 32)>;
 
+// If we're shifting a 32-bit zero extended value left by 0-31 bits, use 2
+// shifts instead of 3. This can occur when unsigned is used to index an array.
+def : Pat<(shl (and GPR:$rs1, 0xffffffff), uimm5:$shamt),
+          (SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
+// shl/and can appear in the other order too.
+def : Pat<(SLLIUWPat GPR:$rs1, uimm5:$shamt),
+          (SRLI (SLLI GPR:$rs1, 32), (ImmSubFrom32 uimm5:$shamt))>;
+}
+
 let Predicates = [IsRV64] in {
 
 /// sext and zext
 
 def : Pat<(sext_inreg GPR:$rs1, i32), (ADDIW GPR:$rs1, 0)>;
 
 /// ALU operations
 

llvm/lib/Target/RISCV/RISCVInstrInfoB.td

let MCOperandPredicate = [{
     if (!MCOp.evaluateAsConstantImm(Imm))
       return false;
     if (STI.getTargetTriple().isArch64Bit())
       return  isUInt<5>(Imm);
     return isUInt<4>(Imm);
   }];
 }
 
 
-// Convert rotl immediate to a rotr immediate for XLen instructions.
-def ImmROTL2R : SDNodeXForm<imm, [{
-  uint64_t XLen = Subtarget->getXLen();
-  return CurDAG->getTargetConstant(XLen - N->getZExtValue(), SDLoc(N),
-                                   N->getValueType(0));
-}]>;
-
-// Convert rotl immediate to a rotr immediate for W instructions.
-def ImmROTL2RW : SDNodeXForm<imm, [{
-  return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N),
-                                   N->getValueType(0));
-}]>;
-
 // Check that it is a SLOI (Shift Left Ones Immediate).
 def SLOIPat : PatFrag<(ops node:$A, node:$B),
                       (or (shl node:$A, node:$B), imm), [{
   return MatchSLOI(N);
 }]>;
 
 // Check that it is a SROI (Shift Right Ones Immediate).
 def SROIPat : PatFrag<(ops node:$A, node:$B),
                       (or (srl node:$A, node:$B), imm), [{
   return MatchSROI(N);
 }]>;
 
 // Check that it is a SROIW (Shift Right Ones Immediate i32 on RV64).
 def SROIWPat : PatFrag<(ops node:$A, node:$B),
                        (or (srl node:$A, node:$B), imm), [{
   return MatchSROIW(N);
 }]>;
 
-// Check that it is a SLLIUW (Shift Logical Left Immediate Unsigned i32
-// on RV64).
-def SLLIUWPat : PatFrag<(ops node:$A, node:$B),
-                        (and (shl node:$A, node:$B), imm), [{
-  return MatchSLLIUW(N);
-}]>;
-
 // Checks if this mask has a single 0 bit and cannot be used with ANDI.
 def BCLRMask : ImmLeaf<XLenVT, [{
   if (Subtarget->is64Bit())
     return !isInt<12>(Imm) && isPowerOf2_64(~Imm);
   return !isInt<12>(Imm) && isPowerOf2_32(~Imm);
 }]>;
 
 // Checks if this mask has a single 1 bit and cannot be used with ORI/XORI.

 } // Predicates = [HasStdExtZbp]
 
 // There's no encoding for roli in the the 'B' extension as it can be
 // implemented with rori by negating the immediate.
 let Predicates = [HasStdExtZbbOrZbp] in {
 def : Pat<(rotr GPR:$rs1, uimmlog2xlen:$shamt),
           (RORI GPR:$rs1, uimmlog2xlen:$shamt)>;
 def : Pat<(rotl GPR:$rs1, uimmlog2xlen:$shamt),
-          (RORI GPR:$rs1, (ImmROTL2R uimmlog2xlen:$shamt))>;
+          (RORI GPR:$rs1, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
 }
 
 // We don't pattern-match sbclri[w], sbseti[w], sbinvi[w] because they are
 // pattern-matched by simple andi, ori, and xori.
 let Predicates = [HasStdExtZbs] in
 def : Pat<(and (srl GPR:$rs1, uimmlog2xlen:$shamt), (XLenVT 1)),
           (BEXTI GPR:$rs1, uimmlog2xlen:$shamt)>;
 
def : Pat<(fshr GPR:$rs3, GPR:$rs1, GPR:$rs2),
           (FSR GPR:$rs1, (ANDI GPR:$rs2, 63), GPR:$rs3)>;
 }
 let Predicates = [HasStdExtZbt] in {
 def : Pat<(fshr GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
           (FSRI GPR:$rs1, GPR:$rs3, uimmlog2xlen:$shamt)>;
 // We can use FSRI for fshl by immediate if we subtract the immediate from
 // XLen and swap the operands.
 def : Pat<(fshl GPR:$rs3, GPR:$rs1, uimmlog2xlen:$shamt),
-          (FSRI GPR:$rs1, GPR:$rs3, (ImmROTL2R uimmlog2xlen:$shamt))>;
+          (FSRI GPR:$rs1, GPR:$rs3, (ImmSubFromXLen uimmlog2xlen:$shamt))>;
 } // Predicates = [HasStdExtZbt]
 
 let Predicates = [HasStdExtZbb] in {
 def : Pat<(ctlz GPR:$rs1), (CLZ GPR:$rs1)>;
 def : Pat<(cttz GPR:$rs1), (CTZ GPR:$rs1)>;
 def : Pat<(ctpop GPR:$rs1), (CPOP GPR:$rs1)>;
 } // Predicates = [HasStdExtZbb]
 

 let Predicates = [HasStdExtZbbOrZbp, IsRV64] in {
 def : Pat<(riscv_rolw GPR:$rs1, GPR:$rs2),
           (ROLW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(riscv_rorw GPR:$rs1, GPR:$rs2),
           (RORW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(riscv_rorw GPR:$rs1, uimm5:$rs2),
           (RORIW GPR:$rs1, uimm5:$rs2)>;
 def : Pat<(riscv_rolw GPR:$rs1, uimm5:$rs2),
-          (RORIW GPR:$rs1, (ImmROTL2RW uimm5:$rs2))>;
+          (RORIW GPR:$rs1, (ImmSubFrom32 uimm5:$rs2))>;
 } // Predicates = [HasStdExtZbbOrZbp, IsRV64]
 
 let Predicates = [HasStdExtZbs, IsRV64] in {
 def : Pat<(and (not (riscv_sllw 1, GPR:$rs2)), (assertsexti32 GPR:$rs1)),
           (BCLRW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(sext_inreg (and (not (riscv_sllw 1, GPR:$rs2)), GPR:$rs1), i32),
           (BCLRW GPR:$rs1, GPR:$rs2)>;
 def : Pat<(or (riscv_sllw 1, GPR:$rs2), (assertsexti32 GPR:$rs1)),

 let Predicates = [HasStdExtZbt, IsRV64] in {
 def : Pat<(riscv_fslw GPR:$rs1, GPR:$rs3, GPR:$rs2),
           (FSLW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, GPR:$rs2),
           (FSRW GPR:$rs1, GPR:$rs2, GPR:$rs3)>;
 def : Pat<(riscv_fsrw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
           (FSRIW GPR:$rs1, GPR:$rs3, uimm5:$shamt)>;
 def : Pat<(riscv_fslw GPR:$rs3, GPR:$rs1, uimm5:$shamt),
-          (FSRIW GPR:$rs1, GPR:$rs3, (ImmROTL2RW uimm5:$shamt))>;
+          (FSRIW GPR:$rs1, GPR:$rs3, (ImmSubFrom32 uimm5:$shamt))>;
 } // Predicates = [HasStdExtZbt, IsRV64]
 
 let Predicates = [HasStdExtZbb, IsRV64] in {
 def : Pat<(add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),
           (CLZW GPR:$rs1)>;
 // computeKnownBits can't figure out that the and mask on the add result is
 // unnecessary so we need to pattern match it away.
 def : Pat<(and (add (ctlz (and GPR:$rs1, (i64 0xFFFFFFFF))), (i64 -32)),

llvm/test/CodeGen/RISCV/rv64Zba.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64I
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-b -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64IB
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zba -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV64IBA
 
 define i64 @slliuw(i64 %a) nounwind {
 ; RV64I-LABEL: slliuw:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 1
-; RV64I-NEXT:    addi a1, zero, 1
-; RV64I-NEXT:    slli a1, a1, 33
-; RV64I-NEXT:    addi a1, a1, -2
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 31
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: slliuw:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    slli.uw a0, a0, 1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: slliuw:
 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    slli.uw a0, a0, 1
 ; RV64IBA-NEXT:    ret
   %conv1 = shl i64 %a, 1
   %shl = and i64 %conv1, 8589934590
   ret i64 %shl
 }
 
 define i128 @slliuw_2(i32 signext %0, i128* %1) {
 ; RV64I-LABEL: slliuw_2:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    slli a0, a0, 4
+; RV64I-NEXT:    srli a0, a0, 28
 ; RV64I-NEXT:    add a1, a1, a0
 ; RV64I-NEXT:    ld a0, 0(a1)
 ; RV64I-NEXT:    ld a1, 8(a1)
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: slliuw_2:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    slli.uw a0, a0, 4
; RV64IBA-NEXT:    ret
   %4 = load i64, i64* %3
   ret i64 %4
 }
 
 define signext i16 @sh1adduw(i32 signext %0, i16* %1) {
 ; RV64I-LABEL: sh1adduw:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    slli a0, a0, 1
+; RV64I-NEXT:    srli a0, a0, 31
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    lh a0, 0(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sh1adduw:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    sh1add.uw a0, a0, a1
 ; RV64IB-NEXT:    lh a0, 0(a0)
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: sh1adduw:
 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    sh1add.uw a0, a0, a1
 ; RV64IBA-NEXT:    lh a0, 0(a0)
 ; RV64IBA-NEXT:    ret
   %3 = zext i32 %0 to i64
   %4 = getelementptr inbounds i16, i16* %1, i64 %3
   %5 = load i16, i16* %4
   ret i16 %5
 }
 
 define i64 @sh1adduw_2(i64 %0, i64 %1) {
 ; RV64I-LABEL: sh1adduw_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 1
-; RV64I-NEXT:    addi a2, zero, 1
-; RV64I-NEXT:    slli a2, a2, 33
-; RV64I-NEXT:    addi a2, a2, -2
-; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 31
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sh1adduw_2:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    sh1add.uw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: sh1adduw_2:
 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    sh1add.uw a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %3 = shl i64 %0, 1
   %4 = and i64 %3, 8589934590
   %5 = add i64 %4, %1
   ret i64 %5
 }
 
 define signext i32 @sh2adduw(i32 signext %0, i32* %1) {
 ; RV64I-LABEL: sh2adduw:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    slli a0, a0, 2
+; RV64I-NEXT:    srli a0, a0, 30
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    lw a0, 0(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sh2adduw:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    sh2add.uw a0, a0, a1
 ; RV64IB-NEXT:    lw a0, 0(a0)
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: sh2adduw:
 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    sh2add.uw a0, a0, a1
 ; RV64IBA-NEXT:    lw a0, 0(a0)
 ; RV64IBA-NEXT:    ret
   %3 = zext i32 %0 to i64
   %4 = getelementptr inbounds i32, i32* %1, i64 %3
   %5 = load i32, i32* %4
   ret i32 %5
 }
 
 define i64 @sh2adduw_2(i64 %0, i64 %1) {
 ; RV64I-LABEL: sh2adduw_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 2
-; RV64I-NEXT:    addi a2, zero, 1
-; RV64I-NEXT:    slli a2, a2, 34
-; RV64I-NEXT:    addi a2, a2, -4
-; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 30
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sh2adduw_2:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    sh2add.uw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: sh2adduw_2:
 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    sh2add.uw a0, a0, a1
 ; RV64IBA-NEXT:    ret
   %3 = shl i64 %0, 2
   %4 = and i64 %3, 17179869180
   %5 = add i64 %4, %1
   ret i64 %5
 }
 
 define i64 @sh3adduw(i32 signext %0, i64* %1) {
 ; RV64I-LABEL: sh3adduw:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 32
-; RV64I-NEXT:    srli a0, a0, 32
-; RV64I-NEXT:    slli a0, a0, 3
+; RV64I-NEXT:    srli a0, a0, 29
 ; RV64I-NEXT:    add a0, a1, a0
 ; RV64I-NEXT:    ld a0, 0(a0)
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sh3adduw:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    sh3add.uw a0, a0, a1
 ; RV64IB-NEXT:    ld a0, 0(a0)
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBA-LABEL: sh3adduw:
 ; RV64IBA:       # %bb.0:
 ; RV64IBA-NEXT:    sh3add.uw a0, a0, a1
 ; RV64IBA-NEXT:    ld a0, 0(a0)
 ; RV64IBA-NEXT:    ret
   %3 = zext i32 %0 to i64
   %4 = getelementptr inbounds i64, i64* %1, i64 %3
   %5 = load i64, i64* %4
   ret i64 %5
 }
 
 define i64 @sh3adduw_2(i64 %0, i64 %1) {
 ; RV64I-LABEL: sh3adduw_2:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    slli a0, a0, 3
-; RV64I-NEXT:    addi a2, zero, 1
-; RV64I-NEXT:    slli a2, a2, 35
-; RV64I-NEXT:    addi a2, a2, -8
-; RV64I-NEXT:    and a0, a0, a2
+; RV64I-NEXT:    slli a0, a0, 32
+; RV64I-NEXT:    srli a0, a0, 29
 ; RV64I-NEXT:    add a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: sh3adduw_2:
 ; RV64IB:       # %bb.0:
 ; RV64IB-NEXT:    sh3add.uw a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;