Page MenuHomePhabricator

[RISCV] Add isel patterns to optimize slli.uw patterns without Zba extension.
ClosedPublic

Authored by craig.topper on Jan 23 2021, 10:10 AM.

Details

Summary

This pattern can occur when an unsigned is used to index an array
on RV64.

Diff Detail

Event Timeline

craig.topper created this revision.Jan 23 2021, 10:10 AM
craig.topper requested review of this revision.Jan 23 2021, 10:10 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 23 2021, 10:10 AM
Herald added a subscriber: MaskRay. · View Herald Transcript
jrtc27 added inline comments.Jan 23 2021, 10:13 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.td
336

This is just NegImm and ImmSub32 composed?

jrtc27 added inline comments.Jan 23 2021, 10:15 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.td
336

(also a shorter name that doesn't require spelling 32 in words would be ImmSubFrom32)

craig.topper added inline comments.Jan 23 2021, 10:18 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.td
336

SDNodeXForms can't be composed can they?

Rename to ImmSubFrom32
Remove ImmROTL2RW which was identical to ImmSubFrom32 in another file
Rename ImmROTL2R to ImmSubFromXLen for consistency

jrtc27 added inline comments.Jan 23 2021, 10:35 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.td
336

Hmm, you can in the patterns but seems there's no way to declare an alias for that.

jrtc27 added inline comments.Jan 23 2021, 10:38 AM
llvm/lib/Target/RISCV/RISCVInstrInfoB.td
48–49

Probably worth just moving this now; no doubt something will come along later that needs it.

Move ImmSubFromXLen to RISCVInstrInfo.td

luismarques accepted this revision.Jan 25 2021, 1:25 PM

LGTM. Nice!

This revision is now accepted and ready to land.Jan 25 2021, 1:25 PM