[AArch64][GlobalISel] Fix instruction selection for G_USUBO

[porglezomp]

Summary

G_USUBO needs to be checked for overflow with the LO condition code
instead of the HS condition code.

[porglezomp]

I don't know the most convenient way to provide this—should I squash this onto the D95032 review instead, so it can get re-reviewed/tested there, and then these re-landed?

[porglezomp]

I also reopened D95032 with the fix squashed onto that, please review whichever of them will be more convenient.

[aemerson]

In D95275#2517024, @porglezomp wrote:

I also reopened D95032 with the fix squashed onto that, please review whichever of them will be more convenient.

It's fine to use the existing review.

llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

default:
     llvm_unreachable("Unexpected opcode!");
   case TargetOpcode::G_SADDO:
     return std::make_pair(emitADDS(Dst, LHS, RHS, MIRBuilder), AArch64CC::VS);
   case TargetOpcode::G_UADDO:
     return std::make_pair(emitADDS(Dst, LHS, RHS, MIRBuilder), AArch64CC::HS);
   case TargetOpcode::G_SSUBO:
     return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::VS);
   case TargetOpcode::G_USUBO:
-    return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::HS);
+    return std::make_pair(emitSUBS(Dst, LHS, RHS, MIRBuilder), AArch64CC::LO);
   }
 }
 
 bool AArch64InstructionSelector::tryOptSelect(MachineInstr &I) const {
   MachineIRBuilder MIB(I);
   MachineRegisterInfo &MRI = *MIB.getMRI();
   // We want to recognize this pattern:
   //

llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir

body:             |
   bb.1.entry:
     liveins: $w0, $w1, $x2
 
     ; CHECK-LABEL: name: usubo_s32
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
     ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
-    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
     ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
     ; CHECK: $w0 = COPY [[UBFMWri1]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s32) = COPY $w0
     %1:gpr(s32) = COPY $w1
     %3:gpr(s32), %4:gpr(s1) = G_USUBO %0, %1
     %5:gpr(s8) = G_ZEXT %4(s1)
body:             |
   bb.1.entry:
     liveins: $x0, $x1, $x2
 
     ; CHECK-LABEL: name: usubo_s64
     ; CHECK: liveins: $x0, $x1, $x2
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
     ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
-    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[CSINCWr]], 0, 0
     ; CHECK: [[UBFMWri1:%[0-9]+]]:gpr32 = UBFMWri [[UBFMWri]], 0, 7
     ; CHECK: $w0 = COPY [[UBFMWri1]]
     ; CHECK: RET_ReallyLR implicit $w0
     %0:gpr(s64) = COPY $x0
     %1:gpr(s64) = COPY $x1
     %3:gpr(s64), %4:gpr(s1) = G_USUBO %0, %1
     %5:gpr(s8) = G_ZEXT %4(s1)
body:             |
   bb.1.entry:
     liveins: $w0, $w1, $x2
     ; Check that we get ADDSWri when we can fold in a constant.
     ;
     ; CHECK-LABEL: name: usubo_s32_imm
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK: %copy:gpr32sp = COPY $w0
     ; CHECK: %add:gpr32 = SUBSWri %copy, 16, 0, implicit-def $nzcv
-    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $w0 = COPY %add
     ; CHECK: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 16
     %add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy, %constant
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
bb.1.entry:
     liveins: $w0, $w1, $x2
     ; Check that we get ADDSWrs when we can fold in a shift.
     ;
     ; CHECK-LABEL: name: usubo_s32_shifted
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK: %copy1:gpr32 = COPY $w0
     ; CHECK: %copy2:gpr32 = COPY $w1
     ; CHECK: %add:gpr32 = SUBSWrs %copy1, %copy2, 16, implicit-def $nzcv
-    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $w0 = COPY %add
     ; CHECK: RET_ReallyLR implicit $w0
     %copy1:gpr(s32) = COPY $w0
     %copy2:gpr(s32) = COPY $w1
     %constant:gpr(s32) = G_CONSTANT i32 16
     %shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
     %add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy1, %shift
     $w0 = COPY %add(s32)
body:             |
   bb.1.entry:
     liveins: $w0, $w1, $x2
     ; Check that we get SUBSWri when we can fold in a negative constant.
     ;
     ; CHECK-LABEL: name: usubo_s32_neg_imm
     ; CHECK: liveins: $w0, $w1, $x2
     ; CHECK: %copy:gpr32sp = COPY $w0
     ; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
-    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $w0 = COPY %add
     ; CHECK: RET_ReallyLR implicit $w0
     %copy:gpr(s32) = COPY $w0
     %constant:gpr(s32) = G_CONSTANT i32 -16
     %add:gpr(s32), %overflow:gpr(s1) = G_USUBO %copy, %constant
     $w0 = COPY %add(s32)
     RET_ReallyLR implicit $w0
 
 ...
 ---
 name:            usubo_arith_extended
 alignment:       4
 legalized:       true
 regBankSelected: true
 tracksRegLiveness: true
 body:             |
   bb.1.entry:
     liveins: $w0, $x0
     ; Check that we get ADDSXrx.
     ; CHECK-LABEL: name: usubo_arith_extended
     ; CHECK: liveins: $w0, $x0
     ; CHECK: %reg0:gpr64sp = COPY $x0
     ; CHECK: %reg1:gpr32 = COPY $w0
     ; CHECK: %add:gpr64 = SUBSXrx %reg0, %reg1, 18, implicit-def $nzcv
-    ; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
+    ; CHECK: %flags:gpr32 = CSINCWr $wzr, $wzr, 2, implicit $nzcv
     ; CHECK: $x0 = COPY %add
     ; CHECK: RET_ReallyLR implicit $x0
     %reg0:gpr(s64) = COPY $x0
     %reg1:gpr(s32) = COPY $w0
     %ext:gpr(s64) = G_ZEXT %reg1(s32)
     %cst:gpr(s64) = G_CONSTANT i64 2
     %shift:gpr(s64) = G_SHL %ext, %cst(s64)
     %add:gpr(s64), %flags:gpr(s1) = G_USUBO %reg0, %shift
     $x0 = COPY %add(s64)
     RET_ReallyLR implicit $x0