[RISCV] Don't create LMUL=8 pseudo instructions for ternary widening arithmetic instructions

[craig.topper]

Summary

These instructions produce 2*SEW result so the input can't have
an LMUL=8 or the result would need a non-existant LMUL=16. So
only create pseudos for LMUL up to 4.

[arcbbb]

LGTM. Thanks!

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

 multiclass VPseudoTernaryV_VX_AAXA<bit IsFloat, string Constraint = ""> {
   foreach m = MxList.m in
     defm !if(IsFloat, "_VF", "_VX") : VPseudoTernary<m.vrclass,
                              !if(IsFloat, FPR32, GPR), m.vrclass, m, Constraint>;
 }
 
 multiclass VPseudoTernaryW_VV {
   defvar constraint = "@earlyclobber $rd";
-  foreach m = MxList.m in
+  foreach m = MxList.m[0-5] in
     defm _VV : VPseudoTernary<m.wvrclass, m.vrclass, m.vrclass, m, constraint>;
 }
 
 multiclass VPseudoTernaryW_VX<bit IsFloat> {
   defvar constraint = "@earlyclobber $rd";
-  foreach m = MxList.m in
+  foreach m = MxList.m[0-5] in
     defm !if(IsFloat, "_VF", "_VX")  : VPseudoTernary<m.wvrclass,
                              !if(IsFloat, FPR32, GPR), m.vrclass, m, constraint>;
 }
 
 multiclass VPseudoTernaryV_VI<Operand ImmType = simm5, string Constraint = ""> {
   foreach m = MxList.m in
     defm _VI : VPseudoTernary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
 }