[PowerPC][AIX] Enable Shrinkwrapping on 32 and 64 bit AIX.

[sidbav]

Summary

Currently Shrinkwrap is not enabled on AIX.
This patch enables shrink wrap on 32 and 64 bit AIX, and 64 bit ELF.

[jsji]

Please add testcases.

[nemanjai]

In D95094#2511062, @jsji wrote:

Please add testcases.

Any PPC64/PPC64LE test cases for shrink-wrapping can be updated to have a couple of new RUN lines (for 32-bit and 64-bit AIX).

[sidbav]

Add test cases for 32 and 64 bit AIX

[sidbav]

Ping!

[sidbav]

Ping

[sfertile]

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

3

A lot of lines in this patch add whitespace error, I get the following message when applying this patch with git:

warning: squelched 28 whitespace errors
warning: 33 lines add whitespace errors.

This line adds one, but there are too many to call out each individually on phab. Can you open the files that were modified in this patch in vim and highlight trailing whitespace and remove it on any line that was modified?

[sidbav]

Remove trailing whitespace

[sfertile]

llvm/test/CodeGen/PowerPC/shrink-wrap.ll

2

When there are more then one check-prefix, then we use --check-prefixes=AIX,32AIX instead of using '-check-prefix' multiple times.

2

Both the new run lines have trailing whitespace.

50

Looking at this test we don't really need to worry about the differences between the codegen specific to Aix vs Linux. The important part of the test is showing that we don't shrink-wrap into a basic-block that is executed significantly more then the entry and exit blocks (IIUC). We can use regex to remove the difference between the labels, and skip some of the instructions which aren't critical to the test, and end up using all the same checks for Linux and 64-bit AIX, then a couple different checks for 32-bit codegen.

; CHECK-LABEL: {{[\.]?}}shrinkwrapme:
; CHECK:       # %bb.0:
; CHECK-NEXT:    cmpwi
; Prolog code
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std
; CHECK64:         std

; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw
; CHECK32:         stw

; CHECK:         blt 0, {{.*}}BB0_3
; CHECK:       # %bb.1:
; CHECK:         li
; CHECK:       {{.*}}BB0_2:
; CHECK:         add
; CHECK:         bdnz {{.*}}BB0_2
; CHECK-NEXT:    b {{.*}}BB0_4
; CHECK:       {{.*}}BB0_3:
; CHECK-NEXT:    li
; CHECK:       {{.*}}BB0_4:

; Epilog code
; CHECK64-DAG:         extsw
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld
; CHECK64-DAG:         ld

; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz
; CHECK32:         lwz

; CHECK:         blr

We can even skip the extsw instruction in the 64-bit prologue and simplify by removing the 'DAG' checks.

[jsji]

llvm/test/CodeGen/PowerPC/shrink-wrap.ll

31–32

You can use <PREFIX>-COUNT-<num> to match multiple lines with the same pattern over and over again.

[sfertile]

llvm/test/CodeGen/PowerPC/shrink-wrap.ll

2

I would stick with power9 for the cpu on the AIX runsteps also, just to keep consilient with the existing runstep.

llvm/test/CodeGen/PowerPC/shrink-wrap.mir

3

ditto on using same cpu as existing runstep.

[sidbav]

Address Comments, remove redundant checks.

[sfertile]

I'll need a bit more time to finish going through ppc-shrink-wrapping.ll but the patch is looking really good. Thanks for the updates.

llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll

5

This test is about shrink-wrapping in the presence of sibling calls, but for AIX we won't emit sib calls or tail calls.
I suggest having a single run step for AIX which uses -tailcallopt -disable-ppc-sco=false --enable-shrink-wrap=true options and checks for the error we emit in the backend. Then when we address tail-calling it will remind us to update this test.

llvm/test/CodeGen/PowerPC/shrink-wrap.ll

31–32

I didn't know we could do this, it really helps the readability of this test.

[sidbav]

Update ppc64-sibcall-shrinkwrap.ll to currently fail since tail calling is not implemented yet.

[sfertile]

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

28

This should stay a `CHECK' lable, we expect this instruction on all platforms.

87

This should stay a `CHECK' lable, we expect this instruction on all platforms.

218

This should stay a `CHECK' lable, we expect this instruction on all platforms.

219–231

We expect the same instructions on both 64-bit targets, we just schedule them slightly differently between Linux and Aix. we should be able to common them up by checking more instructions and using check dag. Something like:

; CHECK: mflr {{[0-9]+}}

; DISABLE64-DAG: std {{[0-9]+}}
; DISABLE64-DAG: std {{[0-9]+}}
; DISABLE64-DAG: std {{[0-9]+}}
; DISABLE64-DAG: stdu 1,
; DISABLE64-DAG: cmplwi 3, 0

; DISABLE32-DAG: stw {{[0-9]+}}
; DISABLE32-DAG: stw {{[0-9]+}}
; DISABLE32-DAG: stw {{[0-9]+}}
; DISABLE32-DAG: stwu 1,
; DISABLE32-DAG: cmplwi 3, 0

; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]

416–418

This check line and the next should be common for both 64-bit targets.

438–439

This check line and the next should be common for both 64-bit targets.

548

CHECK-LINUX-NEXT -> CHECK-NEXT

551

ENABLE-LINUX -> ENABLE

[sfertile]

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

307

These 2 checks should be combined:
ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]

313–325

Similarly here we should not need to differentiate based on target OS. Something like:

; DISABLE64-DAG: std {{[0-9]+}}
; DISABLE64-DAG: std {{[0-9]+}}
; DISABLE64-DAG: std {{[0-9]+}}
; DISABLE64-DAG: stdu 1,
; DISABLE64-DAG: cmplwi 3, 0

; DISABLE32-DAG: stw {{[0-9]+}}
; DISABLE32-DAG: stw {{[0-9]+}}
; DISABLE32-DAG: stw {{[0-9]+}}
; DISABLE32-DAG: stwu 1,
; DISABLE32-DAG: cmplwi 3, 0

; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]

[sfertile]

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

418

Lets change the DISABLE-32AIX label to DIABLE32 to highlight the differences are due to 32-bit vs 64-bit codegen and not Linux vs AIX.

508

DISABLE-LINUX --> DISABLE

[sidbav]

Updates based on feedback.

[sfertile]

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

311

CHECK-LINUX -> CHECK

397

Real minor nit: delete this line.

433

CHECK-LINUX -> CHECK-DAG

440–441

Real minor nit: delete this line.

633–634

The original test is checking that we generate a bclr instruction in the functions body (ie in-between func_begin and func_end). The Label checks ensures we are inside the expected function though so we can simplify this to:

; CHECK-LABEL: {{.*}}infiniteloop3
; CHECK: bclr

[sidbav]

Address Comments

[sfertile]

LGTM.

llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll

6

Real minor nit: when commenting in a lit test we use ;; to make it standout more.

[sidbav]

Address comments

llvm/lib/Target/PowerPC/PPCFrameLowering.cpp

 
 unsigned PPCFrameLowering::getBasePointerSaveOffset() const {
   return BasePointerSaveOffset;
 }
 
 bool PPCFrameLowering::enableShrinkWrapping(const MachineFunction &MF) const {
   if (MF.getInfo<PPCFunctionInfo>()->shrinkWrapDisabled())
     return false;
-  return (MF.getSubtarget<PPCSubtarget>().isSVR4ABI() &&
-          MF.getSubtarget<PPCSubtarget>().isPPC64());
+  return !MF.getSubtarget<PPCSubtarget>().is32BitELFABI();
 }

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

-; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
-; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false -verify-machineinstrs |  FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-64,ENABLE-64
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false -verify-machineinstrs |  FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-64,DISABLE-64
+; RUN: llc -mtriple=powerpc-ibm-aix-xcoff -mattr=-altivec -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-32,ENABLE-32
+; RUN: llc -mtriple=powerpc-ibm-aix-xcoff %s -o - -enable-shrink-wrap=false -verify-machineinstrs |  FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-32,DISABLE-32
+; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff -mattr=-altivec -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,ENABLE,CHECK-64,ENABLE-64
+; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff %s -o - -enable-shrink-wrap=false -verify-machineinstrs |  FileCheck %s --check-prefixes=CHECK,DISABLE,CHECK-64,DISABLE-64
+;
 ;
 ; Note: Lots of tests use inline asm instead of regular calls.
 ; This allows to have a better control on what the allocation will do.
 ; Otherwise, we may have spill right in the entry block, defeating
 ; shrink-wrapping. Moreover, some of the inline asm statement (nop)
 ; are here to ensure that the related paths do not end up as critical
 ; edges.
 
 
 ; Initial motivating example: Simple diamond with a call just on one side.
-; CHECK-LABEL: foo:
+; CHECK-LABEL: {{.*}}foo:
 ;
 ; Compare the arguments and return
 ; No prologue needed.
 ; ENABLE: cmpw 3, 4
 ; ENABLE-NEXT: bgelr 0
 ;
 ; Prologue code.
 ;  At a minimum, we save/restore the link register. Other registers may be saved
-;  as well. 
-; CHECK: mflr 
+;  as well.
+; CHECK: mflr
 ;
 ; Compare the arguments and jump to exit.
 ; After the prologue is set.
 ; DISABLE: cmpw 3, 4
-; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]]
+; DISABLE-NEXT: bge 0, {{.*}}[[EXIT_LABEL:BB[0-9_]+]]
 ;
 ; Store %a on the stack
 ; CHECK: stw 3, {{[0-9]+([0-9]+)}}
 ; Set the alloca address in the second argument.
 ; CHECK-NEXT: addi 4, 1, {{[0-9]+}}
 ; Set the first argument to zero.
 ; CHECK-NEXT: li 3, 0
-; CHECK-NEXT: bl doSomething
+; CHECK-NEXT: bl {{.*}}doSomething
 ;
 ; With shrink-wrapping, epilogue is just after the call.
 ; Restore the link register and return.
-; Note that there could be other epilog code before the link register is 
+; Note that there could be other epilog code before the link register is
 ; restored but we will not check for it here.
 ; ENABLE: mtlr
 ; ENABLE-NEXT: blr
 ;
 ; DISABLE: [[EXIT_LABEL]]:
 ;
 ; Without shrink-wrapping, epilogue is in the exit block.
 ; Epilogue code. (What we pop does not matter.)
false:
   %tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
   ret i32 %tmp.0
 }
 
 ; Function Attrs: optsize
 declare i32 @doSomething(i32, i32*)
 
 
-
 ; Check that we do not perform the restore inside the loop whereas the save
 ; is outside.
-; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
+; CHECK-LABEL: {{.*}}freqSaveAndRestoreOutsideLoop:
 ;
 ; Shrink-wrapping allows to skip the prologue in the else case.
 ; ENABLE: cmplwi 3, 0
-; ENABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; ENABLE: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ;
 ; Prologue code.
 ; Make sure we save the link register
 ; CHECK: mflr {{[0-9]+}}
 ;
 ; DISABLE: cmplwi 3, 0
-; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; DISABLE: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ;
 ; Loop preheader
 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
 ; CHECK-DAG: li [[IV:[0-9]+]], 10
-; 
+;
 ; Loop body
-; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
-; CHECK: bl something
+; CHECK: {{.*}}[[LOOP:BB[0-9_]+]]: # %for.body
+; CHECK: bl {{.*}}something
+;
 ; CHECK-DAG: addi [[IV]], [[IV]], -1
-; CHECK-DAG: add [[SUM]], 3, [[SUM]] 
-; CHECK-NEXT: cmplwi [[IV]], 0
-; CHECK-NEXT: bne 0, .[[LOOP]]
+; CHECK-DAG: add [[SUM]], 3, [[SUM]]
+; CHECK-DAG: cmplwi [[IV]], 0
+; CHECK-NEXT: bne 0, {{.*}}[[LOOP]]
 ;
 ; Next BB.
 ; CHECK: slwi 3, [[SUM]], 3
 ;
 ; Jump to epilogue.
-; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
+; DISABLE: b {{.*}}[[EPILOG_BB:BB[0-9_]+]]
 ;
-; DISABLE: .[[ELSE_LABEL]]: # %if.else
+; DISABLE: {{.*}}[[ELSE_LABEL]]: # %if.else
 ; Shift second argument by one and store into returned register.
 ; DISABLE: slwi 3, 4, 1
-; DISABLE: .[[EPILOG_BB]]: # %if.end
+; DISABLE: {{.*}}[[EPILOG_BB]]: # %if.end
 ;
 ; Epilogue code.
 ; CHECK: mtlr {{[0-9]+}}
 ; CHECK: blr
 ;
-; ENABLE: .[[ELSE_LABEL]]: # %if.else
+; ENABLE: {{.*}}[[ELSE_LABEL]]: # %if.else
 ; Shift second argument by one and store into returned register.
 ; ENABLE: slwi 3, 4, 1
 ; ENABLE-NEXT: blr
 define i32 @freqSaveAndRestoreOutsideLoop(i32 %cond, i32 %N) {
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.preheader
 
if.end:                                           ; preds = %if.else, %for.end
   %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
   ret i32 %sum.1
 }
 
 declare i32 @something(...)
 
 ; Check that we do not perform the shrink-wrapping inside the loop even
 ; though that would be legal. The cost model must prevent that.
-; CHECK-LABEL: freqSaveAndRestoreOutsideLoop2:
+; CHECK-LABEL: {{.*}}freqSaveAndRestoreOutsideLoop2:
 ; Prologue code.
 ; Make sure we save the link register before the call
 ; CHECK: mflr {{[0-9]+}}
 ;
 ; Loop preheader
 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
 ; CHECK-DAG: li [[IV:[0-9]+]], 10
-; 
+;
 ; Loop body
-; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
-; CHECK: bl something
+; CHECK: {{.*}}[[LOOP:BB[0-9_]+]]: # %for.body
+; CHECK: bl {{.*}}something
+;
 ; CHECK-DAG: addi [[IV]], [[IV]], -1
-; CHECK-DAG: add [[SUM]], 3, [[SUM]] 
-; CHECK-NEXT: cmplwi [[IV]], 0
-; CHECK-NEXT: bne 0, .[[LOOP]]
+; CHECK-DAG: add [[SUM]], 3, [[SUM]]
+; CHECK-DAG: cmplwi [[IV]], 0
+;
+; CHECK-NEXT: bne 0, {{.*}}[[LOOP]]
 ;
 ; Next BB
 ; CHECK: %for.exit
 ; CHECK: mtlr {{[0-9]+}}
 ; CHECK: blr
 define i32 @freqSaveAndRestoreOutsideLoop2(i32 %cond) {
 entry:
   br label %for.preheader

 
 for.end:                                          ; preds = %for.body
   ret i32 %add
 }
 
 
 ; Check with a more complex case that we do not have save within the loop and
 ; restore outside.
-; CHECK-LABEL: loopInfoSaveOutsideLoop:
+; CHECK-LABEL: {{.*}}loopInfoSaveOutsideLoop:
 ;
 ; ENABLE: cmplwi 3, 0
-; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ;
 ; Prologue code.
-; Make sure we save the link register 
+; Make sure we save the link register
 ; CHECK: mflr {{[0-9]+}}
 ;
-; DISABLE: std
-; DISABLE-NEXT: std
-; DISABLE: cmplwi 3, 0
-; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; DISABLE-64-DAG: std {{[0-9]+}}
+; DISABLE-64-DAG: std {{[0-9]+}}
+; DISABLE-64-DAG: std {{[0-9]+}}
+; DISABLE-64-DAG: stdu 1,
+; DISABLE-64-DAG: cmplwi 3, 0
+;
+; DISABLE-32-DAG: stw {{[0-9]+}}
+; DISABLE-32-DAG: stw {{[0-9]+}}
+; DISABLE-32-DAG: stw {{[0-9]+}}
+; DISABLE-32-DAG: stwu 1,
+; DISABLE-32-DAG: cmplwi 3, 0
+;
+; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ;
 ; Loop preheader
 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
 ; CHECK-DAG: li [[IV:[0-9]+]], 10
-; 
+;
 ; Loop body
-; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
-; CHECK: bl something
+; CHECK: {{.*}}[[LOOP:BB[0-9_]+]]: # %for.body
+; CHECK: bl {{.*}}something
+;
 ; CHECK-DAG: addi [[IV]], [[IV]], -1
-; CHECK-DAG: add [[SUM]], 3, [[SUM]] 
-; CHECK-NEXT: cmplwi [[IV]], 0
-; CHECK-NEXT: bne 0, .[[LOOP]]
-; 
+; CHECK-DAG: add [[SUM]], 3, [[SUM]]
+; CHECK-DAG: cmplwi [[IV]], 0
+;
+; CHECK-NEXT: bne 0, {{.*}}[[LOOP]]
+;
 ; Next BB
-; CHECK: bl somethingElse 
+; CHECK: bl {{.*}}somethingElse
 ; CHECK: slwi 3, [[SUM]], 3
 ;
 ; Jump to epilogue
-; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
+; DISABLE: b {{.*}}[[EPILOG_BB:BB[0-9_]+]]
 ;
-; DISABLE: .[[ELSE_LABEL]]: # %if.else
+; DISABLE: {{.*}}[[ELSE_LABEL]]: # %if.else
 ; Shift second argument by one and store into returned register.
 ; DISABLE: slwi 3, 4, 1
 ;
-; DISABLE: .[[EPILOG_BB]]: # %if.end
+; DISABLE: {{.*}}[[EPILOG_BB]]: # %if.end
+;
 ; Epilog code
 ; CHECK: mtlr {{[0-9]+}}
 ; CHECK: blr
-; 
-; ENABLE: .[[ELSE_LABEL]]: # %if.else
+;
+; ENABLE: {{.*}}[[ELSE_LABEL]]: # %if.else
 ; Shift second argument by one and store into returned register.
 ; ENABLE: slwi 3, 4, 1
 ; ENABLE-NEXT: blr
 define i32 @loopInfoSaveOutsideLoop(i32 %cond, i32 %N) {
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.preheader
 
if.end:                                           ; preds = %if.else, %for.end
   %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
   ret i32 %sum.1
 }
 
 declare void @somethingElse(...)
 
 ; Check with a more complex case that we do not have restore within the loop and
 ; save outside.
-; CHECK-LABEL: loopInfoRestoreOutsideLoop:
+; CHECK-LABEL: {{.*}}loopInfoRestoreOutsideLoop:
 ;
 ; ENABLE: cmplwi 3, 0
-; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ;
 ; Prologue code.
 ; Make sure we save the link register
 ; CHECK: mflr {{[0-9]+}}
 ;
-; DISABLE: std
-; DISABLE-NEXT: std
-; DISABLE: cmplwi 3, 0
-; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; DISABLE-64-DAG: std {{[0-9]+}}
+; DISABLE-64-DAG: std {{[0-9]+}}
+; DISABLE-64-DAG: std {{[0-9]+}}
+; DISABLE-64-DAG: stdu 1,
+; DISABLE-64-DAG: cmplwi 3, 0
+;
+; DISABLE-32-DAG: stw {{[0-9]+}}
+; DISABLE-32-DAG: stw {{[0-9]+}}
+; DISABLE-32-DAG: stw {{[0-9]+}}
+; DISABLE-32-DAG: stwu 1,
+; DISABLE-32-DAG: cmplwi 3, 0
+;
+; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ;
-; CHECK: bl somethingElse
+; CHECK: bl {{.*}}somethingElse
 ;
 ; Loop preheader
 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
 ; CHECK-DAG: li [[IV:[0-9]+]], 10
-; 
+;
 ; Loop body
-; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
-; CHECK: bl something
+; CHECK: {{.*}}[[LOOP:BB[0-9_]+]]: # %for.body
+; CHECK: bl {{.*}}something
+;
 ; CHECK-DAG: addi [[IV]], [[IV]], -1
-; CHECK-DAG: add [[SUM]], 3, [[SUM]] 
-; CHECK-NEXT: cmplwi [[IV]], 0
-; CHECK-NEXT: bne 0, .[[LOOP]]
+; CHECK-DAG: add [[SUM]], 3, [[SUM]]
+; CHECK-DAG: cmplwi [[IV]], 0
+;
+; CHECK-NEXT: bne 0, {{.*}}[[LOOP]]
 ;
-; Next BB. 
-; slwi 3, [[SUM]], 3
+; Next BB.
+; CHECK: slwi 3, [[SUM]], 3
 ;
-; DISABLE: b .[[EPILOG_BB:LBB[0-9_]+]]
+; DISABLE: b {{.*}}[[EPILOG_BB:BB[0-9_]+]]
 ;
-; DISABLE: .[[ELSE_LABEL]]: # %if.else
+; DISABLE: {{.*}}[[ELSE_LABEL]]: # %if.else
 ; Shift second argument by one and store into returned register.
 ; DISABLE: slwi 3, 4, 1
-; DISABLE: .[[EPILOG_BB]]: # %if.end
+; DISABLE: {{.*}}[[EPILOG_BB]]: # %if.end
 ;
 ; Epilogue code.
 ; CHECK: mtlr {{[0-9]+}}
 ; CHECK: blr
 ;
-; ENABLE: .[[ELSE_LABEL]]: # %if.else
+; ENABLE: {{.*}}[[ELSE_LABEL]]: # %if.else
 ; Shift second argument by one and store into returned register.
 ; ENABLE: slwi 3, 4, 1
 ; ENABLE-NEXT: blr
 define i32 @loopInfoRestoreOutsideLoop(i32 %cond, i32 %N) nounwind {
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %if.then
 
if.else:                                          ; preds = %entry
   br label %if.end
 
 if.end:                                           ; preds = %if.else, %for.end
   %sum.1 = phi i32 [ %shl, %for.end ], [ %mul, %if.else ]
   ret i32 %sum.1
 }
 
 ; Check that we handle function with no frame information correctly.
-; CHECK-LABEL: emptyFrame:
+; CHECK-LABEL: {{.*}}emptyFrame:
 ; CHECK: # %entry
 ; CHECK-NEXT: li 3, 0
 ; CHECK-NEXT: blr
 define i32 @emptyFrame() {
 entry:
   ret i32 0
 }
 
 
 ; Check that we handle inline asm correctly.
-; CHECK-LABEL: inlineAsm:
+; CHECK-LABEL: {{.*}}inlineAsm:
 ;
 ; ENABLE: cmplwi 3, 0
-; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ;
 ; Prologue code.
 ; Make sure we save the CSR used in the inline asm: r14
 ; ENABLE-DAG: li [[IV:[0-9]+]], 10
-; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
+; ENABLE-64-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
+; ENABLE-32-DAG: stw 14, -[[STACK_OFFSET:[0-9]+]](1) # 4-byte Folded Spill
 ;
 ; DISABLE: cmplwi 3, 0
-; DISABLE-NEXT: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
-; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; DISABLE-64-NEXT: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
+; DISABLE-32-NEXT: stw 14, -[[STACK_OFFSET:[0-9]+]](1) # 4-byte Folded Spill
+; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ; DISABLE: li [[IV:[0-9]+]], 10
 ;
 ; CHECK: nop
 ; CHECK: mtctr [[IV]]
 ;
-; CHECK: .[[LOOP_LABEL:LBB[0-9_]+]]: # %for.body
+; CHECK: {{.*}}[[LOOP_LABEL:BB[0-9_]+]]: # %for.body
 ; Inline asm statement.
 ; CHECK: addi 14, 14, 1
-; CHECK: bdnz .[[LOOP_LABEL]]
+; CHECK: bdnz {{.*}}[[LOOP_LABEL]]
 ;
 ; Epilogue code.
 ; CHECK: li 3, 0
-; CHECK-DAG: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
-; CHECK: nop
+; CHECK-64-DAG: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
+; CHECK-32-DAG: lwz 14, -[[STACK_OFFSET]](1) # 4-byte Folded Reload
+; CHECK-DAG: nop
 ; CHECK: blr
 ;
 ; CHECK: [[ELSE_LABEL]]
 ; CHECK-NEXT: slwi 3, 4, 1
-; DISABLE: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
+; DISABLE-64-NEXT: ld 14, -[[STACK_OFFSET]](1) # 8-byte Folded Reload
+; DISABLE-32-NEXT: lwz 14, -[[STACK_OFFSET]](1) # 4-byte Folded Reload
 ; CHECK-NEXT: blr
-; 
 define i32 @inlineAsm(i32 %cond, i32 %N) {
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %for.preheader
 
 for.preheader:
   tail call void asm "nop", ""()
   br label %for.body
 

 
 if.end:                                           ; preds = %for.body, %if.else
   %sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]
   ret i32 %sum.0
 }
 
 
 ; Check that we handle calls to variadic functions correctly.
-; CHECK-LABEL: callVariadicFunc:
+; CHECK-LABEL: {{.*}}callVariadicFunc:
 ;
 ; ENABLE: cmplwi 3, 0
-; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; ENABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ;
 ; Prologue code.
 ; CHECK: mflr {{[0-9]+}}
-; 
+;
 ; DISABLE: cmplwi 3, 0
-; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
+; DISABLE-NEXT: beq 0, {{.*}}[[ELSE_LABEL:BB[0-9_]+]]
 ;
 ; Setup of the varags.
-; CHECK: mr 4, 3
-; CHECK-NEXT: mr 5, 3
-; CHECK-NEXT: mr 6, 3
-; CHECK-NEXT: mr 7, 3
-; CHECK-NEXT: mr 8, 3
-; CHECK-NEXT: mr 9, 3
-; CHECK-NEXT: bl someVariadicFunc
+; CHECK-64: mr 4, 3
+; CHECK-64-NEXT: mr 5, 3
+; CHECK-64-NEXT: mr 6, 3
+; CHECK-64-NEXT: mr 7, 3
+; CHECK-64-NEXT: mr 8, 3
+; CHECK-64-NEXT: mr 9, 3
+;
+; CHECK-32: mr 3, 4
+; CHECK-32-NEXT: mr 5, 4
+; CHECK-32-NEXT: mr 6, 4
+; CHECK-32-NEXT: mr 7, 4
+; CHECK-32-NEXT: mr 8, 4
+; CHECK-32-NEXT: mr 9, 4
+;
+; CHECK-NEXT: bl {{.*}}someVariadicFunc
 ; CHECK: slwi 3, 3, 3
-; DISABLE: b .[[EPILOGUE_BB:LBB[0-9_]+]]
+; DISABLE: b {{.*}}[[EPILOGUE_BB:BB[0-9_]+]]
 ;
 ; ENABLE: mtlr {{[0-9]+}}
 ; ENABLE-NEXT: blr
 ;
-; CHECK: .[[ELSE_LABEL]]: # %if.else
+; CHECK: {{.*}}[[ELSE_LABEL]]: # %if.else
 ; CHECK-NEXT: slwi 3, 4, 1
-; 
-; DISABLE: .[[EPILOGUE_BB]]: # %if.end
+;
+; DISABLE: {{.*}}[[EPILOGUE_BB]]: # %if.end
 ; DISABLE: mtlr
 ; CHECK: blr
 define i32 @callVariadicFunc(i32 %cond, i32 %N) {
 entry:
   %tobool = icmp eq i32 %cond, 0
   br i1 %tobool, label %if.else, label %if.then
 
 if.then:                                          ; preds = %entry

 declare i32 @someVariadicFunc(i32, ...)
 
 
 
 ; Make sure we do not insert unreachable code after noreturn function.
 ; Although this is not incorrect to insert such code, it is useless
 ; and it hurts the binary size.
 ;
-; CHECK-LABEL: noreturn:
+; CHECK-LABEL: {{.*}}noreturn:
 ; DISABLE: mflr {{[0-9]+}}
 ;
 ; CHECK: cmplwi 3, 0
-; CHECK-NEXT: bne{{[-]?}} 0, .[[ABORT:LBB[0-9_]+]]
+; CHECK-NEXT: bne{{[-]?}} 0, {{.*}}[[ABORT:BB[0-9_]+]]
 ;
 ; CHECK: li 3, 42
 ;
 ; DISABLE: mtlr {{[0-9]+}}
 ;
 ; CHECK-NEXT: blr
 ;
-; CHECK: .[[ABORT]]: # %if.abort
-;
+; CHECK: {{.*}}[[ABORT]]: # %if.abort
 ; ENABLE: mflr {{[0-9]+}}
-;
-; CHECK: bl abort
+; CHECK: bl {{.*}}abort
 ; ENABLE-NOT: mtlr {{[0-9]+}}
 define i32 @noreturn(i8 signext %bad_thing) {
 entry:
   %tobool = icmp eq i8 %bad_thing, 0
   br i1 %tobool, label %if.end, label %if.abort
 
 if.abort:
   tail call void @abort() #0

 
 ; Make sure that we handle infinite loops properly When checking that the Save
 ; and Restore blocks are control flow equivalent, the loop searches for the
 ; immediate (post) dominator for the (restore) save blocks. When either the Save
 ; or Restore block is located in an infinite loop the only immediate (post)
 ; dominator is itself. In this case, we cannot perform shrink wrapping, but we
 ; should return gracefully and continue compilation.
 ; The only condition for this test is the compilation finishes correctly.
-; 
-; CHECK-LABEL: infiniteloop
+;
+; CHECK-LABEL: {{.*}}infiniteloop
 ; CHECK: blr
 define void @infiniteloop() {
 entry:
   br i1 undef, label %if.then, label %if.end
 
 if.then:
   %ptr = alloca i32, i32 4
   br label %for.body
 
 for.body:                                         ; preds = %for.body, %entry
   %sum.03 = phi i32 [ 0, %if.then ], [ %add, %for.body ]
   %call = tail call i32 bitcast (i32 (...)* @something to i32 ()*)()
   %add = add nsw i32 %call, %sum.03
   store i32 %add, i32* %ptr
   br label %for.body
 
 if.end:
   ret void
 }
 
 ; Another infinite loop test this time with a body bigger than just one block.
-; CHECK-LABEL: infiniteloop2
+; CHECK-LABEL: {{.*}}infiniteloop2
 ; CHECK: blr
 define void @infiniteloop2() {
 entry:
   br i1 undef, label %if.then, label %if.end
 
 if.then:
   %ptr = alloca i32, i32 4
   br label %for.body
body2:
   tail call void asm sideeffect "nop", "~{r14}"()
   br label %for.body
 
 if.end:
   ret void
 }
 
 ; Another infinite loop test this time with two nested infinite loop.
-; CHECK-LABEL: infiniteloop3
-; CHECK: Lfunc_begin[[FUNCNUM:[0-9]+]]
+; CHECK-LABEL: {{.*}}infiniteloop3
 ; CHECK: bclr
-; CHECK: Lfunc_end[[FUNCNUM]]
 define void @infiniteloop3() {
 entry:
   br i1 undef, label %loop2a, label %body
 
 body:                                             ; preds = %entry
   br i1 undef, label %loop2a, label %end
 
 loop1:                                            ; preds = %loop2a, %loop2b
   %var.phi = phi i32* [ %next.phi, %loop2b ], [ %var, %loop2a ]

 @lock = common global i32 0, align 4
 @htindex = common global i32 0, align 4
 @stride = common global i32 0, align 4
 @ht = common global i32* null, align 8
 @he = common global i8* null, align 8
 
 ; Test for a bug that was caused when save point was equal to restore point.
 ; Function Attrs: nounwind
-; CHECK-LABEL: transpose
+; CHECK-LABEL: {{.*}}transpose
 ;
 ; Store of callee-save register saved by shrink wrapping
 ; FIXME: Test disabled: Improved scheduling needs no spills/reloads any longer!
 ; CHECKXX: std [[CSR:[0-9]+]], -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
 ;
 ; Reload of callee-save register
 ; CHECKXX: ld [[CSR]], -[[STACK_OFFSET]](1) # 8-byte Folded Reload
 ;

llvm/test/CodeGen/PowerPC/ppc64-sibcall-shrinkwrap.ll

 ; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY
 ; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-ONLY
 ; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=false | FileCheck %s -check-prefix=CHECK-SCO-ONLY
 ; RUN: llc -relocation-model=static -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-linux-gnu -disable-ppc-sco=false --enable-shrink-wrap=true | FileCheck %s -check-prefix=CHECK-SCO-ONLY
+; RUN: not --crash llc -relocation-model=pic -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -tailcallopt -disable-ppc-sco=false --enable-shrink-wrap=true 2>&1 | FileCheck %s -check-prefix=CHECK-AIX
+; The above RUN command is expected to fail on AIX since tail calling is not implemented ATM
 ; Edit: D63152 prevents stack popping before loads and stores, so shrink-wrap does nothing here
 %"class.clang::NamedDecl" = type { i32 }
 declare void @__assert_fail();
 
 define dso_local i8 @_ZNK5clang9NamedDecl23getLinkageAndVisibilityEv(
     %"class.clang::NamedDecl"* %this) {
 entry:
   %tobool = icmp eq %"class.clang::NamedDecl"* %this, null

 ; CHECK-SCO-SHRK: stdu 1, -{{[0-9]+}}(1)
 ; CHECK-SCO-SHRK: bl __assert_fail
 ;
 ; CHECK-SCO-ONLY-LABEL: _ZNK5clang9NamedDecl23getLinkageAndVisibilityEv:
 ; CHECK-SCO-ONLY: stdu 1, -{{[0-9]+}}(1)
 ; CHECK-SCO-ONLY: b LVComputationKind
 ; CHECK-SCO-ONLY: #TC_RETURNd8
 ; CHECK-SCO-ONLY: bl __assert_fail
+;
+; CHECK-AIX: LLVM ERROR: Tail call support is unimplemented on AIX.
 }
 
 define dso_local fastcc i8 @LVComputationKind(
     %"class.clang::NamedDecl"* %D,
     i32 %computation) {
   ret i8 0
 }

llvm/test/CodeGen/PowerPC/shrink-wrap.ll

-; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck  %s
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr9 | FileCheck  %s --check-prefixes=CHECK,CHECK64
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc-ibm-aix-xcoff -mcpu=pwr9 -mattr=-altivec | FileCheck  %s --check-prefixes=CHECK,CHECK32
+; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr9 -mattr=-altivec | FileCheck  %s --check-prefixes=CHECK,CHECK64
+
 define signext i32 @shrinkwrapme(i32 signext %a, i32 signext %lim) {
 entry:
   %cmp5 = icmp sgt i32 %lim, 0
   br i1 %cmp5, label %for.body.preheader, label %for.cond.cleanup
 
  for.body.preheader:                               ; preds = %entry
   br label %for.body
 
  for.cond.cleanup.loopexit:                        ; preds = %for.body
   br label %for.cond.cleanup
 
  for.cond.cleanup:                                 ; preds = %for.cond.cleanup.loopexit, %entry
   %Ret.0.lcssa = phi i32 [ 0, %entry ], [ %0, %for.cond.cleanup.loopexit ]
   ret i32 %Ret.0.lcssa
 
  for.body:                                         ; preds = %for.body.preheader, %for.body
   %i.07 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
   %Ret.06 = phi i32 [ %0, %for.body ], [ 0, %for.body.preheader ]
   %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"(i32 %a, i32 %Ret.06)
   %inc = add nuw nsw i32 %i.07, 1
   %exitcond = icmp eq i32 %inc, %lim
   br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
 
-; CHECK-LABEL: shrinkwrapme
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpwi
+; CHECK-LABEL: {{[\.]?}}shrinkwrapme:
+; CHECK:            # %bb.0:
+; CHECK-NEXT:         cmpwi
 ; Prolog code
-; CHECK:         std 
-; CHECK:         std 
-; CHECK:         std 
-; CHECK:         std 
-; CHECK:         blt 0, .LBB0_3
-; CHECK:       # %bb.1:
-; CHECK-NEXT:    clrldi
-; CHECK-NEXT:    mtctr
-; CHECK-NEXT:    li 
-; CHECK:       .LBB0_2: 
-; CHECK:         add
-; CHECK:         bdnz .LBB0_2 
-; CHECK-NEXT:    b .LBB0_4
-; CHECK:       .LBB0_3: 
-; CHECK-NEXT:    li 
-; CHECK:       .LBB0_4: 
+; CHECK64-COUNT-18:   std
+
+; CHECK32-COUNT-18:   stw
+
+; CHECK:              blt 0, {{.*}}BB0_3
+; CHECK:            # %bb.1:
+; CHECK:              li
+; CHECK:            {{.*}}BB0_2:
+; CHECK:              add
+; CHECK:              bdnz {{.*}}BB0_2
+; CHECK-NEXT:         b {{.*}}BB0_4
+; CHECK:            {{.*}}BB0_3:
+; CHECK-NEXT:         li
+; CHECK:            {{.*}}BB0_4:
+
 ; Epilog code
-; CHECK:         ld 
-; CHECK:         ld 
-; CHECK:         extsw
-; CHECK:         ld 
-; CHECK:         ld 
-; CHECK:         blr
+; CHECK64-COUNT-18:   ld
+;
+; CHECK32-COUNT-18:   lwz
+
+; CHECK:              blr
 }

llvm/test/CodeGen/PowerPC/shrink-wrap.mir

 # RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc64le-unknown-linux-gnu \
 # RUN:   -run-pass=shrink-wrap -o - %s | FileCheck %s
+# RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc-ibm-aix-xcoff \
+# RUN:   -run-pass=shrink-wrap -mattr=-altivec -o - %s | FileCheck %s
+# RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple powerpc64-ibm-aix-xcoff \
+# RUN:   -run-pass=shrink-wrap -mattr=-altivec -o - %s | FileCheck %s
 --- |
   ; ModuleID = 'test.ll'
   source_filename = "test.ll"
   target datalayout = "e-m:e-i64:64-n32:64"
-  
   define signext i32 @shrinkwrapme(i32 signext %a, i32 signext %lim) {
   entry:
     %cmp5 = icmp sgt i32 %lim, 0
     br i1 %cmp5, label %for.body.preheader, label %for.cond.cleanup
-  
   for.body.preheader:                               ; preds = %entry
     %0 = add i32 %lim, -1
     %1 = zext i32 %0 to i64
     %2 = add nuw nsw i64 %1, 1
     call void @llvm.set.loop.iterations.i64(i64 %2)
     br label %for.body
-  
   for.cond.cleanup:                                 ; preds = %for.body, %entry
     %Ret.0.lcssa = phi i32 [ 0, %entry ], [ %3, %for.body ]
     ret i32 %Ret.0.lcssa
-  
   for.body:                                         ; preds = %for.body, %for.body.preheader
     %Ret.06 = phi i32 [ %3, %for.body ], [ 0, %for.body.preheader ]
     %3 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15},~{r16},~{r17},~{r18},~{r19},~{r20},~{r21},~{r22},~{r23},~{r24},~{r25},~{r26},~{r27},~{r28},~{r29},~{r30},~{r31}"(i32 %a, i32 %Ret.06)
     %4 = call i1 @llvm.loop.decrement.i64(i64 1)
     br i1 %4, label %for.body, label %for.cond.cleanup
   }
-  
   ; Function Attrs: noduplicate nounwind
   declare void @llvm.set.loop.iterations.i64(i64) #0
-  
   ; Function Attrs: noduplicate nounwind
   declare i1 @llvm.loop.decrement.i64(i64) #0
-  
   ; Function Attrs: nounwind
   declare void @llvm.stackprotector(i8*, i8**) #1
-  
   attributes #0 = { noduplicate nounwind }
   attributes #1 = { nounwind }
 
 ...
 ---
 name:            shrinkwrapme
 alignment:       16
 exposesReturnsTwice: false

 stack:           []
 callSites:       []
 constants:       []
 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     successors: %bb.2(0x50000000), %bb.1(0x30000000)
     liveins: $x3, $x4
-  
     renamable $cr0 = CMPWI renamable $r4, 1
     BCC 4, killed renamable $cr0, %bb.2
-  
   bb.1:
     successors: %bb.3(0x80000000)
-  
     renamable $r4 = LI 0
     B %bb.3
-  
   bb.2.for.body.preheader:
     successors: %bb.4(0x80000000)
     liveins: $x3, $x4
-  
     renamable $r4 = ADDI renamable $r4, -1, implicit killed $x4, implicit-def $x4
     renamable $x4 = RLDICL killed renamable $x4, 0, 32
     renamable $x4 = nuw nsw ADDI8 killed renamable $x4, 1
     MTCTR8loop killed renamable $x4, implicit-def dead $ctr8
     renamable $r4 = LI 0
     B %bb.4
-  
   bb.3.for.cond.cleanup:
     liveins: $r4
-  
     renamable $x3 = EXTSW_32_64 killed renamable $r4
     BLR8 implicit $lr8, implicit $rm, implicit $x3
-  
   bb.4.for.body:
     successors: %bb.4(0x7c000000), %bb.3(0x04000000)
     liveins: $r4, $x3
-  
     INLINEASM &"add $0, $1, $2", 0, 131082, def renamable $r4, 131081, renamable $r3, 131081, killed renamable $r4, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15, 12, implicit-def dead early-clobber $r16, 12, implicit-def dead early-clobber $r17, 12, implicit-def dead early-clobber $r18, 12, implicit-def dead early-clobber $r19, 12, implicit-def dead early-clobber $r20, 12, implicit-def dead early-clobber $r21, 12, implicit-def dead early-clobber $r22, 12, implicit-def dead early-clobber $r23, 12, implicit-def dead early-clobber $r24, 12, implicit-def dead early-clobber $r25, 12, implicit-def dead early-clobber $r26, 12, implicit-def dead early-clobber $r27, 12, implicit-def dead early-clobber $r28, 12, implicit-def dead early-clobber $r29, 12, implicit-def dead early-clobber $r30, 12, implicit-def dead early-clobber $r31
     BDNZ8 %bb.4, implicit-def dead $ctr8, implicit $ctr8
     B %bb.3
 
   ; CHECK:      savePoint:       ''
   ; CHECK-NEXT: restorePoint:    ''
 
   ; CHECK:      bb.4.for.body:
   ; CHECK-NEXT:   successors: %bb.4(0x7c000000), %bb.3(0x04000000)
   ; CHECK-NEXT:   liveins: $r4, $x3
   ; CHECK:        INLINEASM
   ; CHECK-NEXT:   BDNZ8 %bb.4
   ; CHECK-NEXT:   B %bb.3
 ...