With tfe on there can be a vgpr write to vdata+1.
Add tablegen support for 5 register vdata store.
This is required for 4 register vdata store with tfe.
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[AMDGPU][MC] Add tfe disassembler support MIMG opcodes ClosedPublic Authored by Petar.Avramovic on Jan 19 2021, 3:44 AM.
Details Summary With tfe on there can be a vgpr write to vdata+1.
Diff Detail Event TimelineHerald added subscribers: kerbowa, hiraditya, t-tye and 6 others. · View Herald TranscriptJan 19 2021, 3:44 AM This revision is now accepted and ready to land.Jan 19 2021, 6:52 AM Closed by commit rG4ab704d62820: [AMDGPU][MC] Add tfe disassembler support MIMG opcodes (authored by Petar.Avramovic). · Explain WhyJan 20 2021, 1:37 AM This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 317513 llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
llvm/lib/Target/AMDGPU/MIMGInstructions.td
llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt
llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt
llvm/test/MC/Disassembler/AMDGPU/mimg_vi.txt
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