[SystemZ] Introducing assembler dialects for the Z backend

[anirudhp]

Summary

• This patch introduces a different assembler dialect ("hlasm") for z/OS. The default dialect has now been given the "att" dialect name. For this appropriate changes have been added to SystemZ.td.
• This patch also makes a few changes to SystemZInstrFormats.td which restrict a few condition code mnemonics to just the "att" dialect variant (he, le, lh, nhe, nle, nlh). These extended condition code mnemonics are not available in HLASM.
• A new private function has been introduced in SystemZAsmParser.cpp to return the assembler dialect set in SystemZMCAsmInfo.cpp. The reason we couldn't/haven't explicitly queried the overriden getAssemblerDialect function from AsmParser is outlined in this thread here. This returned dialect is directly passed onto the relevant matcher functions which taken in a variantID, so that the matcher functions can appropriately choose an instruction based on the variant.

[anirudhp]

Ping :)

[uweigand]

Just a quick comment that I'm looking at this, but before approval I want to resolve the issues described in the comment in front of getMAIAssemblerDialect. See also discussion here: https://reviews.llvm.org/D82862

[anirudhp]

In D94250#2498246, @uweigand wrote:

Just a quick comment that I'm looking at this, but before approval I want to resolve the issues described in the comment in front of getMAIAssemblerDialect. See also discussion here: https://reviews.llvm.org/D82862

Thanks!

[uweigand]

Looks like resolving the general issues with the AsmDialect setting is more complicated than I thought and may still take a while.

Therefore, I think you should go ahead and commit this patch with the work-around described in getMAIAssemblerDialect for now. This is certainly correct for all SystemZ use case. If we do find a better solution in common code, this hack can still be removed at a later date.

LGTM.

[anirudhp]

In D94250#2589934, @uweigand wrote:

Looks like resolving the general issues with the AsmDialect setting is more complicated than I thought and may still take a while.

Therefore, I think you should go ahead and commit this patch with the work-around described in getMAIAssemblerDialect for now. This is certainly correct for all SystemZ use case. If we do find a better solution in common code, this hack can still be removed at a later date.

LGTM.

Thank you!

llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/SystemZInstPrinter.h"
 #include "MCTargetDesc/SystemZMCTargetDesc.h"
 #include "TargetInfo/SystemZTargetInfo.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstBuilder.h"
 #include "llvm/MC/MCParser/MCAsmLexer.h"
 #include "llvm/MC/MCParser/MCAsmParser.h"
 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
OperandMatchResultTy parseAddress(OperandVector &Operands,
                                     MemoryKind MemKind,
                                     RegisterKind RegKind);
 
   OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
                                   int64_t MaxVal, bool AllowTLS);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
+  // Both the hlasm and att variants still rely on the basic gnu asm
+  // format with respect to inputs, clobbers, outputs etc.
+  //
+  // However, calling the overriden getAssemblerDialect() method in
+  // AsmParser is problematic. It either returns the AssemblerDialect field
+  // in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is
+  // unset, otherwise it returns the private AssemblerDialect field in
+  // AsmParser.
+  //
+  // The problematic part is because, we forcibly set the inline asm dialect
+  // in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query
+  // to the overriden getAssemblerDialect function in AsmParser.cpp, will
+  // not return the assembler dialect set in the respective MCAsmInfo instance.
+  //
+  // For this purpose, we explicitly query the SystemZMCAsmInfo instance
+  // here, to get the "correct" assembler dialect, and use it in various
+  // functions.
+  unsigned getMAIAssemblerDialect() {
+    return Parser.getContext().getAsmInfo()->getAssemblerDialect();
+  }
+
 public:
   SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser,
                    const MCInstrInfo &MII,
                    const MCTargetOptions &Options)
     : MCTargetAsmParser(Options, sti, MII), Parser(parser) {
     MCAsmParserExtension::Initialize(Parser);
 
     // Alias the .word directive to .short.

 }
 
 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
                                         StringRef Name, SMLoc NameLoc,
                                         OperandVector &Operands) {
 
   // Apply mnemonic aliases first, before doing anything else, in
   // case the target uses it.
-  applyMnemonicAliases(Name, getAvailableFeatures(), 0 /*VariantID*/);
+  applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect());
 
   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
 
   // Read the remaining operands.
   if (getLexer().isNot(AsmToken::EndOfStatement)) {
     // Read the first operand.
     if (parseOperand(Operands, Name)) {
       return true;

 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                                OperandVector &Operands,
                                                MCStreamer &Out,
                                                uint64_t &ErrorInfo,
                                                bool MatchingInlineAsm) {
   MCInst Inst;
   unsigned MatchResult;
 
+  unsigned Dialect = getMAIAssemblerDialect();
+
   FeatureBitset MissingFeatures;
-  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
-                                     MissingFeatures, MatchingInlineAsm);
+  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,
+                                     MatchingInlineAsm, Dialect);
   switch (MatchResult) {
   case Match_Success:
     Inst.setLoc(IDLoc);
     Out.emitInstruction(Inst, getSTI());
     return false;
 
   case Match_MissingFeature: {
     assert(MissingFeatures.any() && "Unknown missing feature!");
if (ErrorInfo != ~0ULL) {
         ErrorLoc = IDLoc;
     }
     return Error(ErrorLoc, "invalid operand for instruction");
   }
 
   case Match_MnemonicFail: {
     FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits());
     std::string Suggestion = SystemZMnemonicSpellCheck(
-      ((SystemZOperand &)*Operands[0]).getToken(), FBS);
+        ((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect);
     return Error(IDLoc, "invalid instruction" + Suggestion,
                  ((SystemZOperand &)*Operands[0]).getLocRange());
   }
   }
 
   llvm_unreachable("Unexpected match type");
 }
 

llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmInfo.cpp

 //===-- SystemZMCAsmInfo.cpp - SystemZ asm properties ---------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "SystemZMCAsmInfo.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCSectionELF.h"
 
 using namespace llvm;
 
+enum AsmDialect { AD_ATT = 0, AD_HLASM = 1 };
+
 SystemZMCAsmInfo::SystemZMCAsmInfo(const Triple &TT) {
   CodePointerSize = 8;
   CalleeSaveStackSlotSize = 8;
   IsLittleEndian = false;
 
+  AssemblerDialect = TT.isOSzOS() ? AD_HLASM : AD_ATT;
+
   MaxInstLength = 6;
 
   CommentString = "#";
   ZeroDirective = "\t.space\t";
   Data64bitsDirective = "\t.quad\t";
   UsesELFSectionDirectiveForBSS = true;
   SupportsDebugInformation = true;
   ExceptionsType = ExceptionHandling::DwarfCFI;
 }

llvm/lib/Target/SystemZ/SystemZ.td

 //===----------------------------------------------------------------------===//
 // Assembly parser
 //===----------------------------------------------------------------------===//
 
 def SystemZAsmParser : AsmParser {
   let ShouldEmitMatchRegisterName = 0;
 }
 
+def ATTAsmParserVariant : AsmParserVariant {
+  int Variant = 0;
+
+  // Variant name.
+  string Name = "att";
+}
+
+def HLASMAsmParserVariant : AsmParserVariant {
+  int Variant = 1;
+
+  // Variant name.
+  string Name = "hlasm";
+}
+
 //===----------------------------------------------------------------------===//
 // Top-level target declaration
 //===----------------------------------------------------------------------===//
 
 def SystemZ : Target {
   let InstructionSet = SystemZInstrInfo;
   let AssemblyParsers = [SystemZAsmParser];
+  let AssemblyParserVariants = [ATTAsmParserVariant, HLASMAsmParserVariant];
   let AllowRegisterRenaming = 1;
 }

llvm/lib/Target/SystemZ/SystemZInstrFormats.td

 // We don't make one of the two names an alias of the other because
 // we need the custom parsing routines to select the correct register class.
 //
 // This section provides helpers for generating the specific forms.
 //
 //===----------------------------------------------------------------------===//
 
 // A class to describe a variant of an instruction with condition mask.
-class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein> {
+class CondVariant<bits<4> ccmaskin, string suffixin, bit alternatein,
+                  string asmvariantin = ""> {
   // The fixed condition mask to use.
   bits<4> ccmask = ccmaskin;
 
   // The suffix to use for the extended assembler mnemonic.
   string suffix = suffixin;
 
   // Whether this is an alternate that needs to be marked isAsmParserOnly.
   bit alternate = alternatein;
+
+  // Whether this needs be to restricted to a specific dialect.
+  // Valid values are "att" and "hlasm", which when passed in
+  // will set AsmVariantName.
+  string asmvariant = asmvariantin;
 }
 
 // Condition mask 15 means "always true", which is used to define
 // unconditional branches as a variant of conditional branches.
 def CondAlways : CondVariant<15, "", 0>;
 
 // Condition masks for general instructions that can set all 4 bits.
 def CondVariantO   : CondVariant<1,  "o",   0>;
 def CondVariantH   : CondVariant<2,  "h",   0>;
 def CondVariantP   : CondVariant<2,  "p",   1>;
-def CondVariantNLE : CondVariant<3,  "nle", 0>;
+def CondVariantNLE : CondVariant<3,  "nle", 0, "att">;
 def CondVariantL   : CondVariant<4,  "l",   0>;
 def CondVariantM   : CondVariant<4,  "m",   1>;
-def CondVariantNHE : CondVariant<5,  "nhe", 0>;
-def CondVariantLH  : CondVariant<6,  "lh",  0>;
+def CondVariantNHE : CondVariant<5,  "nhe", 0, "att">;
+def CondVariantLH  : CondVariant<6,  "lh",  0, "att">;
 def CondVariantNE  : CondVariant<7,  "ne",  0>;
 def CondVariantNZ  : CondVariant<7,  "nz",  1>;
 def CondVariantE   : CondVariant<8,  "e",   0>;
 def CondVariantZ   : CondVariant<8,  "z",   1>;
-def CondVariantNLH : CondVariant<9,  "nlh", 0>;
-def CondVariantHE  : CondVariant<10, "he",  0>;
+def CondVariantNLH : CondVariant<9,  "nlh", 0, "att">;
+def CondVariantHE  : CondVariant<10, "he",  0, "att">;
 def CondVariantNL  : CondVariant<11, "nl",  0>;
 def CondVariantNM  : CondVariant<11, "nm",  1>;
-def CondVariantLE  : CondVariant<12, "le",  0>;
+def CondVariantLE  : CondVariant<12, "le",  0, "att">;
 def CondVariantNH  : CondVariant<13, "nh",  0>;
 def CondVariantNP  : CondVariant<13, "np",  1>;
 def CondVariantNO  : CondVariant<14, "no",  0>;
 
 // A helper class to look up one of the above by name.
 class CV<string name>
   : CondVariant<!cast<CondVariant>("CondVariant"#name).ccmask,
                 !cast<CondVariant>("CondVariant"#name).suffix,
-                !cast<CondVariant>("CondVariant"#name).alternate>;
+                !cast<CondVariant>("CondVariant"#name).alternate,
+                !cast<CondVariant>("CondVariant"#name).asmvariant>;
 
 // Condition masks for integer instructions (e.g. compare-and-branch).
 // This is like the list above, except that condition 3 is not possible
 // and that the low bit of the mask is therefore always 0.  This means
 // that each condition has two names.  Conditions "o" and "no" are not used.
 def IntCondVariantH   : CondVariant<2,  "h",   0>;
-def IntCondVariantNLE : CondVariant<2,  "nle", 1>;
+def IntCondVariantNLE : CondVariant<2,  "nle", 1, "att">;
 def IntCondVariantL   : CondVariant<4,  "l",   0>;
-def IntCondVariantNHE : CondVariant<4,  "nhe", 1>;
-def IntCondVariantLH  : CondVariant<6,  "lh",  0>;
+def IntCondVariantNHE : CondVariant<4,  "nhe", 1, "att">;
+def IntCondVariantLH  : CondVariant<6,  "lh",  0, "att">;
 def IntCondVariantNE  : CondVariant<6,  "ne",  1>;
 def IntCondVariantE   : CondVariant<8,  "e",   0>;
-def IntCondVariantNLH : CondVariant<8,  "nlh", 1>;
-def IntCondVariantHE  : CondVariant<10, "he",  0>;
+def IntCondVariantNLH : CondVariant<8,  "nlh", 1, "att">;
+def IntCondVariantHE  : CondVariant<10, "he",  0, "att">;
 def IntCondVariantNL  : CondVariant<10, "nl",  1>;
-def IntCondVariantLE  : CondVariant<12, "le",  0>;
+def IntCondVariantLE  : CondVariant<12, "le",  0, "att">;
 def IntCondVariantNH  : CondVariant<12, "nh",  1>;
 
 // A helper class to look up one of the above by name.
 class ICV<string name>
   : CondVariant<!cast<CondVariant>("IntCondVariant"#name).ccmask,
                 !cast<CondVariant>("IntCondVariant"#name).suffix,
-                !cast<CondVariant>("IntCondVariant"#name).alternate>;
+                !cast<CondVariant>("IntCondVariant"#name).alternate,
+                !cast<CondVariant>("IntCondVariant"#name).asmvariant>;
 
 // Defines a class that makes it easier to define
 // a MnemonicAlias when CondVariant's are involved.
 class MnemonicCondBranchAlias<CondVariant V, string from, string to>
-  : MnemonicAlias<!subst("#", V.suffix, from), !subst("#", V.suffix, to)>;
+  : MnemonicAlias<!subst("#", V.suffix, from), !subst("#", V.suffix, to),
+                  V.asmvariant>;
 
 //===----------------------------------------------------------------------===//
 // Instruction definitions with semantics
 //===----------------------------------------------------------------------===//
 //
 // These classes have the form [Cond]<Category><Format>, where <Format> is one
 // of the formats defined above and where <Category> describes the inputs
 // and outputs.  "Cond" is used if the instruction is conditional,
: InstRIc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget16:$RI2),
             [(operator cond4:$valid, cond4:$M1, bb:$RI2)]> {
   let CCMaskFirst = 1;
 }
 
 class AsmCondBranchRI<string mnemonic, bits<12> opcode>
   : InstRIc<opcode, (outs), (ins imm32zx4:$M1, brtarget16:$RI2),
             mnemonic#"\t$M1, $RI2", []>;
 
-// Defines a class that makes it easier to define
-// a MnemonicAlias when CondVariant's are involved
-class MnemonicCondBranch<CondVariant V, string from, string to>
-  : MnemonicAlias<!subst("#", V.suffix, from), !subst("#", V.suffix, to)>;
-
 class FixedCondBranchRI<CondVariant V, string mnemonic, bits<12> opcode,
                         SDPatternOperator operator = null_frag>
   : InstRIc<opcode, (outs), (ins brtarget16:$RI2),
             !subst("#", V.suffix, mnemonic)#"\t$RI2", [(operator bb:$RI2)]> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M1 = V.ccmask;
 }
 
 class CondBranchRIL<string mnemonic, bits<12> opcode>
   : InstRILc<opcode, (outs), (ins cond4:$valid, cond4:$M1, brtarget32:$RI2),
              !subst("#", "${M1}", mnemonic)#"\t$RI2", []> {
   let CCMaskFirst = 1;
 }
 
 class AsmCondBranchRIL<string mnemonic, bits<12> opcode>
   : InstRILc<opcode, (outs), (ins imm32zx4:$M1, brtarget32:$RI2),
              mnemonic#"\t$M1, $RI2", []>;
 
 class FixedCondBranchRIL<CondVariant V, string mnemonic, bits<12> opcode>
   : InstRILc<opcode, (outs), (ins brtarget32:$RI2),
              !subst("#", V.suffix, mnemonic)#"\t$RI2", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M1 = V.ccmask;
 }
 
 class CondBranchRR<string mnemonic, bits<8> opcode>
   : InstRR<opcode, (outs), (ins cond4:$valid, cond4:$R1, GR64:$R2),
            !subst("#", "${R1}", mnemonic)#"\t$R2", []> {
   let CCMaskFirst = 1;
 }
 
 class AsmCondBranchRR<string mnemonic, bits<8> opcode>
   : InstRR<opcode, (outs), (ins imm32zx4:$R1, GR64:$R2),
            mnemonic#"\t$R1, $R2", []>;
 
 class FixedCondBranchRR<CondVariant V, string mnemonic, bits<8> opcode,
                       SDPatternOperator operator = null_frag>
   : InstRR<opcode, (outs), (ins ADDR64:$R2),
            !subst("#", V.suffix, mnemonic)#"\t$R2", [(operator ADDR64:$R2)]> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let R1 = V.ccmask;
 }
 
 class CondBranchRX<string mnemonic, bits<8> opcode>
   : InstRXb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr12only:$XBD2),
             !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
   let CCMaskFirst = 1;
 }
 
 class AsmCondBranchRX<string mnemonic, bits<8> opcode>
   : InstRXb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr12only:$XBD2),
             mnemonic#"\t$M1, $XBD2", []>;
 
 class FixedCondBranchRX<CondVariant V, string mnemonic, bits<8> opcode>
   : InstRXb<opcode, (outs), (ins bdxaddr12only:$XBD2),
             !subst("#", V.suffix, mnemonic)#"\t$XBD2", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M1 = V.ccmask;
 }
 
 class CondBranchRXY<string mnemonic, bits<16> opcode>
   : InstRXYb<opcode, (outs), (ins cond4:$valid, cond4:$M1, bdxaddr20only:$XBD2),
              !subst("#", "${M1}", mnemonic)#"\t$XBD2", []> {
   let CCMaskFirst = 1;
   let mayLoad = 1;
 }
 
 class AsmCondBranchRXY<string mnemonic, bits<16> opcode>
   : InstRXYb<opcode, (outs), (ins imm32zx4:$M1, bdxaddr20only:$XBD2),
              mnemonic#"\t$M1, $XBD2", []> {
   let mayLoad = 1;
 }
 
 class FixedCondBranchRXY<CondVariant V, string mnemonic, bits<16> opcode,
                          SDPatternOperator operator = null_frag>
   : InstRXYb<opcode, (outs), (ins bdxaddr20only:$XBD2),
              !subst("#", V.suffix, mnemonic)#"\t$XBD2",
              [(operator (load bdxaddr20only:$XBD2))]> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M1 = V.ccmask;
   let mayLoad = 1;
 }
 
 class CmpBranchRIEa<string mnemonic, bits<16> opcode,
                     RegisterOperand cls, ImmOpWithPattern imm>
   : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, cond4:$M3),
              mnemonic#"$M3\t$R1, $I2", []>;
 
 class AsmCmpBranchRIEa<string mnemonic, bits<16> opcode,
                        RegisterOperand cls, ImmOpWithPattern imm>
   : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2, imm32zx4:$M3),
              mnemonic#"\t$R1, $I2, $M3", []>;
 
 class FixedCmpBranchRIEa<CondVariant V, string mnemonic, bits<16> opcode,
                           RegisterOperand cls, ImmOpWithPattern imm>
   : InstRIEa<opcode, (outs), (ins cls:$R1, imm:$I2),
              mnemonic#V.suffix#"\t$R1, $I2", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CmpBranchRIEaPair<string mnemonic, bits<16> opcode,
                              RegisterOperand cls, ImmOpWithPattern imm> {
   let isCodeGenOnly = 1 in
     def "" : CmpBranchRIEa<mnemonic, opcode, cls, imm>;
   def Asm : AsmCmpBranchRIEa<mnemonic, opcode, cls, imm>;
: InstRIEb<opcode, (outs),
              (ins cls:$R1, cls:$R2, imm32zx4:$M3, brtarget16:$RI4),
              mnemonic#"\t$R1, $R2, $M3, $RI4", []>;
 
 class FixedCmpBranchRIEb<CondVariant V, string mnemonic, bits<16> opcode,
                          RegisterOperand cls>
   : InstRIEb<opcode, (outs), (ins cls:$R1, cls:$R2, brtarget16:$RI4),
              mnemonic#V.suffix#"\t$R1, $R2, $RI4", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CmpBranchRIEbPair<string mnemonic, bits<16> opcode,
                              RegisterOperand cls> {
   let isCodeGenOnly = 1 in
     def "" : CmpBranchRIEb<mnemonic, opcode, cls>;
   def Asm : AsmCmpBranchRIEb<mnemonic, opcode, cls>;
: InstRIEc<opcode, (outs),
              (ins cls:$R1, imm:$I2, imm32zx4:$M3, brtarget16:$RI4),
              mnemonic#"\t$R1, $I2, $M3, $RI4", []>;
 
 class FixedCmpBranchRIEc<CondVariant V, string mnemonic, bits<16> opcode,
                          RegisterOperand cls, ImmOpWithPattern imm>
   : InstRIEc<opcode, (outs), (ins cls:$R1, imm:$I2, brtarget16:$RI4),
              mnemonic#V.suffix#"\t$R1, $I2, $RI4", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CmpBranchRIEcPair<string mnemonic, bits<16> opcode,
                             RegisterOperand cls, ImmOpWithPattern imm> {
   let isCodeGenOnly = 1 in
     def "" : CmpBranchRIEc<mnemonic, opcode, cls, imm>;
   def Asm : AsmCmpBranchRIEc<mnemonic, opcode, cls, imm>;
multiclass CmpBranchRRFcPair<string mnemonic, bits<16> opcode,
   def Asm : AsmCmpBranchRRFc<mnemonic, opcode, cls>;
 }
 
 class FixedCmpBranchRRFc<CondVariant V, string mnemonic, bits<16> opcode,
                           RegisterOperand cls>
   : InstRRFc<opcode, (outs), (ins cls:$R1, cls:$R2),
              mnemonic#V.suffix#"\t$R1, $R2", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 class CmpBranchRRS<string mnemonic, bits<16> opcode,
                    RegisterOperand cls>
   : InstRRS<opcode, (outs),
             (ins cls:$R1, cls:$R2, cond4:$M3, bdaddr12only:$BD4),
             mnemonic#"$M3\t$R1, $R2, $BD4", []>;
 
 class AsmCmpBranchRRS<string mnemonic, bits<16> opcode,
                       RegisterOperand cls>
   : InstRRS<opcode, (outs),
             (ins cls:$R1, cls:$R2, imm32zx4:$M3, bdaddr12only:$BD4),
             mnemonic#"\t$R1, $R2, $M3, $BD4", []>;
 
 class FixedCmpBranchRRS<CondVariant V, string mnemonic, bits<16> opcode,
                         RegisterOperand cls>
   : InstRRS<opcode, (outs), (ins cls:$R1, cls:$R2, bdaddr12only:$BD4),
             mnemonic#V.suffix#"\t$R1, $R2, $BD4", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CmpBranchRRSPair<string mnemonic, bits<16> opcode,
                             RegisterOperand cls> {
   let isCodeGenOnly = 1 in
     def "" : CmpBranchRRS<mnemonic, opcode, cls>;
   def Asm : AsmCmpBranchRRS<mnemonic, opcode, cls>;
: InstRIS<opcode, (outs),
             (ins cls:$R1, imm:$I2, imm32zx4:$M3, bdaddr12only:$BD4),
             mnemonic#"\t$R1, $I2, $M3, $BD4", []>;
 
 class FixedCmpBranchRIS<CondVariant V, string mnemonic, bits<16> opcode,
                         RegisterOperand cls, ImmOpWithPattern imm>
   : InstRIS<opcode, (outs), (ins cls:$R1, imm:$I2, bdaddr12only:$BD4),
             mnemonic#V.suffix#"\t$R1, $I2, $BD4", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CmpBranchRISPair<string mnemonic, bits<16> opcode,
                             RegisterOperand cls, ImmOpWithPattern imm> {
   let isCodeGenOnly = 1 in
     def "" : CmpBranchRIS<mnemonic, opcode, cls, imm>;
   def Asm : AsmCmpBranchRIS<mnemonic, opcode, cls, imm>;
multiclass CmpBranchRSYbPair<string mnemonic, bits<16> opcode,
   def Asm : AsmCmpBranchRSYb<mnemonic, opcode, cls>;
 }
 
 class FixedCmpBranchRSYb<CondVariant V, string mnemonic, bits<16> opcode,
                           RegisterOperand cls>
   : InstRSYb<opcode, (outs), (ins cls:$R1, bdaddr20only:$BD2),
              mnemonic#V.suffix#"\t$R1, $BD2", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 class BranchUnaryRI<string mnemonic, bits<12> opcode, RegisterOperand cls>
   : InstRIb<opcode, (outs cls:$R1), (ins cls:$R1src, brtarget16:$RI2),
             mnemonic#"\t$R1, $RI2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";

 class FixedCondStoreRSY<CondVariant V, string mnemonic, bits<16> opcode,
                         RegisterOperand cls, bits<5> bytes,
                         AddressingMode mode = bdaddr20only>
   : InstRSYb<opcode, (outs), (ins cls:$R1, mode:$BD2),
              mnemonic#V.suffix#"\t$R1, $BD2", []> {
   let mayStore = 1;
   let AccessBytes = bytes;
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CondStoreRSYPair<string mnemonic, bits<16> opcode,
                             RegisterOperand cls, bits<5> bytes,
                             AddressingMode mode = bdaddr20only> {
   let isCodeGenOnly = 1 in
     def "" : CondStoreRSY<mnemonic, opcode, cls, bytes, mode>;
class FixedCondUnaryRSY<CondVariant V, string mnemonic, bits<16> opcode,
                         AddressingMode mode = bdaddr20only>
   : InstRSYb<opcode, (outs cls:$R1), (ins cls:$R1src, mode:$BD2),
              mnemonic#V.suffix#"\t$R1, $BD2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let mayLoad = 1;
   let AccessBytes = bytes;
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CondUnaryRSYPair<string mnemonic, bits<16> opcode,
                             SDPatternOperator operator,
                             RegisterOperand cls, bits<5> bytes,
                             AddressingMode mode = bdaddr20only> {
   let isCodeGenOnly = 1 in

 // Like CondBinaryRRF, but with a fixed CC mask.
 class FixedCondBinaryRRF<CondVariant V, string mnemonic, bits<16> opcode,
                          RegisterOperand cls1, RegisterOperand cls2>
   : InstRRFc<opcode, (outs cls1:$R1), (ins cls1:$R1src, cls2:$R2),
              mnemonic#V.suffix#"\t$R1, $R2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CondBinaryRRFPair<string mnemonic, bits<16> opcode,
                              RegisterOperand cls1, RegisterOperand cls2> {
   let isCodeGenOnly = 1 in
     def "" : CondBinaryRRF<mnemonic, opcode, cls1, cls2>;
   def Asm : AsmCondBinaryRRF<mnemonic, opcode, cls1, cls2>;

 
 // Like CondBinaryRRFa, but with a fixed CC mask.
 class FixedCondBinaryRRFa<CondVariant V, string mnemonic, bits<16> opcode,
                          RegisterOperand cls1, RegisterOperand cls2,
                          RegisterOperand cls3>
   : InstRRFa<opcode, (outs cls1:$R1), (ins cls3:$R3, cls2:$R2),
              mnemonic#V.suffix#"\t$R1, $R2, $R3", []> {
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M4 = V.ccmask;
 }
 
 multiclass CondBinaryRRFaPair<string mnemonic, bits<16> opcode,
                              RegisterOperand cls1, RegisterOperand cls2,
                              RegisterOperand cls3> {
   let isCodeGenOnly = 1 in
     def "" : CondBinaryRRFa<mnemonic, opcode, cls1, cls2, cls3>;

 // Like CondBinaryRIE, but with a fixed CC mask.
 class FixedCondBinaryRIE<CondVariant V, string mnemonic, bits<16> opcode,
                          RegisterOperand cls, ImmOpWithPattern imm>
   : InstRIEg<opcode, (outs cls:$R1), (ins cls:$R1src, imm:$I2),
              mnemonic#V.suffix#"\t$R1, $I2", []> {
   let Constraints = "$R1 = $R1src";
   let DisableEncoding = "$R1src";
   let isAsmParserOnly = V.alternate;
+  let AsmVariantName = V.asmvariant;
   let M3 = V.ccmask;
 }
 
 multiclass CondBinaryRIEPair<string mnemonic, bits<16> opcode,
                              RegisterOperand cls, ImmOpWithPattern imm> {
   let isCodeGenOnly = 1 in
     def "" : CondBinaryRIE<mnemonic, opcode, cls, imm>;
   def Asm : AsmCondBinaryRIE<mnemonic, opcode, cls, imm>;

llvm/lib/Target/SystemZ/SystemZInstrInfo.td

let Defs = [CC] in {
     def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>;
   }
   def BXH   : BranchBinaryRS<"bxh",  0x86, GR32>;
   def BXLE  : BranchBinaryRS<"bxle", 0x87, GR32>;
   def BXHG  : BranchBinaryRSY<"bxhg",  0xEB44, GR64>;
   def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>;
 }
 
-
 //===----------------------------------------------------------------------===//
 // Trap instructions
 //===----------------------------------------------------------------------===//
 
 // Unconditional trap.
 let hasCtrlDep = 1, hasSideEffects = 1 in
   def Trap : Alias<4, (outs), (ins), [(trap)]>;