This is an archive of the discontinued LLVM Phabricator instance.

Differential D94214

[AMDGPU] Add volatile support to SIMemoryLegalizer
ClosedPublic

Authored by t-tye on Jan 6 2021, 10:59 PM.

Details

Reviewers
b-sumner
rampitec
arsenm
kzhuravl
yaxunl
scott.linder
Commits
rG2f499b9affb6: [AMDGPU] Add volatile support to SIMemoryLegalizer
Summary

Treat a non-atomic volatile load and store as a relaxed atomic at
system scope for the address spaces accessed. This will ensure all
relevant caches will be bypassed.

A volatile atomic is not changed and still only bypasses caches upto
the level specified by the SyncScope operand.

Diff Detail

Event Timeline

t-tye created this revision.Jan 6 2021, 10:59 PM
Herald added subscribers: kerbowa, jfb, arphaman and 6 others. · View Herald TranscriptJan 6 2021, 10:59 PM
t-tye requested review of this revision.Jan 6 2021, 10:59 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 6 2021, 10:59 PM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
Harbormaster completed remote builds in B84292: Diff 315052.Jan 6 2021, 11:33 PM
rampitec added a comment.Jan 7 2021, 11:46 AM

LGTM. Make sure to rerun tests before push as a lot of tests are affected.

rampitec accepted this revision.Jan 8 2021, 12:02 PM
This revision is now accepted and ready to land.Jan 8 2021, 12:02 PM
This revision was landed with ongoing or failed builds.Jan 8 2021, 4:53 PM
Closed by commit rG2f499b9affb6: [AMDGPU] Add volatile support to SIMemoryLegalizer (authored by t-tye). · Explain Why
This revision was automatically updated to reflect the committed changes.
t-tye added a commit: rG2f499b9affb6: [AMDGPU] Add volatile support to SIMemoryLegalizer.

Revision Contents

PathSize
llvm/
docs/
76 lines
lib/
Target/
AMDGPU/
146 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
4 lines
14 lines
158 lines
213 lines
81 lines
44 lines
111 lines
2 lines
2 lines
1 line
1 line
11 lines
11 lines
4 lines
20 lines
64 lines
6 lines
24 lines
1 line
2 lines
4 lines
5 lines
6 lines
20 lines
25 lines
4 lines
6 lines
21 lines
12 lines
12 lines
4 lines
79 lines
14 lines
6 lines
2 lines
12 lines
16 lines
13 lines
468 lines
90 lines
2 lines
36 lines
10 lines
8 lines
48 lines
45 lines
3 lines
5 lines
1 line
12 lines
115 lines
6 lines
24 lines
24 lines
44 lines
152 lines
50 lines
110 lines
2 lines
2 lines
10 lines
396 lines
458 lines
440 lines
404 lines
2 lines
2 lines
1 line
12 lines
4 lines
2 lines
122 lines
8 lines
82 lines
2 lines
38 lines
6 lines
5 lines
7 lines
96 lines
8 lines
4 lines
2 lines
23 lines
4 lines

Diff 315553

llvm/docs/AMDGPUUsage.rst

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,730 Lines • ▼ Show 20 Lines .. table:: AMDHSA Memory Model Code Sequences GFX6-GFX9
load *none* *none* - global - !volatile & !nontemporal load *none* *none* - global - !volatile & !nontemporal
- generic - generic
- private 1. buffer/global/flat_load - private 1. buffer/global/flat_load
- constant - constant
- volatile & !nontemporal - volatile & !nontemporal
1. buffer/global/flat_load 1. buffer/global/flat_load
glc=1 glc=1
2. s_waitcnt vmcnt(0)
- Must happen before
any following volatile
global/generic
load/store.
- Ensures that
volatile
operations to
different
addresses will not
be reordered by
hardware.
- nontemporal - !volatile & nontemporal
1. buffer/global/flat_load 1. buffer/global/flat_load
glc=1 slc=1 glc=1 slc=1
load *none* *none* - local 1. ds_load load *none* *none* - local 1. ds_load
store *none* *none* - global - !nontemporal store *none* *none* - global - !volatile & !nontemporal
- generic - generic
- private 1. buffer/global/flat_store - private 1. buffer/global/flat_store
- constant - constant
- nontemporal - volatile & !nontemporal
1. buffer/global/flat_store
2. s_waitcnt vmcnt(0)
- Must happen before
any following volatile
global/generic
load/store.
- Ensures that
volatile
operations to
different
addresses will not
be reordered by
hardware.
- !volatile & nontemporal
1. buffer/global/flat_store 1. buffer/global/flat_store
glc=1 slc=1 glc=1 slc=1
store *none* *none* - local 1. ds_store store *none* *none* - local 1. ds_store
**Unordered Atomic** **Unordered Atomic**
------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------
load atomic unordered *any* *any* *Same as non-atomic*. load atomic unordered *any* *any* *Same as non-atomic*.
▲ Show 20 Lines • Show All 1,244 Lines • ▼ Show 20 Lines .. table:: AMDHSA Memory Model Code Sequences GFX10
load *none* *none* - global - !volatile & !nontemporal load *none* *none* - global - !volatile & !nontemporal
- generic - generic
- private 1. buffer/global/flat_load - private 1. buffer/global/flat_load
- constant - constant
- volatile & !nontemporal - volatile & !nontemporal
1. buffer/global/flat_load 1. buffer/global/flat_load
glc=1 dlc=1 glc=1 dlc=1
2. s_waitcnt vmcnt(0)
- Must happen before
any following volatile
global/generic
load/store.
- Ensures that
volatile
operations to
different
addresses will not
be reordered by
hardware.
- nontemporal - !volatile & nontemporal
1. buffer/global/flat_load 1. buffer/global/flat_load
slc=1 slc=1
load *none* *none* - local 1. ds_load load *none* *none* - local 1. ds_load
store *none* *none* - global - !nontemporal store *none* *none* - global - !volatile & !nontemporal
- generic - generic
- private 1. buffer/global/flat_store - private 1. buffer/global/flat_store
- constant - constant
- nontemporal - volatile & !nontemporal
1. buffer/global/flat_store
2. s_waitcnt vscnt(0)
- Must happen before
any following volatile
global/generic
load/store.
- Ensures that
volatile
operations to
different
addresses will not
be reordered by
hardware.
- !volatile & nontemporal
1. buffer/global/flat_store 1. buffer/global/flat_store
slc=1 slc=1
store *none* *none* - local 1. ds_store store *none* *none* - local 1. ds_store
**Unordered Atomic** **Unordered Atomic**
------------------------------------------------------------------------------------ ------------------------------------------------------------------------------------
load atomic unordered *any* *any* *Same as non-atomic*. load atomic unordered *any* *any* *Same as non-atomic*.
▲ Show 20 Lines • Show All 3,409 Lines • Show Last 20 Lines

llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp

Show First 20 Lines • Show All 104 Lines • ▼ Show 20 Linesprivate:
friend class SIMemOpAccess; friend class SIMemOpAccess;
AtomicOrdering Ordering = AtomicOrdering::NotAtomic; AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic; AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic;
SIAtomicScope Scope = SIAtomicScope::SYSTEM; SIAtomicScope Scope = SIAtomicScope::SYSTEM;
SIAtomicAddrSpace OrderingAddrSpace = SIAtomicAddrSpace::NONE; SIAtomicAddrSpace OrderingAddrSpace = SIAtomicAddrSpace::NONE;
SIAtomicAddrSpace InstrAddrSpace = SIAtomicAddrSpace::NONE; SIAtomicAddrSpace InstrAddrSpace = SIAtomicAddrSpace::NONE;
bool IsCrossAddressSpaceOrdering = false; bool IsCrossAddressSpaceOrdering = false;
bool IsVolatile = false;
bool IsNonTemporal = false; bool IsNonTemporal = false;
SIMemOpInfo(AtomicOrdering Ordering = AtomicOrdering::SequentiallyConsistent, SIMemOpInfo(AtomicOrdering Ordering = AtomicOrdering::SequentiallyConsistent,
SIAtomicScope Scope = SIAtomicScope::SYSTEM, SIAtomicScope Scope = SIAtomicScope::SYSTEM,
SIAtomicAddrSpace OrderingAddrSpace = SIAtomicAddrSpace::ATOMIC, SIAtomicAddrSpace OrderingAddrSpace = SIAtomicAddrSpace::ATOMIC,
SIAtomicAddrSpace InstrAddrSpace = SIAtomicAddrSpace::ALL, SIAtomicAddrSpace InstrAddrSpace = SIAtomicAddrSpace::ALL,
bool IsCrossAddressSpaceOrdering = true, bool IsCrossAddressSpaceOrdering = true,
AtomicOrdering FailureOrdering = AtomicOrdering FailureOrdering =
AtomicOrdering::SequentiallyConsistent, AtomicOrdering::SequentiallyConsistent,
bool IsVolatile = false,
bool IsNonTemporal = false) bool IsNonTemporal = false)
: Ordering(Ordering), FailureOrdering(FailureOrdering), : Ordering(Ordering), FailureOrdering(FailureOrdering),
Scope(Scope), OrderingAddrSpace(OrderingAddrSpace), Scope(Scope), OrderingAddrSpace(OrderingAddrSpace),
InstrAddrSpace(InstrAddrSpace), InstrAddrSpace(InstrAddrSpace),
IsCrossAddressSpaceOrdering(IsCrossAddressSpaceOrdering), IsCrossAddressSpaceOrdering(IsCrossAddressSpaceOrdering),
IsVolatile(IsVolatile),
IsNonTemporal(IsNonTemporal) { IsNonTemporal(IsNonTemporal) {
// There is also no cross address space ordering if the ordering // There is also no cross address space ordering if the ordering
// address space is the same as the instruction address space and // address space is the same as the instruction address space and
// only contains a single address space. // only contains a single address space.
if ((OrderingAddrSpace == InstrAddrSpace) && if ((OrderingAddrSpace == InstrAddrSpace) &&
isPowerOf2_32(uint32_t(InstrAddrSpace))) isPowerOf2_32(uint32_t(InstrAddrSpace)))
this->IsCrossAddressSpaceOrdering = false; this->IsCrossAddressSpaceOrdering = false;
} }
Show All 31 Linespublic:
/// \returns Return true iff memory ordering of operations on /// \returns Return true iff memory ordering of operations on
/// different address spaces is required. /// different address spaces is required.
bool getIsCrossAddressSpaceOrdering() const { bool getIsCrossAddressSpaceOrdering() const {
return IsCrossAddressSpaceOrdering; return IsCrossAddressSpaceOrdering;
} }
/// \returns True if memory access of the machine instruction used to /// \returns True if memory access of the machine instruction used to
/// create this SIMemOpInfo is non-temporal, false otherwise. /// create this SIMemOpInfo is volatile, false otherwise.
bool isVolatile() const {
return IsVolatile;
}
/// \returns True if memory access of the machine instruction used to
/// create this SIMemOpInfo is nontemporal, false otherwise.
bool isNonTemporal() const { bool isNonTemporal() const {
return IsNonTemporal; return IsNonTemporal;
} }
/// \returns True if ordering constraint of the machine instruction used to /// \returns True if ordering constraint of the machine instruction used to
/// create this SIMemOpInfo is unordered or higher, false otherwise. /// create this SIMemOpInfo is unordered or higher, false otherwise.
bool isAtomic() const { bool isAtomic() const {
return Ordering != AtomicOrdering::NotAtomic; return Ordering != AtomicOrdering::NotAtomic;
▲ Show 20 Lines • Show All 71 Lines • ▼ Show 20 Linespublic:
/// Update \p MI memory load instruction to bypass any caches up to /// Update \p MI memory load instruction to bypass any caches up to
/// the \p Scope memory scope for address spaces \p /// the \p Scope memory scope for address spaces \p
/// AddrSpace. Return true iff the instruction was modified. /// AddrSpace. Return true iff the instruction was modified.
virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI, virtual bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
SIAtomicScope Scope, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace) const = 0; SIAtomicAddrSpace AddrSpace) const = 0;
/// Update \p MI memory instruction to indicate it is /// Update \p MI memory instruction of kind \p Op associated with address
/// nontemporal. Return true iff the instruction was modified. /// spaces \p AddrSpace to indicate it is volatile and/or nontemporal. Return
virtual bool enableNonTemporal(const MachineBasicBlock::iterator &MI) /// true iff the instruction was modified.
const = 0; virtual bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
SIAtomicAddrSpace AddrSpace,
SIMemOp Op, bool IsVolatile,
bool IsNonTemporal) const = 0;
/// Inserts any necessary instructions at position \p Pos relative /// Inserts any necessary instructions at position \p Pos relative
/// to instruction \p MI to ensure memory instructions before \p Pos of kind /// to instruction \p MI to ensure memory instructions before \p Pos of kind
/// \p Op associated with address spaces \p AddrSpace have completed. Used /// \p Op associated with address spaces \p AddrSpace have completed. Used
/// between memory instructions to enforce the order they become visible as /// between memory instructions to enforce the order they become visible as
/// observed by other memory instructions executing in memory scope \p Scope. /// observed by other memory instructions executing in memory scope \p Scope.
/// \p IsCrossAddrSpaceOrdering indicates if the memory ordering is between /// \p IsCrossAddrSpaceOrdering indicates if the memory ordering is between
/// address spaces. Returns true iff any instructions inserted. /// address spaces. Returns true iff any instructions inserted.
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
public: public:
SIGfx6CacheControl(const GCNSubtarget &ST) : SICacheControl(ST) {}; SIGfx6CacheControl(const GCNSubtarget &ST) : SICacheControl(ST) {};
bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI, bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
SIAtomicScope Scope, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace) const override; SIAtomicAddrSpace AddrSpace) const override;
bool enableNonTemporal(const MachineBasicBlock::iterator &MI) const override; bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
SIAtomicAddrSpace AddrSpace, SIMemOp Op,
bool IsVolatile,
bool IsNonTemporal) const override;
bool insertWait(MachineBasicBlock::iterator &MI, bool insertWait(MachineBasicBlock::iterator &MI,
SIAtomicScope Scope, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace, SIAtomicAddrSpace AddrSpace,
SIMemOp Op, SIMemOp Op,
bool IsCrossAddrSpaceOrdering, bool IsCrossAddrSpaceOrdering,
Position Pos) const override; Position Pos) const override;
Show All 33 Lines
public: public:
SIGfx10CacheControl(const GCNSubtarget &ST) : SIGfx7CacheControl(ST) {}; SIGfx10CacheControl(const GCNSubtarget &ST) : SIGfx7CacheControl(ST) {};
bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI, bool enableLoadCacheBypass(const MachineBasicBlock::iterator &MI,
SIAtomicScope Scope, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace) const override; SIAtomicAddrSpace AddrSpace) const override;
bool enableNonTemporal(const MachineBasicBlock::iterator &MI) const override; bool enableVolatileAndOrNonTemporal(MachineBasicBlock::iterator &MI,
SIAtomicAddrSpace AddrSpace, SIMemOp Op,
bool IsVolatile,
bool IsNonTemporal) const override;
bool insertWait(MachineBasicBlock::iterator &MI, bool insertWait(MachineBasicBlock::iterator &MI,
SIAtomicScope Scope, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace, SIAtomicAddrSpace AddrSpace,
SIMemOp Op, SIMemOp Op,
bool IsCrossAddrSpaceOrdering, bool IsCrossAddrSpaceOrdering,
Position Pos) const override; Position Pos) const override;
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 LinesOptional<SIMemOpInfo> SIMemOpAccess::constructFromMIWithMMO(
const MachineBasicBlock::iterator &MI) const { const MachineBasicBlock::iterator &MI) const {
assert(MI->getNumMemOperands() > 0); assert(MI->getNumMemOperands() > 0);
SyncScope::ID SSID = SyncScope::SingleThread; SyncScope::ID SSID = SyncScope::SingleThread;
AtomicOrdering Ordering = AtomicOrdering::NotAtomic; AtomicOrdering Ordering = AtomicOrdering::NotAtomic;
AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic; AtomicOrdering FailureOrdering = AtomicOrdering::NotAtomic;
SIAtomicAddrSpace InstrAddrSpace = SIAtomicAddrSpace::NONE; SIAtomicAddrSpace InstrAddrSpace = SIAtomicAddrSpace::NONE;
bool IsNonTemporal = true; bool IsNonTemporal = true;
bool IsVolatile = false;
// Validator should check whether or not MMOs cover the entire set of // Validator should check whether or not MMOs cover the entire set of
// locations accessed by the memory instruction. // locations accessed by the memory instruction.
for (const auto &MMO : MI->memoperands()) { for (const auto &MMO : MI->memoperands()) {
IsNonTemporal &= MMO->isNonTemporal(); IsNonTemporal &= MMO->isNonTemporal();
IsVolatile |= MMO->isVolatile();
InstrAddrSpace |= InstrAddrSpace |=
toSIAtomicAddrSpace(MMO->getPointerInfo().getAddrSpace()); toSIAtomicAddrSpace(MMO->getPointerInfo().getAddrSpace());
AtomicOrdering OpOrdering = MMO->getOrdering(); AtomicOrdering OpOrdering = MMO->getOrdering();
if (OpOrdering != AtomicOrdering::NotAtomic) { if (OpOrdering != AtomicOrdering::NotAtomic) {
const auto &IsSyncScopeInclusion = const auto &IsSyncScopeInclusion =
MMI->isSyncScopeInclusion(SSID, MMO->getSyncScopeID()); MMI->isSyncScopeInclusion(SSID, MMO->getSyncScopeID());
if (!IsSyncScopeInclusion) { if (!IsSyncScopeInclusion) {
reportUnsupported(MI, reportUnsupported(MI,
Show All 26 Lines std::tie(Scope, OrderingAddrSpace, IsCrossAddressSpaceOrdering) =
ScopeOrNone.getValue(); ScopeOrNone.getValue();
if ((OrderingAddrSpace == SIAtomicAddrSpace::NONE) || if ((OrderingAddrSpace == SIAtomicAddrSpace::NONE) ||
((OrderingAddrSpace & SIAtomicAddrSpace::ATOMIC) != OrderingAddrSpace)) { ((OrderingAddrSpace & SIAtomicAddrSpace::ATOMIC) != OrderingAddrSpace)) {
reportUnsupported(MI, "Unsupported atomic address space"); reportUnsupported(MI, "Unsupported atomic address space");
return None; return None;
} }
} }
return SIMemOpInfo(Ordering, Scope, OrderingAddrSpace, InstrAddrSpace, return SIMemOpInfo(Ordering, Scope, OrderingAddrSpace, InstrAddrSpace,
IsCrossAddressSpaceOrdering, FailureOrdering, IsNonTemporal); IsCrossAddressSpaceOrdering, FailureOrdering, IsVolatile,
IsNonTemporal);
} }
Optional<SIMemOpInfo> SIMemOpAccess::getLoadInfo( Optional<SIMemOpInfo> SIMemOpAccess::getLoadInfo(
const MachineBasicBlock::iterator &MI) const { const MachineBasicBlock::iterator &MI) const {
assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic); assert(MI->getDesc().TSFlags & SIInstrFlags::maybeAtomic);
if (!(MI->mayLoad() && !MI->mayStore())) if (!(MI->mayLoad() && !MI->mayStore()))
return None; return None;
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Linesbool SIGfx6CacheControl::enableLoadCacheBypass(
/// sequentially consistent, and no other thread can access scratch /// sequentially consistent, and no other thread can access scratch
/// memory. /// memory.
/// Other address spaces do not have a cache. /// Other address spaces do not have a cache.
return Changed; return Changed;
} }
bool SIGfx6CacheControl::enableNonTemporal( bool SIGfx6CacheControl::enableVolatileAndOrNonTemporal(
const MachineBasicBlock::iterator &MI) const { MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,
bool IsVolatile, bool IsNonTemporal) const {
// Only handle load and store, not atomic read-modify-write insructions. The
// latter use glc to indicate if the atomic returns a result and so must not
// be used for cache control.
assert(MI->mayLoad() ^ MI->mayStore()); assert(MI->mayLoad() ^ MI->mayStore());
// Only update load and store, not LLVM IR atomic read-modify-write
// instructions. The latter are always marked as volatile so cannot sensibly
// handle it as do not want to pessimize all atomics. Also they do not support
// the nontemporal attribute.
assert( Op == SIMemOp::LOAD || Op == SIMemOp::STORE);
bool Changed = false; bool Changed = false;
/// TODO: Do not enableGLCBit if rmw atomic. if (IsVolatile) {
if (Op == SIMemOp::LOAD)
Changed |= enableGLCBit(MI);
// Ensure operation has completed at system scope to cause all volatile
// operations to be visible outside the program in a global order. Do not
// request cross address space as only the global address space can be
// observable outside the program, so no need to cause a waitcnt for LDS
// address space operations.
Changed |= insertWait(MI, SIAtomicScope::SYSTEM, AddrSpace, Op, false,
Position::AFTER);
return Changed;
}
if (IsNonTemporal) {
// Request L1 MISS_EVICT and L2 STREAM for load and store instructions.
Changed |= enableGLCBit(MI); Changed |= enableGLCBit(MI);
Changed |= enableSLCBit(MI); Changed |= enableSLCBit(MI);
return Changed;
}
return Changed; return Changed;
} }
bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI, bool SIGfx6CacheControl::insertWait(MachineBasicBlock::iterator &MI,
SIAtomicScope Scope, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace, SIAtomicAddrSpace AddrSpace,
SIMemOp Op, SIMemOp Op,
bool IsCrossAddrSpaceOrdering, bool IsCrossAddrSpaceOrdering,
Position Pos) const { Position Pos) const {
bool Changed = false; bool Changed = false;
MachineBasicBlock &MBB = *MI->getParent(); MachineBasicBlock &MBB = *MI->getParent();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
if (Pos == Position::AFTER) if (Pos == Position::AFTER)
++MI; ++MI;
bool VMCnt = false; bool VMCnt = false;
bool LGKMCnt = false; bool LGKMCnt = false;
if ((AddrSpace & SIAtomicAddrSpace::GLOBAL) != SIAtomicAddrSpace::NONE) { if ((AddrSpace & (SIAtomicAddrSpace::GLOBAL | SIAtomicAddrSpace::SCRATCH)) !=
SIAtomicAddrSpace::NONE) {
switch (Scope) { switch (Scope) {
case SIAtomicScope::SYSTEM: case SIAtomicScope::SYSTEM:
case SIAtomicScope::AGENT: case SIAtomicScope::AGENT:
VMCnt |= true; VMCnt |= true;
break; break;
case SIAtomicScope::WORKGROUP: case SIAtomicScope::WORKGROUP:
case SIAtomicScope::WAVEFRONT: case SIAtomicScope::WAVEFRONT:
case SIAtomicScope::SINGLETHREAD: case SIAtomicScope::SINGLETHREAD:
▲ Show 20 Lines • Show All 210 Lines • ▼ Show 20 Linesbool SIGfx10CacheControl::enableLoadCacheBypass(
/// sequentially consistent, and no other thread can access scratch /// sequentially consistent, and no other thread can access scratch
/// memory. /// memory.
/// Other address spaces do not have a cache. /// Other address spaces do not have a cache.
return Changed; return Changed;
} }
bool SIGfx10CacheControl::enableNonTemporal( bool SIGfx10CacheControl::enableVolatileAndOrNonTemporal(
const MachineBasicBlock::iterator &MI) const { MachineBasicBlock::iterator &MI, SIAtomicAddrSpace AddrSpace, SIMemOp Op,
bool IsVolatile, bool IsNonTemporal) const {
// Only handle load and store, not atomic read-modify-write insructions. The
// latter use glc to indicate if the atomic returns a result and so must not
// be used for cache control.
assert(MI->mayLoad() ^ MI->mayStore()); assert(MI->mayLoad() ^ MI->mayStore());
// Only update load and store, not LLVM IR atomic read-modify-write
// instructions. The latter are always marked as volatile so cannot sensibly
// handle it as do not want to pessimize all atomics. Also they do not support
// the nontemporal attribute.
assert( Op == SIMemOp::LOAD || Op == SIMemOp::STORE);
bool Changed = false; bool Changed = false;
if (IsVolatile) {
if (Op == SIMemOp::LOAD) {
Changed |= enableGLCBit(MI);
Changed |= enableDLCBit(MI);
}
// Ensure operation has completed at system scope to cause all volatile
// operations to be visible outside the program in a global order. Do not
// request cross address space as only the global address space can be
// observable outside the program, so no need to cause a waitcnt for LDS
// address space operations.
Changed |= insertWait(MI, SIAtomicScope::SYSTEM, AddrSpace, Op, false,
Position::AFTER);
return Changed;
}
if (IsNonTemporal) {
// Request L0/L1 HIT_EVICT and L2 STREAM for load and store instructions.
Changed |= enableSLCBit(MI); Changed |= enableSLCBit(MI);
/// TODO for store (non-rmw atomic) instructions also enableGLCBit(MI) return Changed;
}
return Changed; return Changed;
} }
bool SIGfx10CacheControl::insertWait(MachineBasicBlock::iterator &MI, bool SIGfx10CacheControl::insertWait(MachineBasicBlock::iterator &MI,
SIAtomicScope Scope, SIAtomicScope Scope,
SIAtomicAddrSpace AddrSpace, SIAtomicAddrSpace AddrSpace,
SIMemOp Op, SIMemOp Op,
bool IsCrossAddrSpaceOrdering, bool IsCrossAddrSpaceOrdering,
Position Pos) const { Position Pos) const {
bool Changed = false; bool Changed = false;
MachineBasicBlock &MBB = *MI->getParent(); MachineBasicBlock &MBB = *MI->getParent();
DebugLoc DL = MI->getDebugLoc(); DebugLoc DL = MI->getDebugLoc();
if (Pos == Position::AFTER) if (Pos == Position::AFTER)
++MI; ++MI;
bool VMCnt = false; bool VMCnt = false;
bool VSCnt = false; bool VSCnt = false;
bool LGKMCnt = false; bool LGKMCnt = false;
if ((AddrSpace & SIAtomicAddrSpace::GLOBAL) != SIAtomicAddrSpace::NONE) { if ((AddrSpace & (SIAtomicAddrSpace::GLOBAL | SIAtomicAddrSpace::SCRATCH)) !=
SIAtomicAddrSpace::NONE) {
switch (Scope) { switch (Scope) {
case SIAtomicScope::SYSTEM: case SIAtomicScope::SYSTEM:
case SIAtomicScope::AGENT: case SIAtomicScope::AGENT:
if ((Op & SIMemOp::LOAD) != SIMemOp::NONE) if ((Op & SIMemOp::LOAD) != SIMemOp::NONE)
VMCnt |= true; VMCnt |= true;
if ((Op & SIMemOp::STORE) != SIMemOp::NONE) if ((Op & SIMemOp::STORE) != SIMemOp::NONE)
VSCnt |= true; VSCnt |= true;
break; break;
▲ Show 20 Lines • Show All 186 Lines • ▼ Show 20 Lines if (MOI.getOrdering() == AtomicOrdering::Acquire ||
Changed |= CC->insertAcquire(MI, MOI.getScope(), Changed |= CC->insertAcquire(MI, MOI.getScope(),
MOI.getOrderingAddrSpace(), MOI.getOrderingAddrSpace(),
Position::AFTER); Position::AFTER);
} }
return Changed; return Changed;
} }
// Atomic instructions do not have the nontemporal attribute. // Atomic instructions already bypass caches to the scope specified by the
if (MOI.isNonTemporal()) { // SyncScope operand. Only non-atomic volatile and nontemporal instructions
Changed |= CC->enableNonTemporal(MI); // need additional treatment.
return Changed; Changed |= CC->enableVolatileAndOrNonTemporal(MI, MOI.getInstrAddrSpace(),
} SIMemOp::LOAD, MOI.isVolatile(),
MOI.isNonTemporal());
return Changed; return Changed;
} }
bool SIMemoryLegalizer::expandStore(const SIMemOpInfo &MOI, bool SIMemoryLegalizer::expandStore(const SIMemOpInfo &MOI,
MachineBasicBlock::iterator &MI) { MachineBasicBlock::iterator &MI) {
assert(!MI->mayLoad() && MI->mayStore()); assert(!MI->mayLoad() && MI->mayStore());
bool Changed = false; bool Changed = false;
if (MOI.isAtomic()) { if (MOI.isAtomic()) {
if (MOI.getOrdering() == AtomicOrdering::Release || if (MOI.getOrdering() == AtomicOrdering::Release ||
MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent) MOI.getOrdering() == AtomicOrdering::SequentiallyConsistent)
Changed |= CC->insertRelease(MI, MOI.getScope(), Changed |= CC->insertRelease(MI, MOI.getScope(),
MOI.getOrderingAddrSpace(), MOI.getOrderingAddrSpace(),
MOI.getIsCrossAddressSpaceOrdering(), MOI.getIsCrossAddressSpaceOrdering(),
Position::BEFORE); Position::BEFORE);
return Changed; return Changed;
} }
// Atomic instructions do not have the nontemporal attribute. // Atomic instructions already bypass caches to the scope specified by the
if (MOI.isNonTemporal()) { // SyncScope operand. Only non-atomic volatile and nontemporal instructions
Changed |= CC->enableNonTemporal(MI); // need additional treatment.
return Changed; Changed |= CC->enableVolatileAndOrNonTemporal(
} MI, MOI.getInstrAddrSpace(), SIMemOp::STORE, MOI.isVolatile(),
MOI.isNonTemporal());
return Changed; return Changed;
} }
bool SIMemoryLegalizer::expandAtomicFence(const SIMemOpInfo &MOI, bool SIMemoryLegalizer::expandAtomicFence(const SIMemOpInfo &MOI,
MachineBasicBlock::iterator &MI) { MachineBasicBlock::iterator &MI) {
assert(MI->getOpcode() == AMDGPU::ATOMIC_FENCE); assert(MI->getOpcode() == AMDGPU::ATOMIC_FENCE);
AtomicPseudoMIs.push_back(MI); AtomicPseudoMIs.push_back(MI);
▲ Show 20 Lines • Show All 125 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_xor_b32 s0, s0, -1 ; GCN-NEXT: s_xor_b32 s0, s0, -1
; GCN-NEXT: s_and_b32 s0, s0, 1 ; GCN-NEXT: s_and_b32 s0, s0, 1
; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_cmp_lg_u32 s0, 0
; GCN-NEXT: s_cbranch_scc1 BB3_2 ; GCN-NEXT: s_cbranch_scc1 BB3_2
; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: ; %bb.1: ; %bb0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: flat_store_dword v[0:1], v0 ; GCN-NEXT: flat_store_dword v[0:1], v0
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: BB3_2: ; %bb1 ; GCN-NEXT: BB3_2: ; %bb1
; GCN-NEXT: v_mov_b32_e32 v0, 1 ; GCN-NEXT: v_mov_b32_e32 v0, 1
; GCN-NEXT: flat_store_dword v[0:1], v0 ; GCN-NEXT: flat_store_dword v[0:1], v0
; GCN-NEXT: s_waitcnt vmcnt(0)
entry: entry:
%trunc = trunc i32 %cond to i1 %trunc = trunc i32 %cond to i1
br i1 %trunc, label %bb0, label %bb1 br i1 %trunc, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
unreachable unreachable
Show All 10 Lines
; GCN-NEXT: s_and_b32 s0, s0, s1 ; GCN-NEXT: s_and_b32 s0, s0, s1
; GCN-NEXT: s_xor_b32 s0, s0, -1 ; GCN-NEXT: s_xor_b32 s0, s0, -1
; GCN-NEXT: s_and_b32 s0, s0, 1 ; GCN-NEXT: s_and_b32 s0, s0, 1
; GCN-NEXT: s_cmp_lg_u32 s0, 0 ; GCN-NEXT: s_cmp_lg_u32 s0, 0
; GCN-NEXT: s_cbranch_scc1 BB4_2 ; GCN-NEXT: s_cbranch_scc1 BB4_2
; GCN-NEXT: ; %bb.1: ; %bb0 ; GCN-NEXT: ; %bb.1: ; %bb0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: flat_store_dword v[0:1], v0 ; GCN-NEXT: flat_store_dword v[0:1], v0
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: BB4_2: ; %bb1 ; GCN-NEXT: BB4_2: ; %bb1
; GCN-NEXT: v_mov_b32_e32 v0, 1 ; GCN-NEXT: v_mov_b32_e32 v0, 1
; GCN-NEXT: flat_store_dword v[0:1], v0 ; GCN-NEXT: flat_store_dword v[0:1], v0
; GCN-NEXT: s_waitcnt vmcnt(0)
entry: entry:
%trunc0 = trunc i32 %cond0 to i1 %trunc0 = trunc i32 %cond0 to i1
%trunc1 = trunc i32 %cond1 to i1 %trunc1 = trunc i32 %cond1 to i1
%and = and i1 %trunc0, %trunc1 %and = and i1 %trunc0, %trunc1
br i1 %and, label %bb0, label %bb1 br i1 %and, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
unreachable unreachable
bb1: bb1:
store volatile i32 1, i32 addrspace(1)* undef store volatile i32 1, i32 addrspace(1)* undef
unreachable unreachable
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -amdgpu-global-isel-risky-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -global-isel -amdgpu-global-isel-risky-select -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s
; Make sure the branch targets are correct after lowering llvm.amdgcn.if ; Make sure the branch targets are correct after lowering llvm.amdgcn.if
define i32 @divergent_if_swap_brtarget_order0(i32 %value) { define i32 @divergent_if_swap_brtarget_order0(i32 %value) {
; CHECK-LABEL: divergent_if_swap_brtarget_order0: ; CHECK-LABEL: divergent_if_swap_brtarget_order0:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: ; implicit-def: $vgpr0 ; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_cbranch_execz BB0_2 ; CHECK-NEXT: s_cbranch_execz BB0_2
; CHECK-NEXT: ; %bb.1: ; %if.true ; CHECK-NEXT: ; %bb.1: ; %if.true
; CHECK-NEXT: global_load_dword v0, v[0:1], off ; CHECK-NEXT: global_load_dword v0, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: BB0_2: ; %endif ; CHECK-NEXT: BB0_2: ; %endif
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%c = icmp ne i32 %value, 0 %c = icmp ne i32 %value, 0
br i1 %c, label %if.true, label %endif br i1 %c, label %if.true, label %endif
Show All 10 Lines
; CHECK-LABEL: divergent_if_swap_brtarget_order1: ; CHECK-LABEL: divergent_if_swap_brtarget_order1:
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: ; implicit-def: $vgpr0 ; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_cbranch_execz BB1_2 ; CHECK-NEXT: s_cbranch_execz BB1_2
; CHECK-NEXT: ; %bb.1: ; %if.true ; CHECK-NEXT: ; %bb.1: ; %if.true
; CHECK-NEXT: global_load_dword v0, v[0:1], off ; CHECK-NEXT: global_load_dword v0, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: BB1_2: ; %endif ; CHECK-NEXT: BB1_2: ; %endif
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%c = icmp ne i32 %value, 0 %c = icmp ne i32 %value, 0
br i1 %c, label %if.true, label %endif br i1 %c, label %if.true, label %endif
Show All 12 Lines
; CHECK: ; %bb.0: ; %entry ; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 ; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: ; implicit-def: $vgpr0 ; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_cbranch_execz BB2_2 ; CHECK-NEXT: s_cbranch_execz BB2_2
; CHECK-NEXT: ; %bb.1: ; %if.true ; CHECK-NEXT: ; %bb.1: ; %if.true
; CHECK-NEXT: global_load_dword v0, v[0:1], off ; CHECK-NEXT: global_load_dword v0, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: BB2_2: ; %endif ; CHECK-NEXT: BB2_2: ; %endif
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%c = trunc i32 %value to i1 %c = trunc i32 %value to i1
br i1 %c, label %if.true, label %endif br i1 %c, label %if.true, label %endif
Show All 14 Lines
; CHECK-NEXT: global_load_dword v0, v[0:1], off ; CHECK-NEXT: global_load_dword v0, v[0:1], off
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 ; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: ; implicit-def: $vgpr0 ; CHECK-NEXT: ; implicit-def: $vgpr0
; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc ; CHECK-NEXT: s_and_saveexec_b64 s[4:5], vcc
; CHECK-NEXT: s_cbranch_execz BB3_2 ; CHECK-NEXT: s_cbranch_execz BB3_2
; CHECK-NEXT: ; %bb.1: ; %if.true ; CHECK-NEXT: ; %bb.1: ; %if.true
; CHECK-NEXT: global_load_dword v0, v[0:1], off ; CHECK-NEXT: global_load_dword v0, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: BB3_2: ; %endif ; CHECK-NEXT: BB3_2: ; %endif
; CHECK-NEXT: s_or_b64 exec, exec, s[4:5] ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: s_setpc_b64 s[30:31] ; CHECK-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%value = load i32, i32 addrspace(1)* %ptr %value = load i32, i32 addrspace(1)* %ptr
%c = trunc i32 %value to i1 %c = trunc i32 %value to i1
br i1 %c, label %if.true, label %endif br i1 %c, label %if.true, label %endif
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Lines
; CHECK-NEXT: BB5_2: ; %bb1 ; CHECK-NEXT: BB5_2: ; %bb1
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: v_add_u32_e32 v1, 1, v1 ; CHECK-NEXT: v_add_u32_e32 v1, 1, v1
; CHECK-NEXT: v_cmp_le_i32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_le_i32_e32 vcc, 0, v1
; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, 1 ; CHECK-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, 1
; CHECK-NEXT: s_cbranch_vccnz BB5_1 ; CHECK-NEXT: s_cbranch_vccnz BB5_1
; CHECK-NEXT: ; %bb.3: ; %bb4 ; CHECK-NEXT: ; %bb.3: ; %bb4
; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1 ; CHECK-NEXT: ; in Loop: Header=BB5_2 Depth=1
; CHECK-NEXT: global_load_dword v2, v[0:1], off ; CHECK-NEXT: global_load_dword v2, v[0:1], off glc
; CHECK-NEXT: s_waitcnt vmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_cmp_ge_i32_e64 s[2:3], v0, v2 ; CHECK-NEXT: v_cmp_ge_i32_e64 s[2:3], v0, v2
; CHECK-NEXT: s_branch BB5_1 ; CHECK-NEXT: s_branch BB5_1
; CHECK-NEXT: BB5_4: ; %bb9 ; CHECK-NEXT: BB5_4: ; %bb9
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
bb: bb:
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%tmp = sub i32 %id, %arg %tmp = sub i32 %id, %arg
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll

Show All 9 Lines
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-NEXT: s_and_b32 s0, s0, 15 ; GFX9-NEXT: s_and_b32 s0, s0, 15
; GFX9-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-NEXT: s_add_u32 s1, 4, s1 ; GFX9-NEXT: s_add_u32 s1, 4, s1
; GFX9-NEXT: scratch_store_dword off, v0, s1 ; GFX9-NEXT: scratch_store_dword off, v0, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, 4, s0 ; GFX9-NEXT: s_add_u32 s0, 4, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_sindex_kernel: ; GFX10-LABEL: store_load_sindex_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s2, s2, s5 ; GFX10-NEXT: s_add_u32 s2, s2, s5
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-NEXT: v_mov_b32_e32 v0, 15
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s1, s0, 15 ; GFX10-NEXT: s_and_b32 s1, s0, 15
; GFX10-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-NEXT: s_add_u32 s0, 4, s0 ; GFX10-NEXT: s_add_u32 s0, 4, s0
; GFX10-NEXT: s_add_u32 s1, 4, s1 ; GFX10-NEXT: s_add_u32 s1, 4, s1
; GFX10-NEXT: scratch_store_dword off, v0, s0 ; GFX10-NEXT: scratch_store_dword off, v0, s0
; GFX10-NEXT: scratch_load_dword v0, off, s1 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
Show All 10 Lines
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 4 ; GFX9-NEXT: v_mov_b32_e32 v2, 4
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: scratch_store_dword v1, v3, off ; GFX9-NEXT: scratch_store_dword v1, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_vindex_kernel: ; GFX10-LABEL: store_load_vindex_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v2, 4 ; GFX10-NEXT: v_mov_b32_e32 v2, 4
; GFX10-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT: scratch_store_dword v0, v3, off ; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i2 = tail call i32 @llvm.amdgcn.workitem.id.x() %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()
%i3 = zext i32 %i2 to i64 %i3 = zext i32 %i2 to i64
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
Show All 11 Lines
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX9-NEXT: v_and_b32_e32 v0, 15, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 15, v0
; GFX9-NEXT: v_mov_b32_e32 v2, s32 ; GFX9-NEXT: v_mov_b32_e32 v2, s32
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: scratch_store_dword v1, v3, off ; GFX9-NEXT: scratch_store_dword v1, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off ; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_vindex_foo: ; GFX10-LABEL: store_load_vindex_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v1, 15, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 15, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v2, s32 ; GFX10-NEXT: v_mov_b32_e32 v2, s32
; GFX10-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT: scratch_store_dword v0, v3, off ; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: scratch_load_dword v0, v1, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
Show All 33 Lines
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-NEXT: s_add_u32 s2, 4, 0 ; GFX9-NEXT: s_add_u32 s2, 4, 0
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-NEXT: s_and_b32 s0, s0, 15 ; GFX9-NEXT: s_and_b32 s0, s0, 15
; GFX9-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-NEXT: s_add_u32 s1, 0x104, s1 ; GFX9-NEXT: s_add_u32 s1, 0x104, s1
; GFX9-NEXT: scratch_load_dword v1, off, s2 ; GFX9-NEXT: scratch_load_dword v1, off, s2 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_store_dword off, v0, s1 ; GFX9-NEXT: scratch_store_dword off, v0, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, 0x104, s0 ; GFX9-NEXT: s_add_u32 s0, 0x104, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_sindex_small_offset_kernel: ; GFX10-LABEL: store_load_sindex_small_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s2, s2, s5 ; GFX10-NEXT: s_add_u32 s2, s2, s5
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-NEXT: s_add_u32 s1, 4, 0 ; GFX10-NEXT: s_add_u32 s1, 4, 0
; GFX10-NEXT: scratch_load_dword v0, off, s1 ; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-NEXT: v_mov_b32_e32 v0, 15
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s1, s0, 15 ; GFX10-NEXT: s_and_b32 s1, s0, 15
; GFX10-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-NEXT: s_add_u32 s0, 0x104, s0 ; GFX10-NEXT: s_add_u32 s0, 0x104, s0
; GFX10-NEXT: s_add_u32 s1, 0x104, s1 ; GFX10-NEXT: s_add_u32 s1, 0x104, s1
; GFX10-NEXT: scratch_store_dword off, v0, s0 ; GFX10-NEXT: scratch_store_dword off, v0, s0
; GFX10-NEXT: scratch_load_dword v0, off, s1 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%padding = alloca [64 x i32], align 4, addrspace(5) %padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define amdgpu_kernel void @store_load_vindex_small_offset_kernel() { define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX9-LABEL: store_load_vindex_small_offset_kernel: ; GFX9-LABEL: store_load_vindex_small_offset_kernel:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_add_u32 s0, 4, 0 ; GFX9-NEXT: s_add_u32 s0, 4, 0
; GFX9-NEXT: scratch_load_dword v1, off, s0 ; GFX9-NEXT: scratch_load_dword v1, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x104 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x104
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: scratch_store_dword v1, v3, off ; GFX9-NEXT: scratch_store_dword v1, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_vindex_small_offset_kernel: ; GFX10-LABEL: store_load_vindex_small_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v2, 0x104 ; GFX10-NEXT: v_mov_b32_e32 v2, 0x104
; GFX10-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: s_add_u32 s0, 4, 0 ; GFX10-NEXT: s_add_u32 s0, 4, 0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT: scratch_load_dword v2, off, s0 ; GFX10-NEXT: scratch_load_dword v2, off, s0 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: scratch_store_dword v0, v3, off ; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%padding = alloca [64 x i32], align 4, addrspace(5) %padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i2 = tail call i32 @llvm.amdgcn.workitem.id.x() %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()
%i3 = zext i32 %i2 to i64 %i3 = zext i32 %i2 to i64
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = sub nsw i32 31, %i2 %i9 = sub nsw i32 31, %i2
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define void @store_load_vindex_small_offset_foo(i32 %idx) { define void @store_load_vindex_small_offset_foo(i32 %idx) {
; GFX9-LABEL: store_load_vindex_small_offset_foo: ; GFX9-LABEL: store_load_vindex_small_offset_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_add_u32 s0, s32, 0 ; GFX9-NEXT: s_add_u32 s0, s32, 0
; GFX9-NEXT: scratch_load_dword v1, off, s0 ; GFX9-NEXT: scratch_load_dword v1, off, s0 glc
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x100
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x100
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX9-NEXT: v_and_b32_e32 v0, 15, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 15, v0
; GFX9-NEXT: v_mov_b32_e32 v2, vcc_hi ; GFX9-NEXT: v_mov_b32_e32 v2, vcc_hi
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: scratch_store_dword v1, v3, off ; GFX9-NEXT: scratch_store_dword v1, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off ; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_vindex_small_offset_foo: ; GFX10-LABEL: store_load_vindex_small_offset_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v1, 15, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 15, v0
; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x100 ; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x100
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT: s_add_u32 s0, s32, 0 ; GFX10-NEXT: s_add_u32 s0, s32, 0
; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT: scratch_load_dword v2, off, s0 ; GFX10-NEXT: scratch_load_dword v2, off, s0 glc dlc
; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: scratch_load_dword v0, v1, off
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%padding = alloca [64 x i32], align 4, addrspace(5) %padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
Show All 14 Lines
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-NEXT: s_add_u32 s2, 4, 0 ; GFX9-NEXT: s_add_u32 s2, 4, 0
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-NEXT: s_and_b32 s0, s0, 15 ; GFX9-NEXT: s_and_b32 s0, s0, 15
; GFX9-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-NEXT: s_add_u32 s1, 0x4004, s1 ; GFX9-NEXT: s_add_u32 s1, 0x4004, s1
; GFX9-NEXT: scratch_load_dword v1, off, s2 ; GFX9-NEXT: scratch_load_dword v1, off, s2 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_store_dword off, v0, s1 ; GFX9-NEXT: scratch_store_dword off, v0, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX9-NEXT: s_add_u32 s0, 0x4004, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_sindex_large_offset_kernel: ; GFX10-LABEL: store_load_sindex_large_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s2, s2, s5 ; GFX10-NEXT: s_add_u32 s2, s2, s5
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-NEXT: s_add_u32 s1, 4, 0 ; GFX10-NEXT: s_add_u32 s1, 4, 0
; GFX10-NEXT: scratch_load_dword v0, off, s1 ; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-NEXT: v_mov_b32_e32 v0, 15
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s1, s0, 15 ; GFX10-NEXT: s_and_b32 s1, s0, 15
; GFX10-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX10-NEXT: s_add_u32 s0, 0x4004, s0
; GFX10-NEXT: s_add_u32 s1, 0x4004, s1 ; GFX10-NEXT: s_add_u32 s1, 0x4004, s1
; GFX10-NEXT: scratch_store_dword off, v0, s0 ; GFX10-NEXT: scratch_store_dword off, v0, s0
; GFX10-NEXT: scratch_load_dword v0, off, s1 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%padding = alloca [4096 x i32], align 4, addrspace(5) %padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define amdgpu_kernel void @store_load_vindex_large_offset_kernel() { define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX9-LABEL: store_load_vindex_large_offset_kernel: ; GFX9-LABEL: store_load_vindex_large_offset_kernel:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_add_u32 s0, 4, 0 ; GFX9-NEXT: s_add_u32 s0, 4, 0
; GFX9-NEXT: scratch_load_dword v1, off, s0 ; GFX9-NEXT: scratch_load_dword v1, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT: v_mov_b32_e32 v2, 0x4004 ; GFX9-NEXT: v_mov_b32_e32 v2, 0x4004
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: scratch_store_dword v1, v3, off ; GFX9-NEXT: scratch_store_dword v1, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_vindex_large_offset_kernel: ; GFX10-LABEL: store_load_vindex_large_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v1, 0, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v2, 0x4004 ; GFX10-NEXT: v_mov_b32_e32 v2, 0x4004
; GFX10-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: s_add_u32 s0, 4, 0 ; GFX10-NEXT: s_add_u32 s0, 4, 0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT: scratch_load_dword v2, off, s0 ; GFX10-NEXT: scratch_load_dword v2, off, s0 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: scratch_store_dword v0, v3, off ; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v1, off offset:124 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%padding = alloca [4096 x i32], align 4, addrspace(5) %padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i2 = tail call i32 @llvm.amdgcn.workitem.id.x() %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()
%i3 = zext i32 %i2 to i64 %i3 = zext i32 %i2 to i64
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = sub nsw i32 31, %i2 %i9 = sub nsw i32 31, %i2
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define void @store_load_vindex_large_offset_foo(i32 %idx) { define void @store_load_vindex_large_offset_foo(i32 %idx) {
; GFX9-LABEL: store_load_vindex_large_offset_foo: ; GFX9-LABEL: store_load_vindex_large_offset_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_add_u32 s0, s32, 0 ; GFX9-NEXT: s_add_u32 s0, s32, 0
; GFX9-NEXT: scratch_load_dword v1, off, s0 ; GFX9-NEXT: scratch_load_dword v1, off, s0 glc
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX9-NEXT: v_and_b32_e32 v0, 15, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 15, v0
; GFX9-NEXT: v_mov_b32_e32 v2, vcc_hi ; GFX9-NEXT: v_mov_b32_e32 v2, vcc_hi
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_add_u32_e32 v1, v2, v1 ; GFX9-NEXT: v_add_u32_e32 v1, v2, v1
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: scratch_store_dword v1, v3, off ; GFX9-NEXT: scratch_store_dword v1, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, v2, v0 ; GFX9-NEXT: v_add_u32_e32 v0, v2, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off ; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_vindex_large_offset_foo: ; GFX10-LABEL: store_load_vindex_large_offset_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_and_b32_e32 v1, 15, v0 ; GFX10-NEXT: v_and_b32_e32 v1, 15, v0
; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo
; GFX10-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1 ; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v1
; GFX10-NEXT: s_add_u32 s0, s32, 0 ; GFX10-NEXT: s_add_u32 s0, s32, 0
; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v2, v0
; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v2, v1
; GFX10-NEXT: scratch_load_dword v2, off, s0 ; GFX10-NEXT: scratch_load_dword v2, off, s0 glc dlc
; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: scratch_load_dword v0, v1, off
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: scratch_store_dword v0, v3, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v1, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%padding = alloca [4096 x i32], align 4, addrspace(5) %padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
Show All 9 Lines
define amdgpu_kernel void @store_load_large_imm_offset_kernel() { define amdgpu_kernel void @store_load_large_imm_offset_kernel() {
; GFX9-LABEL: store_load_large_imm_offset_kernel: ; GFX9-LABEL: store_load_large_imm_offset_kernel:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: v_mov_b32_e32 v0, 13
; GFX9-NEXT: s_add_u32 s0, 4, 0 ; GFX9-NEXT: s_add_u32 s0, 4, 0
; GFX9-NEXT: scratch_store_dword off, v0, s0 ; GFX9-NEXT: scratch_store_dword off, v0, s0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_movk_i32 s0, 0x3e80 ; GFX9-NEXT: s_movk_i32 s0, 0x3e80
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: s_add_u32 s0, 4, s0 ; GFX9-NEXT: s_add_u32 s0, 4, s0
; GFX9-NEXT: scratch_store_dword off, v0, s0 ; GFX9-NEXT: scratch_store_dword off, v0, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_large_imm_offset_kernel: ; GFX10-LABEL: store_load_large_imm_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_mov_b32_e32 v0, 13 ; GFX10-NEXT: v_mov_b32_e32 v0, 13
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: s_movk_i32 s0, 0x3e80 ; GFX10-NEXT: s_movk_i32 s0, 0x3e80
; GFX10-NEXT: s_add_u32 s1, 4, 0 ; GFX10-NEXT: s_add_u32 s1, 4, 0
; GFX10-NEXT: s_add_u32 s0, 4, s0 ; GFX10-NEXT: s_add_u32 s0, 4, s0
; GFX10-NEXT: scratch_store_dword off, v0, s1 ; GFX10-NEXT: scratch_store_dword off, v0, s1
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_store_dword off, v1, s0 ; GFX10-NEXT: scratch_store_dword off, v1, s0
; GFX10-NEXT: scratch_load_dword v0, off, s0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s0 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%i = alloca [4096 x i32], align 4, addrspace(5) %i = alloca [4096 x i32], align 4, addrspace(5)
%i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef %i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef
store volatile i32 13, i32 addrspace(5)* %i1, align 4 store volatile i32 13, i32 addrspace(5)* %i1, align 4
%i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 %i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
store volatile i32 15, i32 addrspace(5)* %i7, align 4 store volatile i32 15, i32 addrspace(5)* %i7, align 4
%i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 %i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
%i12 = load volatile i32, i32 addrspace(5)* %i10, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i10, align 4
ret void ret void
} }
define void @store_load_large_imm_offset_foo() { define void @store_load_large_imm_offset_foo() {
; GFX9-LABEL: store_load_large_imm_offset_foo: ; GFX9-LABEL: store_load_large_imm_offset_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: v_mov_b32_e32 v0, 13
; GFX9-NEXT: s_add_u32 s0, s32, 0 ; GFX9-NEXT: s_add_u32 s0, s32, 0
; GFX9-NEXT: scratch_store_dword off, v0, s0 ; GFX9-NEXT: scratch_store_dword off, v0, s0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_movk_i32 s0, 0x3e80 ; GFX9-NEXT: s_movk_i32 s0, 0x3e80
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: s_add_u32 s0, s32, s0 ; GFX9-NEXT: s_add_u32 s0, s32, s0
; GFX9-NEXT: scratch_store_dword off, v0, s0 ; GFX9-NEXT: scratch_store_dword off, v0, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_large_imm_offset_foo: ; GFX10-LABEL: store_load_large_imm_offset_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v0, 13 ; GFX10-NEXT: v_mov_b32_e32 v0, 13
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: s_movk_i32 s0, 0x3e80 ; GFX10-NEXT: s_movk_i32 s0, 0x3e80
; GFX10-NEXT: s_add_u32 s1, s32, 0 ; GFX10-NEXT: s_add_u32 s1, s32, 0
; GFX10-NEXT: s_add_u32 s0, s32, s0 ; GFX10-NEXT: s_add_u32 s0, s32, s0
; GFX10-NEXT: scratch_store_dword off, v0, s1 ; GFX10-NEXT: scratch_store_dword off, v0, s1
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_store_dword off, v1, s0 ; GFX10-NEXT: scratch_store_dword off, v1, s0
; GFX10-NEXT: scratch_load_dword v0, off, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s0 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%i = alloca [4096 x i32], align 4, addrspace(5) %i = alloca [4096 x i32], align 4, addrspace(5)
%i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef %i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef
store volatile i32 13, i32 addrspace(5)* %i1, align 4 store volatile i32 13, i32 addrspace(5)* %i1, align 4
%i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 %i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
store volatile i32 15, i32 addrspace(5)* %i7, align 4 store volatile i32 15, i32 addrspace(5)* %i7, align 4
%i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 %i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
%i12 = load volatile i32, i32 addrspace(5)* %i10, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i10, align 4
ret void ret void
} }
define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) { define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX9-LABEL: store_load_vidx_sidx_offset: ; GFX9-LABEL: store_load_vidx_sidx_offset:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 15 ; GFX9-NEXT: v_mov_b32_e32 v1, 15
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_add_lshl_u32 v0, s0, v0, 2 ; GFX9-NEXT: v_add_lshl_u32 v0, s0, v0, 2
; GFX9-NEXT: v_add_u32_e32 v0, 4, v0 ; GFX9-NEXT: v_add_u32_e32 v0, 4, v0
; GFX9-NEXT: scratch_store_dword v0, v1, off offset:1024 ; GFX9-NEXT: scratch_store_dword v0, v1, off offset:1024
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:1024 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:1024 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_vidx_sidx_offset: ; GFX10-LABEL: store_load_vidx_sidx_offset:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s2, s2, s5 ; GFX10-NEXT: s_add_u32 s2, s2, s5
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_add_lshl_u32 v0, s0, v0, 2 ; GFX10-NEXT: v_add_lshl_u32 v0, s0, v0, 2
; GFX10-NEXT: v_add_nc_u32_e32 v0, 4, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, 4, v0
; GFX10-NEXT: scratch_store_dword v0, v1, off offset:1024 ; GFX10-NEXT: scratch_store_dword v0, v1, off offset:1024
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:1024 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:1024 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%alloca = alloca [32 x i32], align 4, addrspace(5) %alloca = alloca [32 x i32], align 4, addrspace(5)
%vidx = tail call i32 @llvm.amdgcn.workitem.id.x() %vidx = tail call i32 @llvm.amdgcn.workitem.id.x()
%add1 = add nsw i32 %sidx, %vidx %add1 = add nsw i32 %sidx, %vidx
%add2 = add nsw i32 %add1, 256 %add2 = add nsw i32 %add1, 256
%gep = getelementptr inbounds [32 x i32], [32 x i32] addrspace(5)* %alloca, i32 0, i32 %add2 %gep = getelementptr inbounds [32 x i32], [32 x i32] addrspace(5)* %alloca, i32 0, i32 %add2
store volatile i32 15, i32 addrspace(5)* %gep, align 4 store volatile i32 15, i32 addrspace(5)* %gep, align 4
%load = load volatile i32, i32 addrspace(5)* %gep, align 4 %load = load volatile i32, i32 addrspace(5)* %gep, align 4
ret void ret void
} }
define void @store_load_i64_aligned(i64 addrspace(5)* nocapture %arg) { define void @store_load_i64_aligned(i64 addrspace(5)* nocapture %arg) {
; GFX9-LABEL: store_load_i64_aligned: ; GFX9-LABEL: store_load_i64_aligned:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, 15 ; GFX9-NEXT: v_mov_b32_e32 v1, 15
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_i64_aligned: ; GFX10-LABEL: store_load_i64_aligned:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
bb: bb:
store volatile i64 15, i64 addrspace(5)* %arg, align 8 store volatile i64 15, i64 addrspace(5)* %arg, align 8
%load = load volatile i64, i64 addrspace(5)* %arg, align 8 %load = load volatile i64, i64 addrspace(5)* %arg, align 8
ret void ret void
} }
define void @store_load_i64_unaligned(i64 addrspace(5)* nocapture %arg) { define void @store_load_i64_unaligned(i64 addrspace(5)* nocapture %arg) {
; GFX9-LABEL: store_load_i64_unaligned: ; GFX9-LABEL: store_load_i64_unaligned:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, 15 ; GFX9-NEXT: v_mov_b32_e32 v1, 15
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_i64_unaligned: ; GFX10-LABEL: store_load_i64_unaligned:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
bb: bb:
store volatile i64 15, i64 addrspace(5)* %arg, align 1 store volatile i64 15, i64 addrspace(5)* %arg, align 1
%load = load volatile i64, i64 addrspace(5)* %arg, align 1 %load = load volatile i64, i64 addrspace(5)* %arg, align 1
ret void ret void
} }
define void @store_load_v3i32_unaligned(<3 x i32> addrspace(5)* nocapture %arg) { define void @store_load_v3i32_unaligned(<3 x i32> addrspace(5)* nocapture %arg) {
; GFX9-LABEL: store_load_v3i32_unaligned: ; GFX9-LABEL: store_load_v3i32_unaligned:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s2, 3 ; GFX9-NEXT: s_mov_b32 s2, 3
; GFX9-NEXT: s_mov_b32 s1, 2 ; GFX9-NEXT: s_mov_b32 s1, 2
; GFX9-NEXT: s_mov_b32 s0, 1 ; GFX9-NEXT: s_mov_b32 s0, 1
; GFX9-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_mov_b32_e32 v2, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: scratch_store_dwordx3 v0, v[1:3], off ; GFX9-NEXT: scratch_store_dwordx3 v0, v[1:3], off
; GFX9-NEXT: scratch_load_dwordx3 v[0:2], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dwordx3 v[0:2], v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_v3i32_unaligned: ; GFX10-LABEL: store_load_v3i32_unaligned:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s2, 3 ; GFX10-NEXT: s_mov_b32 s2, 3
; GFX10-NEXT: s_mov_b32 s1, 2 ; GFX10-NEXT: s_mov_b32 s1, 2
; GFX10-NEXT: s_mov_b32 s0, 1 ; GFX10-NEXT: s_mov_b32 s0, 1
; GFX10-NEXT: v_mov_b32_e32 v3, s2 ; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s1 ; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s0 ; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: scratch_store_dwordx3 v0, v[1:3], off ; GFX10-NEXT: scratch_store_dwordx3 v0, v[1:3], off
; GFX10-NEXT: scratch_load_dwordx3 v[0:2], v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dwordx3 v[0:2], v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
bb: bb:
store volatile <3 x i32> <i32 1, i32 2, i32 3>, <3 x i32> addrspace(5)* %arg, align 1 store volatile <3 x i32> <i32 1, i32 2, i32 3>, <3 x i32> addrspace(5)* %arg, align 1
%load = load volatile <3 x i32>, <3 x i32> addrspace(5)* %arg, align 1 %load = load volatile <3 x i32>, <3 x i32> addrspace(5)* %arg, align 1
ret void ret void
} }
define void @store_load_v4i32_unaligned(<4 x i32> addrspace(5)* nocapture %arg) { define void @store_load_v4i32_unaligned(<4 x i32> addrspace(5)* nocapture %arg) {
; GFX9-LABEL: store_load_v4i32_unaligned: ; GFX9-LABEL: store_load_v4i32_unaligned:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s3, 4 ; GFX9-NEXT: s_mov_b32 s3, 4
; GFX9-NEXT: s_mov_b32 s2, 3 ; GFX9-NEXT: s_mov_b32 s2, 3
; GFX9-NEXT: s_mov_b32 s1, 2 ; GFX9-NEXT: s_mov_b32 s1, 2
; GFX9-NEXT: s_mov_b32 s0, 1 ; GFX9-NEXT: s_mov_b32 s0, 1
; GFX9-NEXT: v_mov_b32_e32 v4, s3 ; GFX9-NEXT: v_mov_b32_e32 v4, s3
; GFX9-NEXT: v_mov_b32_e32 v3, s2 ; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: v_mov_b32_e32 v2, s1 ; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: scratch_store_dwordx4 v0, v[1:4], off ; GFX9-NEXT: scratch_store_dwordx4 v0, v[1:4], off
; GFX9-NEXT: scratch_load_dwordx4 v[0:3], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dwordx4 v[0:3], v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_v4i32_unaligned: ; GFX10-LABEL: store_load_v4i32_unaligned:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s3, 4 ; GFX10-NEXT: s_mov_b32 s3, 4
; GFX10-NEXT: s_mov_b32 s2, 3 ; GFX10-NEXT: s_mov_b32 s2, 3
; GFX10-NEXT: s_mov_b32 s1, 2 ; GFX10-NEXT: s_mov_b32 s1, 2
; GFX10-NEXT: s_mov_b32 s0, 1 ; GFX10-NEXT: s_mov_b32 s0, 1
; GFX10-NEXT: v_mov_b32_e32 v4, s3 ; GFX10-NEXT: v_mov_b32_e32 v4, s3
; GFX10-NEXT: v_mov_b32_e32 v3, s2 ; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s1 ; GFX10-NEXT: v_mov_b32_e32 v2, s1
; GFX10-NEXT: v_mov_b32_e32 v1, s0 ; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: scratch_store_dwordx4 v0, v[1:4], off ; GFX10-NEXT: scratch_store_dwordx4 v0, v[1:4], off
; GFX10-NEXT: scratch_load_dwordx4 v[0:3], v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dwordx4 v[0:3], v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
bb: bb:
store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %arg, align 1 store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %arg, align 1
%load = load volatile <4 x i32>, <4 x i32> addrspace(5)* %arg, align 1 %load = load volatile <4 x i32>, <4 x i32> addrspace(5)* %arg, align 1
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()

llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s ; RUN: llc -global-isel -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=SI %s
; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VI %s ; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=VI %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
define amdgpu_kernel void @v_test_global_nnans_med3_f32_pat0_srcmod0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #2 { define amdgpu_kernel void @v_test_global_nnans_med3_f32_pat0_srcmod0(float addrspace(1)* %out, float addrspace(1)* %aptr, float addrspace(1)* %bptr, float addrspace(1)* %cptr) #2 {
; SI-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod0: ; SI-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod0:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b32 s10, 0 ; SI-NEXT: s_mov_b32 s10, 0
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[2:3] ; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[4:5] ; SI-NEXT: s_mov_b64 s[8:9], s[4:5]
; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[6:7] ; SI-NEXT: s_mov_b64 s[8:9], s[6:7]
; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_sub_f32_e32 v2, 0x80000000, v2
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_sub_f32_e32 v2, 0x80000000, v2
; SI-NEXT: v_med3_f32 v2, v2, v3, v4 ; SI-NEXT: v_med3_f32 v2, v2, v3, v4
; SI-NEXT: s_mov_b64 s[2:3], s[10:11] ; SI-NEXT: s_mov_b64 s[2:3], s[10:11]
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod0: ; VI-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod0:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v8, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v8, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v8 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v8
; VI-NEXT: v_mov_b32_e32 v2, s4 ; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v8 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v8
; VI-NEXT: v_mov_b32_e32 v4, s6 ; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_mov_b32_e32 v5, s7 ; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v8 ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v8
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v2, v[4:5] ; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v2, v[4:5] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v7, s1 ; VI-NEXT: v_mov_b32_e32 v7, s1
; VI-NEXT: v_mov_b32_e32 v6, s0 ; VI-NEXT: v_mov_b32_e32 v6, s0
; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v8 ; VI-NEXT: v_add_u32_e32 v6, vcc, v6, v8
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc ; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v7, vcc
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_sub_f32_e32 v0, 0x80000000, v0 ; VI-NEXT: v_sub_f32_e32 v0, 0x80000000, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_med3_f32 v0, v0, v1, v2 ; VI-NEXT: v_med3_f32 v0, v0, v1, v2
; VI-NEXT: flat_store_dword v[6:7], v0 ; VI-NEXT: flat_store_dword v[6:7], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod0: ; GFX9-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: global_load_dword v2, v0, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] ; GFX9-NEXT: global_load_dword v2, v0, s[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_sub_f32_e32 v1, 0x80000000, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_f32_e32 v1, 0x80000000, v1
; GFX9-NEXT: v_med3_f32 v1, v1, v2, v3 ; GFX9-NEXT: v_med3_f32 v1, v1, v2, v3
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr float, float addrspace(1)* %bptr, i32 %tid %gep1 = getelementptr float, float addrspace(1)* %bptr, i32 %tid
%gep2 = getelementptr float, float addrspace(1)* %cptr, i32 %tid %gep2 = getelementptr float, float addrspace(1)* %cptr, i32 %tid
%outgep = getelementptr float, float addrspace(1)* %out, i32 %tid %outgep = getelementptr float, float addrspace(1)* %out, i32 %tid
Show All 14 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b32 s10, 0 ; SI-NEXT: s_mov_b32 s10, 0
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[2:3] ; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[4:5] ; SI-NEXT: s_mov_b64 s[8:9], s[4:5]
; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[6:7] ; SI-NEXT: s_mov_b64 s[8:9], s[6:7]
; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_sub_f32_e32 v2, 0x80000000, v2 ; SI-NEXT: v_sub_f32_e32 v2, 0x80000000, v2
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3 ; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
; SI-NEXT: v_min_f32_e32 v5, v2, v3 ; SI-NEXT: v_min_f32_e32 v5, v2, v3
; SI-NEXT: v_max_f32_e32 v2, v2, v3 ; SI-NEXT: v_max_f32_e32 v2, v2, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4 ; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_min_f32_e32 v2, v2, v3 ; SI-NEXT: v_min_f32_e32 v2, v2, v3
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5 ; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_max_f32_e32 v2, v3, v2 ; SI-NEXT: v_max_f32_e32 v2, v3, v2
; SI-NEXT: s_mov_b64 s[2:3], s[10:11] ; SI-NEXT: s_mov_b64 s[2:3], s[10:11]
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
Show All 11 Lines
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; VI-NEXT: v_mov_b32_e32 v4, s6 ; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_mov_b32_e32 v5, s7 ; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: flat_load_dword v7, v[0:1] ; VI-NEXT: flat_load_dword v7, v[0:1] glc
; VI-NEXT: flat_load_dword v2, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] ; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_sub_f32_e32 v4, 0x80000000, v7 ; VI-NEXT: v_sub_f32_e32 v4, 0x80000000, v7
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; VI-NEXT: v_mul_f32_e32 v4, 1.0, v4 ; VI-NEXT: v_mul_f32_e32 v4, 1.0, v4
; VI-NEXT: v_min_f32_e32 v5, v4, v2 ; VI-NEXT: v_min_f32_e32 v5, v4, v2
; VI-NEXT: v_max_f32_e32 v2, v4, v2 ; VI-NEXT: v_max_f32_e32 v2, v4, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mul_f32_e32 v3, 1.0, v3 ; VI-NEXT: v_mul_f32_e32 v3, 1.0, v3
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; VI-NEXT: v_min_f32_e32 v2, v2, v3 ; VI-NEXT: v_min_f32_e32 v2, v2, v3
; VI-NEXT: v_mul_f32_e32 v3, 1.0, v5 ; VI-NEXT: v_mul_f32_e32 v3, 1.0, v5
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; VI-NEXT: v_max_f32_e32 v2, v3, v2 ; VI-NEXT: v_max_f32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_no_global_nnans_med3_f32_pat0_srcmod0: ; GFX9-LABEL: v_test_no_global_nnans_med3_f32_pat0_srcmod0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: global_load_dword v2, v0, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] ; GFX9-NEXT: global_load_dword v2, v0, s[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_f32_e32 v1, 0x80000000, v1 ; GFX9-NEXT: v_sub_f32_e32 v1, 0x80000000, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_max_f32_e32 v2, v2, v2 ; GFX9-NEXT: v_max_f32_e32 v2, v2, v2
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
; GFX9-NEXT: v_min_f32_e32 v4, v1, v2 ; GFX9-NEXT: v_min_f32_e32 v4, v1, v2
; GFX9-NEXT: v_max_f32_e32 v1, v1, v2 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f32_e32 v3, v3, v3 ; GFX9-NEXT: v_max_f32_e32 v3, v3, v3
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
; GFX9-NEXT: v_min_f32_e32 v1, v1, v3 ; GFX9-NEXT: v_min_f32_e32 v1, v1, v3
; GFX9-NEXT: v_max_f32_e32 v2, v4, v4 ; GFX9-NEXT: v_max_f32_e32 v2, v4, v4
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
; GFX9-NEXT: v_max_f32_e32 v1, v2, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v2, v1
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
Show All 19 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b32 s10, 0 ; SI-NEXT: s_mov_b32 s10, 0
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[2:3] ; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[4:5] ; SI-NEXT: s_mov_b64 s[8:9], s[4:5]
; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[6:7] ; SI-NEXT: s_mov_b64 s[8:9], s[6:7]
; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s2, 0x80000000 ; SI-NEXT: s_mov_b32 s2, 0x80000000
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_sub_f32_e32 v2, s2, v2 ; SI-NEXT: v_sub_f32_e32 v2, s2, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_sub_f32_e64 v4, s2, |v4| ; SI-NEXT: v_sub_f32_e64 v4, s2, |v4|
; SI-NEXT: v_med3_f32 v2, v2, |v3|, v4 ; SI-NEXT: v_med3_f32 v2, v2, |v3|, v4
; SI-NEXT: s_mov_b64 s[2:3], s[10:11] ; SI-NEXT: s_mov_b64 s[2:3], s[10:11]
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod012: ; VI-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod012:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6
; VI-NEXT: v_mov_b32_e32 v2, s4 ; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; VI-NEXT: v_mov_b32_e32 v4, s6 ; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_mov_b32_e32 v5, s7 ; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: flat_load_dword v7, v[0:1] ; VI-NEXT: flat_load_dword v7, v[0:1] glc
; VI-NEXT: flat_load_dword v2, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] ; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: s_mov_b32 s2, 0x80000000 ; VI-NEXT: s_mov_b32 s2, 0x80000000
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_sub_f32_e32 v4, s2, v7 ; VI-NEXT: v_sub_f32_e32 v4, s2, v7
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_sub_f32_e64 v3, s2, |v3| ; VI-NEXT: v_sub_f32_e64 v3, s2, |v3|
; VI-NEXT: v_med3_f32 v2, v4, |v2|, v3 ; VI-NEXT: v_med3_f32 v2, v4, |v2|, v3
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod012: ; GFX9-LABEL: v_test_global_nnans_med3_f32_pat0_srcmod012:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: global_load_dword v2, v0, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] ; GFX9-NEXT: global_load_dword v2, v0, s[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s2, 0x80000000 ; GFX9-NEXT: s_mov_b32 s2, 0x80000000
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_sub_f32_e32 v1, s2, v1 ; GFX9-NEXT: v_sub_f32_e32 v1, s2, v1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_f32_e64 v3, s2, |v3| ; GFX9-NEXT: v_sub_f32_e64 v3, s2, |v3|
; GFX9-NEXT: v_med3_f32 v1, v1, |v2|, v3 ; GFX9-NEXT: v_med3_f32 v1, v1, |v2|, v3
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr float, float addrspace(1)* %bptr, i32 %tid %gep1 = getelementptr float, float addrspace(1)* %bptr, i32 %tid
%gep2 = getelementptr float, float addrspace(1)* %cptr, i32 %tid %gep2 = getelementptr float, float addrspace(1)* %cptr, i32 %tid
Show All 21 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b32 s10, 0 ; SI-NEXT: s_mov_b32 s10, 0
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[2:3] ; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[4:5] ; SI-NEXT: s_mov_b64 s[8:9], s[4:5]
; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[6:7] ; SI-NEXT: s_mov_b64 s[8:9], s[6:7]
; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s2, 0x80000000 ; SI-NEXT: s_mov_b32 s2, 0x80000000
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_sub_f32_e64 v2, s2, |v2| ; SI-NEXT: v_sub_f32_e64 v2, s2, |v2|
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_sub_f32_e64 v3, s2, |v3| ; SI-NEXT: v_sub_f32_e64 v3, s2, |v3|
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_sub_f32_e64 v4, s2, |v4| ; SI-NEXT: v_sub_f32_e64 v4, s2, |v4|
; SI-NEXT: v_med3_f32 v2, v2, v3, v4 ; SI-NEXT: v_med3_f32 v2, v2, v3, v4
; SI-NEXT: s_mov_b64 s[2:3], s[10:11] ; SI-NEXT: s_mov_b64 s[2:3], s[10:11]
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_global_nnans_med3_f32_pat0_negabs012: ; VI-LABEL: v_test_global_nnans_med3_f32_pat0_negabs012:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v6, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6
; VI-NEXT: v_mov_b32_e32 v2, s4 ; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; VI-NEXT: v_mov_b32_e32 v4, s6 ; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_mov_b32_e32 v5, s7 ; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: flat_load_dword v7, v[0:1] ; VI-NEXT: flat_load_dword v7, v[0:1] glc
; VI-NEXT: flat_load_dword v2, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] ; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s2, 0x80000000 ; VI-NEXT: s_mov_b32 s2, 0x80000000
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_sub_f32_e64 v4, s2, |v7| ; VI-NEXT: v_sub_f32_e64 v4, s2, |v7|
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_sub_f32_e64 v2, s2, |v2| ; VI-NEXT: v_sub_f32_e64 v2, s2, |v2|
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_sub_f32_e64 v3, s2, |v3| ; VI-NEXT: v_sub_f32_e64 v3, s2, |v3|
; VI-NEXT: v_med3_f32 v2, v4, v2, v3 ; VI-NEXT: v_med3_f32 v2, v4, v2, v3
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_global_nnans_med3_f32_pat0_negabs012: ; GFX9-LABEL: v_test_global_nnans_med3_f32_pat0_negabs012:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: global_load_dword v2, v0, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] ; GFX9-NEXT: global_load_dword v2, v0, s[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s2, 0x80000000 ; GFX9-NEXT: s_mov_b32 s2, 0x80000000
; GFX9-NEXT: s_waitcnt vmcnt(2)
; GFX9-NEXT: v_sub_f32_e64 v1, s2, |v1| ; GFX9-NEXT: v_sub_f32_e64 v1, s2, |v1|
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_sub_f32_e64 v2, s2, |v2| ; GFX9-NEXT: v_sub_f32_e64 v2, s2, |v2|
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_f32_e64 v3, s2, |v3| ; GFX9-NEXT: v_sub_f32_e64 v3, s2, |v3|
; GFX9-NEXT: v_med3_f32 v1, v1, v2, v3 ; GFX9-NEXT: v_med3_f32 v1, v1, v2, v3
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid %gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
%gep1 = getelementptr float, float addrspace(1)* %bptr, i32 %tid %gep1 = getelementptr float, float addrspace(1)* %bptr, i32 %tid
%gep2 = getelementptr float, float addrspace(1)* %cptr, i32 %tid %gep2 = getelementptr float, float addrspace(1)* %cptr, i32 %tid
Show All 23 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b32 s10, 0 ; SI-NEXT: s_mov_b32 s10, 0
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[2:3] ; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[4:5] ; SI-NEXT: s_mov_b64 s[8:9], s[4:5]
; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[6:7] ; SI-NEXT: s_mov_b64 s[8:9], s[6:7]
; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_add_f32_e32 v2, 1.0, v2
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_add_f32_e32 v3, 2.0, v3 ; SI-NEXT: v_add_f32_e32 v3, 2.0, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_add_f32_e32 v4, 4.0, v4 ; SI-NEXT: v_add_f32_e32 v4, 4.0, v4
; SI-NEXT: v_min_f32_e32 v5, v2, v3 ; SI-NEXT: v_min_f32_e32 v5, v2, v3
; SI-NEXT: v_max_f32_e32 v2, v2, v3 ; SI-NEXT: v_max_f32_e32 v2, v2, v3
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_min_f32_e32 v2, v2, v4 ; SI-NEXT: v_min_f32_e32 v2, v2, v4
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5 ; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_max_f32_e32 v2, v3, v2 ; SI-NEXT: v_max_f32_e32 v2, v3, v2
Show All 13 Lines
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; VI-NEXT: v_mov_b32_e32 v4, s6 ; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_mov_b32_e32 v5, s7 ; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: flat_load_dword v7, v[0:1] ; VI-NEXT: flat_load_dword v7, v[0:1] glc
; VI-NEXT: flat_load_dword v2, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] ; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_add_f32_e32 v4, 1.0, v7 ; VI-NEXT: v_add_f32_e32 v4, 1.0, v7
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_add_f32_e32 v2, 2.0, v2 ; VI-NEXT: v_add_f32_e32 v2, 2.0, v2
; VI-NEXT: v_min_f32_e32 v5, v4, v2 ; VI-NEXT: v_min_f32_e32 v5, v4, v2
; VI-NEXT: v_max_f32_e32 v2, v4, v2 ; VI-NEXT: v_max_f32_e32 v2, v4, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_f32_e32 v3, 4.0, v3 ; VI-NEXT: v_add_f32_e32 v3, 4.0, v3
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; VI-NEXT: v_min_f32_e32 v2, v2, v3 ; VI-NEXT: v_min_f32_e32 v2, v2, v3
; VI-NEXT: v_mul_f32_e32 v3, 1.0, v5 ; VI-NEXT: v_mul_f32_e32 v3, 1.0, v5
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; VI-NEXT: v_max_f32_e32 v2, v3, v2 ; VI-NEXT: v_max_f32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_nnan_inputs_med3_f32_pat0: ; GFX9-LABEL: v_nnan_inputs_med3_f32_pat0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: global_load_dword v2, v0, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] ; GFX9-NEXT: global_load_dword v2, v0, s[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1 ; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_add_f32_e32 v2, 2.0, v2 ; GFX9-NEXT: v_add_f32_e32 v2, 2.0, v2
; GFX9-NEXT: v_min_f32_e32 v4, v1, v2 ; GFX9-NEXT: v_min_f32_e32 v4, v1, v2
; GFX9-NEXT: v_max_f32_e32 v1, v1, v2 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v2
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_f32_e32 v3, 4.0, v3 ; GFX9-NEXT: v_add_f32_e32 v3, 4.0, v3
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
; GFX9-NEXT: v_min_f32_e32 v1, v1, v3 ; GFX9-NEXT: v_min_f32_e32 v1, v1, v3
; GFX9-NEXT: v_max_f32_e32 v2, v4, v4 ; GFX9-NEXT: v_max_f32_e32 v2, v4, v4
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
; GFX9-NEXT: v_max_f32_e32 v1, v2, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v2, v1
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
Show All 28 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x9
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b32 s10, 0 ; SI-NEXT: s_mov_b32 s10, 0
; SI-NEXT: s_mov_b32 s11, 0xf000 ; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[2:3] ; SI-NEXT: s_mov_b64 s[8:9], s[2:3]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[8:9], s[4:5] ; SI-NEXT: s_mov_b64 s[8:9], s[4:5]
; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v3, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s3, s11 ; SI-NEXT: s_mov_b32 s3, s11
; SI-NEXT: s_mov_b64 s[8:9], s[6:7] ; SI-NEXT: s_mov_b64 s[8:9], s[6:7]
; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_load_dword v4, v[0:1], s[8:11], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3 ; SI-NEXT: v_mul_f32_e32 v3, 1.0, v3
; SI-NEXT: v_min_f32_e32 v5, v2, v3 ; SI-NEXT: v_min_f32_e32 v5, v2, v3
; SI-NEXT: v_max_f32_e32 v2, v2, v3 ; SI-NEXT: v_max_f32_e32 v2, v2, v3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4 ; SI-NEXT: v_mul_f32_e32 v3, 1.0, v4
; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v5, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_min_f32_e32 v2, v2, v3 ; SI-NEXT: v_min_f32_e32 v2, v2, v3
; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5 ; SI-NEXT: v_mul_f32_e32 v3, 1.0, v5
; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; SI-NEXT: v_max_f32_e32 v2, v3, v2 ; SI-NEXT: v_max_f32_e32 v2, v3, v2
; SI-NEXT: s_mov_b64 s[2:3], s[10:11] ; SI-NEXT: s_mov_b64 s[2:3], s[10:11]
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
Show All 10 Lines
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s5 ; VI-NEXT: v_mov_b32_e32 v3, s5
; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6 ; VI-NEXT: v_add_u32_e32 v2, vcc, v2, v6
; VI-NEXT: v_mov_b32_e32 v4, s6 ; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: v_mov_b32_e32 v5, s7 ; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6 ; VI-NEXT: v_add_u32_e32 v4, vcc, v4, v6
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: flat_load_dword v7, v[0:1] ; VI-NEXT: flat_load_dword v7, v[0:1] glc
; VI-NEXT: flat_load_dword v2, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] ; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v3, v[4:5] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0 ; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6 ; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v6
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_mul_f32_e32 v4, 1.0, v7 ; VI-NEXT: v_mul_f32_e32 v4, 1.0, v7
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; VI-NEXT: v_min_f32_e32 v5, v4, v2 ; VI-NEXT: v_min_f32_e32 v5, v4, v2
; VI-NEXT: v_max_f32_e32 v2, v4, v2 ; VI-NEXT: v_max_f32_e32 v2, v4, v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mul_f32_e32 v3, 1.0, v3 ; VI-NEXT: v_mul_f32_e32 v3, 1.0, v3
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; VI-NEXT: v_min_f32_e32 v2, v2, v3 ; VI-NEXT: v_min_f32_e32 v2, v2, v3
; VI-NEXT: v_mul_f32_e32 v3, 1.0, v5 ; VI-NEXT: v_mul_f32_e32 v3, 1.0, v5
; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2 ; VI-NEXT: v_mul_f32_e32 v2, 1.0, v2
; VI-NEXT: v_max_f32_e32 v2, v3, v2 ; VI-NEXT: v_max_f32_e32 v2, v3, v2
; VI-NEXT: flat_store_dword v[0:1], v5 ; VI-NEXT: flat_store_dword v[0:1], v5
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_safe_med3_f32_pat0_multi_use0: ; GFX9-LABEL: v_test_safe_med3_f32_pat0_multi_use0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx8 s[0:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: global_load_dword v2, v0, s[4:5] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] ; GFX9-NEXT: global_load_dword v2, v0, s[4:5] glc
; GFX9-NEXT: s_waitcnt vmcnt(2) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v3, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_max_f32_e32 v2, v2, v2 ; GFX9-NEXT: v_max_f32_e32 v2, v2, v2
; GFX9-NEXT: v_min_f32_e32 v4, v1, v2 ; GFX9-NEXT: v_min_f32_e32 v4, v1, v2
; GFX9-NEXT: v_max_f32_e32 v1, v1, v2 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v2
; GFX9-NEXT: global_store_dword v[0:1], v4, off ; GFX9-NEXT: global_store_dword v[0:1], v4, off
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f32_e32 v3, v3, v3 ; GFX9-NEXT: v_max_f32_e32 v3, v3, v3
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
; GFX9-NEXT: v_min_f32_e32 v1, v1, v3 ; GFX9-NEXT: v_min_f32_e32 v1, v1, v3
; GFX9-NEXT: v_max_f32_e32 v2, v4, v4 ; GFX9-NEXT: v_max_f32_e32 v2, v4, v4
; GFX9-NEXT: v_max_f32_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v1, v1
; GFX9-NEXT: v_max_f32_e32 v1, v2, v1 ; GFX9-NEXT: v_max_f32_e32 v1, v2, v1
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
Show All 30 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll

Show First 20 Lines • Show All 804 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: v_cndmask_b32_e64 v17, v17, v0, s[14:15] ; GPRIDX-NEXT: v_cndmask_b32_e64 v17, v17, v0, s[14:15]
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v1, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v1, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v16, v16, v1, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e64 v16, v16, v1, s[12:13]
; GPRIDX-NEXT: v_cndmask_b32_e64 v18, v18, v1, s[14:15] ; GPRIDX-NEXT: v_cndmask_b32_e64 v18, v18, v1, s[14:15]
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[3:6], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[7:10], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[11:14], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[15:18], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0) ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_setpc_b64 s[30:31] ; GPRIDX-NEXT: s_setpc_b64 s[30:31]
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_const_s_v_v: ; MOVREL-LABEL: dyn_insertelement_v8f64_const_s_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; MOVREL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0 ; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v0, s7 ; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v0, s7
; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v1, s6 ; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v1, s6
; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v1, s7 ; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v1, s7
; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v0, s8 ; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v0, s8
; MOVREL-NEXT: v_cndmask_b32_e64 v17, v17, v0, s9 ; MOVREL-NEXT: v_cndmask_b32_e64 v17, v17, v0, s9
; MOVREL-NEXT: v_cndmask_b32_e64 v16, v16, v1, s8 ; MOVREL-NEXT: v_cndmask_b32_e64 v16, v16, v1, s8
; MOVREL-NEXT: v_cndmask_b32_e64 v18, v18, v1, s9 ; MOVREL-NEXT: v_cndmask_b32_e64 v18, v18, v1, s9
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[3:6], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[7:10], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[11:14], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[15:18], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0 ; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_setpc_b64 s[30:31] ; MOVREL-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%insert = insertelement <8 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0>, double %val, i32 %idx %insert = insertelement <8 x double> <double 1.0, double 2.0, double 3.0, double 4.0, double 5.0, double 6.0, double 7.0, double 8.0>, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v6, v6, v0, s[0:1] ; GPRIDX-NEXT: v_cndmask_b32_e64 v6, v6, v0, s[0:1]
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v0, s[2:3] ; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v0, s[2:3]
; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v0, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v0, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v0, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v0, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v0, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v0, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v16, v16, v0, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v16, v16, v0, s[10:11]
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[1:4], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[1:4], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[5:8], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[5:8], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[9:12], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[9:12], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[13:16], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[13:16], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_s_s_v: ; MOVREL-LABEL: dyn_insertelement_v8f64_s_s_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: s_mov_b32 s7, s9
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, s31, s0 ; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, s31, s0
; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, s30, s2 ; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, s30, s2
; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, s31, s2 ; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, s31, s2
; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, s30, s3 ; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, s30, s3
; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, s31, s3 ; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, s31, s3
; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, s30, s4 ; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, s30, s4
; MOVREL-NEXT: v_cndmask_b32_e64 v16, v16, s31, s4 ; MOVREL-NEXT: v_cndmask_b32_e64 v16, v16, s31, s4
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[1:4], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[1:4], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[5:8], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[5:8], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[9:12], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[9:12], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[13:16], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[13:16], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
entry: entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx %insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7> %vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef
Show All 39 Lines
; GPRIDX-NEXT: v_mov_b32_e32 v3, s1 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s0 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s0
; GPRIDX-NEXT: s_lshl_b32 s0, s18, 1 ; GPRIDX-NEXT: s_lshl_b32 s0, s18, 1
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST) ; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v2, v0 ; GPRIDX-NEXT: v_mov_b32_e32 v2, v0
; GPRIDX-NEXT: v_mov_b32_e32 v3, v1 ; GPRIDX-NEXT: v_mov_b32_e32 v3, v1
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[2:5], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[6:9], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[6:9], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[10:13], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[10:13], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[14:17], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[14:17], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_s_v_s: ; MOVREL-LABEL: dyn_insertelement_v8f64_s_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: s_mov_b32 s7, s9
Show All 24 Lines
; MOVREL-NEXT: v_mov_b32_e32 v7, s5 ; MOVREL-NEXT: v_mov_b32_e32 v7, s5
; MOVREL-NEXT: v_mov_b32_e32 v6, s4 ; MOVREL-NEXT: v_mov_b32_e32 v6, s4
; MOVREL-NEXT: v_mov_b32_e32 v5, s3 ; MOVREL-NEXT: v_mov_b32_e32 v5, s3
; MOVREL-NEXT: v_mov_b32_e32 v4, s2 ; MOVREL-NEXT: v_mov_b32_e32 v4, s2
; MOVREL-NEXT: v_mov_b32_e32 v3, s1 ; MOVREL-NEXT: v_mov_b32_e32 v3, s1
; MOVREL-NEXT: v_movreld_b32_e32 v2, v0 ; MOVREL-NEXT: v_movreld_b32_e32 v2, v0
; MOVREL-NEXT: v_movreld_b32_e32 v3, v1 ; MOVREL-NEXT: v_movreld_b32_e32 v3, v1
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[2:5], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[6:9], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[6:9], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[10:13], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[10:13], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[14:17], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[14:17], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
entry: entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx %insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7> %vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef
store volatile <2 x double> %vec.1, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.1, <2 x double> addrspace(1)* undef
store volatile <2 x double> %vec.2, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.2, <2 x double> addrspace(1)* undef
store volatile <2 x double> %vec.3, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.3, <2 x double> addrspace(1)* undef
ret void ret void
} }
define amdgpu_ps void @dyn_insertelement_v8f64_v_s_s(<8 x double> %vec, double inreg %val, i32 inreg %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_v_s_s(<8 x double> %vec, double inreg %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_v_s_s: ; GPRIDX-LABEL: dyn_insertelement_v8f64_v_s_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_lshl_b32 s0, s4, 1 ; GPRIDX-NEXT: s_lshl_b32 s0, s4, 1
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST) ; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v0, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v0, s2
; GPRIDX-NEXT: v_mov_b32_e32 v1, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s3
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_v_s_s: ; MOVREL-LABEL: dyn_insertelement_v8f64_v_s_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_lshl_b32 m0, s4, 1 ; MOVREL-NEXT: s_lshl_b32 m0, s4, 1
; MOVREL-NEXT: v_movreld_b32_e32 v0, s2 ; MOVREL-NEXT: v_movreld_b32_e32 v0, s2
; MOVREL-NEXT: v_movreld_b32_e32 v1, s3 ; MOVREL-NEXT: v_movreld_b32_e32 v1, s3
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
entry: entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx %insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7> %vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: v_cndmask_b32_e64 v17, v17, v0, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v17, v17, v0, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[0:1] ; GPRIDX-NEXT: v_cndmask_b32_e64 v8, v8, v1, s[0:1]
; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[2:3] ; GPRIDX-NEXT: v_cndmask_b32_e64 v10, v10, v1, s[2:3]
; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e64 v12, v12, v1, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v1, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v1, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v16, v16, v1, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e64 v16, v16, v1, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v18, v18, v1, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v18, v18, v1, s[10:11]
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[3:6], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[7:10], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[11:14], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[15:18], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_s_v_v: ; MOVREL-LABEL: dyn_insertelement_v8f64_s_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: s_mov_b32 s3, s5
; MOVREL-NEXT: s_mov_b32 s5, s7 ; MOVREL-NEXT: s_mov_b32 s5, s7
; MOVREL-NEXT: s_mov_b32 s7, s9 ; MOVREL-NEXT: s_mov_b32 s7, s9
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3 ; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v0, s3
; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2 ; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v1, s2
; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3 ; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v1, s3
; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4 ; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v0, s4
; MOVREL-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5 ; MOVREL-NEXT: v_cndmask_b32_e64 v17, v17, v0, s5
; MOVREL-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4 ; MOVREL-NEXT: v_cndmask_b32_e64 v16, v16, v1, s4
; MOVREL-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5 ; MOVREL-NEXT: v_cndmask_b32_e64 v18, v18, v1, s5
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[3:6], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[3:6], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[7:10], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[7:10], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[11:14], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[11:14], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[15:18], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[15:18], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
entry: entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx %insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7> %vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef
Show All 28 Lines
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v17, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v17, s[12:13]
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v16, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v16, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v16, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v16, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v16, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v16, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v16, s[14:15] ; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v16, s[14:15]
; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v16, s[12:13]
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_v_s_v: ; MOVREL-LABEL: dyn_insertelement_v8f64_v_s_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16
; MOVREL-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo
; MOVREL-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v16
Show All 13 Lines
; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, s3, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, s3, vcc_lo
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16
; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo
; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v16 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v16
; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, s2, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, s2, vcc_lo
; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, s3, vcc_lo ; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, s3, vcc_lo
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
entry: entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx %insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7> %vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef
store volatile <2 x double> %vec.1, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.1, <2 x double> addrspace(1)* undef
store volatile <2 x double> %vec.2, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.2, <2 x double> addrspace(1)* undef
store volatile <2 x double> %vec.3, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.3, <2 x double> addrspace(1)* undef
ret void ret void
} }
define amdgpu_ps void @dyn_insertelement_v8f64_v_v_s(<8 x double> %vec, double %val, i32 inreg %idx) { define amdgpu_ps void @dyn_insertelement_v8f64_v_v_s(<8 x double> %vec, double %val, i32 inreg %idx) {
; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_s: ; GPRIDX-LABEL: dyn_insertelement_v8f64_v_v_s:
; GPRIDX: ; %bb.0: ; %entry ; GPRIDX: ; %bb.0: ; %entry
; GPRIDX-NEXT: s_lshl_b32 s0, s2, 1 ; GPRIDX-NEXT: s_lshl_b32 s0, s2, 1
; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST) ; GPRIDX-NEXT: s_set_gpr_idx_on s0, gpr_idx(DST)
; GPRIDX-NEXT: v_mov_b32_e32 v0, v16 ; GPRIDX-NEXT: v_mov_b32_e32 v0, v16
; GPRIDX-NEXT: v_mov_b32_e32 v1, v17 ; GPRIDX-NEXT: v_mov_b32_e32 v1, v17
; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: s_set_gpr_idx_off
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_v_v_s: ; MOVREL-LABEL: dyn_insertelement_v8f64_v_v_s:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_lshl_b32 m0, s2, 1 ; MOVREL-NEXT: s_lshl_b32 m0, s2, 1
; MOVREL-NEXT: v_movreld_b32_e32 v0, v16 ; MOVREL-NEXT: v_movreld_b32_e32 v0, v16
; MOVREL-NEXT: v_movreld_b32_e32 v1, v17 ; MOVREL-NEXT: v_movreld_b32_e32 v1, v17
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
entry: entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx %insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7> %vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef
Show All 26 Lines
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v17, s[2:3] ; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v17, s[2:3]
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v17, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v17, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v17, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v17, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[12:13]
; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[10:11]
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_v_v_v: ; MOVREL-LABEL: dyn_insertelement_v8f64_v_v_v:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 1, v18 ; MOVREL-NEXT: v_cmp_eq_u32_e64 s0, 1, v18
; MOVREL-NEXT: v_mov_b32_e32 v19, v0 ; MOVREL-NEXT: v_mov_b32_e32 v19, v0
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
; MOVREL-NEXT: v_mov_b32_e32 v23, v1 ; MOVREL-NEXT: v_mov_b32_e32 v23, v1
Show All 15 Lines
; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4 ; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4
; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3 ; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3
; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4 ; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4
; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6 ; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6
; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5 ; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5
; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6 ; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6
; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5 ; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
entry: entry:
%insert = insertelement <8 x double> %vec, double %val, i32 %idx %insert = insertelement <8 x double> %vec, double %val, i32 %idx
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7> %vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef store volatile <2 x double> %vec.0, <2 x double> addrspace(1)* undef
▲ Show 20 Lines • Show All 465 Lines • ▼ Show 20 Lines
; GPRIDX-NEXT: s_mov_b32 m0, s20 ; GPRIDX-NEXT: s_mov_b32 m0, s20
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_nop 0
; GPRIDX-NEXT: s_movreld_b64 s[2:3], s[18:19] ; GPRIDX-NEXT: s_movreld_b64 s[2:3], s[18:19]
; GPRIDX-NEXT: v_mov_b32_e32 v0, s0 ; GPRIDX-NEXT: v_mov_b32_e32 v0, s0
; GPRIDX-NEXT: v_mov_b32_e32 v1, s1 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s1
; GPRIDX-NEXT: v_mov_b32_e32 v2, s2 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s2
; GPRIDX-NEXT: v_mov_b32_e32 v3, s3 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s3
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: v_mov_b32_e32 v0, s4 ; GPRIDX-NEXT: v_mov_b32_e32 v0, s4
; GPRIDX-NEXT: v_mov_b32_e32 v1, s5 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s5
; GPRIDX-NEXT: v_mov_b32_e32 v2, s6 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s6
; GPRIDX-NEXT: v_mov_b32_e32 v3, s7 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s7
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: v_mov_b32_e32 v0, s8 ; GPRIDX-NEXT: v_mov_b32_e32 v0, s8
; GPRIDX-NEXT: v_mov_b32_e32 v1, s9 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s9
; GPRIDX-NEXT: v_mov_b32_e32 v2, s10 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s10
; GPRIDX-NEXT: v_mov_b32_e32 v3, s11 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s11
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_nop 0 ; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: v_mov_b32_e32 v0, s12 ; GPRIDX-NEXT: v_mov_b32_e32 v0, s12
; GPRIDX-NEXT: v_mov_b32_e32 v1, s13 ; GPRIDX-NEXT: v_mov_b32_e32 v1, s13
; GPRIDX-NEXT: v_mov_b32_e32 v2, s14 ; GPRIDX-NEXT: v_mov_b32_e32 v2, s14
; GPRIDX-NEXT: v_mov_b32_e32 v3, s15 ; GPRIDX-NEXT: v_mov_b32_e32 v3, s15
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_s_s_s_add_1: ; MOVREL-LABEL: dyn_insertelement_v8f64_s_s_s_add_1:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: s_mov_b32 s0, s2 ; MOVREL-NEXT: s_mov_b32 s0, s2
; MOVREL-NEXT: s_mov_b32 s1, s3 ; MOVREL-NEXT: s_mov_b32 s1, s3
; MOVREL-NEXT: s_mov_b32 s2, s4 ; MOVREL-NEXT: s_mov_b32 s2, s4
; MOVREL-NEXT: s_mov_b32 s3, s5 ; MOVREL-NEXT: s_mov_b32 s3, s5
Show All 23 Lines
; MOVREL-NEXT: v_mov_b32_e32 v12, s12 ; MOVREL-NEXT: v_mov_b32_e32 v12, s12
; MOVREL-NEXT: v_mov_b32_e32 v9, s9 ; MOVREL-NEXT: v_mov_b32_e32 v9, s9
; MOVREL-NEXT: v_mov_b32_e32 v10, s10 ; MOVREL-NEXT: v_mov_b32_e32 v10, s10
; MOVREL-NEXT: v_mov_b32_e32 v11, s11 ; MOVREL-NEXT: v_mov_b32_e32 v11, s11
; MOVREL-NEXT: v_mov_b32_e32 v13, s13 ; MOVREL-NEXT: v_mov_b32_e32 v13, s13
; MOVREL-NEXT: v_mov_b32_e32 v14, s14 ; MOVREL-NEXT: v_mov_b32_e32 v14, s14
; MOVREL-NEXT: v_mov_b32_e32 v15, s15 ; MOVREL-NEXT: v_mov_b32_e32 v15, s15
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
entry: entry:
%idx.add = add i32 %idx, 1 %idx.add = add i32 %idx, 1
%insert = insertelement <8 x double> %vec, double %val, i32 %idx.add %insert = insertelement <8 x double> %vec, double %val, i32 %idx.add
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7> %vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
Show All 28 Lines
; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v14, v14, v16, s[10:11]
; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v17, s[2:3] ; GPRIDX-NEXT: v_cndmask_b32_e64 v5, v5, v17, s[2:3]
; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v17, s[4:5] ; GPRIDX-NEXT: v_cndmask_b32_e64 v7, v7, v17, s[4:5]
; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v17, s[6:7] ; GPRIDX-NEXT: v_cndmask_b32_e64 v9, v9, v17, s[6:7]
; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[8:9] ; GPRIDX-NEXT: v_cndmask_b32_e64 v11, v11, v17, s[8:9]
; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[12:13] ; GPRIDX-NEXT: v_cndmask_b32_e64 v13, v13, v17, s[12:13]
; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[10:11] ; GPRIDX-NEXT: v_cndmask_b32_e64 v15, v15, v17, s[10:11]
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; GPRIDX-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; GPRIDX-NEXT: s_waitcnt vmcnt(0)
; GPRIDX-NEXT: s_endpgm ; GPRIDX-NEXT: s_endpgm
; ;
; MOVREL-LABEL: dyn_insertelement_v8f64_v_v_v_add_1: ; MOVREL-LABEL: dyn_insertelement_v8f64_v_v_v_add_1:
; MOVREL: ; %bb.0: ; %entry ; MOVREL: ; %bb.0: ; %entry
; MOVREL-NEXT: v_add_nc_u32_e32 v18, 1, v18 ; MOVREL-NEXT: v_add_nc_u32_e32 v18, 1, v18
; MOVREL-NEXT: v_mov_b32_e32 v19, v0 ; MOVREL-NEXT: v_mov_b32_e32 v19, v0
; MOVREL-NEXT: v_mov_b32_e32 v23, v1 ; MOVREL-NEXT: v_mov_b32_e32 v23, v1
; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18 ; MOVREL-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v18
Show All 16 Lines
; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4 ; MOVREL-NEXT: v_cndmask_b32_e64 v10, v10, v16, s4
; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3 ; MOVREL-NEXT: v_cndmask_b32_e64 v9, v9, v17, s3
; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4 ; MOVREL-NEXT: v_cndmask_b32_e64 v11, v11, v17, s4
; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6 ; MOVREL-NEXT: v_cndmask_b32_e64 v12, v12, v16, s6
; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5 ; MOVREL-NEXT: v_cndmask_b32_e64 v14, v14, v16, s5
; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6 ; MOVREL-NEXT: v_cndmask_b32_e64 v13, v13, v17, s6
; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5 ; MOVREL-NEXT: v_cndmask_b32_e64 v15, v15, v17, s5
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[0:3], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[4:7], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[8:11], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off ; MOVREL-NEXT: global_store_dwordx4 v[0:1], v[12:15], off
; MOVREL-NEXT: s_waitcnt_vscnt null, 0x0
; MOVREL-NEXT: s_endpgm ; MOVREL-NEXT: s_endpgm
entry: entry:
%idx.add = add i32 %idx, 1 %idx.add = add i32 %idx, 1
%insert = insertelement <8 x double> %vec, double %val, i32 %idx.add %insert = insertelement <8 x double> %vec, double %val, i32 %idx.add
%vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1> %vec.0 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 0, i32 1>
%vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3> %vec.1 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 2, i32 3>
%vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5> %vec.2 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 4, i32 5>
%vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7> %vec.3 = shufflevector <8 x double> %insert, <8 x double> undef, <2 x i32> <i32 6, i32 7>
▲ Show 20 Lines • Show All 2,359 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

Show First 20 Lines • Show All 812 Lines • ▼ Show 20 Lines
; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX7-NEXT: s_load_dword s8, s[0:1], 0x15 ; GFX7-NEXT: s_load_dword s8, s[0:1], 0x15
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX7-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX7-NEXT: v_mov_b32_e32 v2, 0 ; GFX7-NEXT: v_mov_b32_e32 v2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_mov_b64 s[0:1], s[6:7] ; GFX7-NEXT: s_mov_b64 s[0:1], s[6:7]
; GFX7-NEXT: buffer_load_dword v3, v[1:2], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v3, v[1:2], s[0:3], 0 addr64 glc
; GFX7-NEXT: buffer_load_dword v4, v[1:2], s[0:3], 0 addr64 offset:4 ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_load_dword v1, v[1:2], s[0:3], 0 addr64 offset:8 ; GFX7-NEXT: buffer_load_dword v4, v[1:2], s[0:3], 0 addr64 offset:4 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_load_dword v1, v[1:2], s[0:3], 0 addr64 offset:8 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_cmp_lg_u32 s8, 0 ; GFX7-NEXT: s_cmp_lg_u32 s8, 0
; GFX7-NEXT: s_cselect_b32 s0, 1, 0 ; GFX7-NEXT: s_cselect_b32 s0, 1, 0
; GFX7-NEXT: s_and_b32 s0, 1, s0 ; GFX7-NEXT: s_and_b32 s0, 1, s0
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX7-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX7-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_and_b64 vcc, vcc, s[0:1] ; GFX7-NEXT: s_and_b64 vcc, vcc, s[0:1]
; GFX7-NEXT: s_mov_b64 s[6:7], s[2:3] ; GFX7-NEXT: s_mov_b64 s[6:7], s[2:3]
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_div_fmas_f32 v0, v3, v4, v1 ; GFX7-NEXT: v_div_fmas_f32 v0, v3, v4, v1
; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:8 ; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0 offset:8
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_div_fmas_f32_logical_cond_to_vcc: ; GFX8-LABEL: test_div_fmas_f32_logical_cond_to_vcc:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX8-NEXT: s_load_dword s2, s[0:1], 0x54 ; GFX8-NEXT: s_load_dword s2, s[0:1], 0x54
; GFX8-NEXT: v_lshlrev_b32_e32 v3, 2, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v3, 2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s6 ; GFX8-NEXT: v_mov_b32_e32 v1, s6
; GFX8-NEXT: v_mov_b32_e32 v2, s7 ; GFX8-NEXT: v_mov_b32_e32 v2, s7
; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3 ; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v1 ; GFX8-NEXT: v_add_u32_e32 v3, vcc, 4, v1
; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v4, vcc, 0, v2, vcc
; GFX8-NEXT: v_add_u32_e32 v5, vcc, 8, v1 ; GFX8-NEXT: v_add_u32_e32 v5, vcc, 8, v1
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v2, vcc
; GFX8-NEXT: flat_load_dword v1, v[1:2] ; GFX8-NEXT: flat_load_dword v1, v[1:2] glc
; GFX8-NEXT: flat_load_dword v2, v[3:4] ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dword v3, v[5:6] ; GFX8-NEXT: flat_load_dword v2, v[3:4] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dword v3, v[5:6] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_add_u32 s0, s4, 8 ; GFX8-NEXT: s_add_u32 s0, s4, 8
; GFX8-NEXT: s_addc_u32 s1, s5, 0 ; GFX8-NEXT: s_addc_u32 s1, s5, 0
; GFX8-NEXT: s_cmp_lg_u32 s2, 0 ; GFX8-NEXT: s_cmp_lg_u32 s2, 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0 ; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_and_b32 s2, 1, s2 ; GFX8-NEXT: s_and_b32 s2, 1, s2
; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2
; GFX8-NEXT: s_and_b64 vcc, vcc, s[2:3] ; GFX8-NEXT: s_and_b64 vcc, vcc, s[2:3]
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_nop 1
; GFX8-NEXT: s_nop 0
; GFX8-NEXT: v_div_fmas_f32 v2, v1, v2, v3 ; GFX8-NEXT: v_div_fmas_f32 v2, v1, v2, v3
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX10_W32-LABEL: test_div_fmas_f32_logical_cond_to_vcc: ; GFX10_W32-LABEL: test_div_fmas_f32_logical_cond_to_vcc:
; GFX10_W32: ; %bb.0: ; GFX10_W32: ; %bb.0:
; GFX10_W32-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10_W32-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10_W32-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX10_W32-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX10_W32-NEXT: s_load_dword s0, s[0:1], 0x54 ; GFX10_W32-NEXT: s_load_dword s0, s[0:1], 0x54
; GFX10_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX10_W32-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W32-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W32-NEXT: s_clause 0x2 ; GFX10_W32-NEXT: global_load_dword v2, v1, s[6:7] glc dlc
; GFX10_W32-NEXT: global_load_dword v2, v1, s[6:7] ; GFX10_W32-NEXT: s_waitcnt vmcnt(0)
; GFX10_W32-NEXT: global_load_dword v3, v1, s[6:7] offset:4 ; GFX10_W32-NEXT: global_load_dword v3, v1, s[6:7] offset:4 glc dlc
; GFX10_W32-NEXT: global_load_dword v1, v1, s[6:7] offset:8 ; GFX10_W32-NEXT: s_waitcnt vmcnt(0)
; GFX10_W32-NEXT: global_load_dword v1, v1, s[6:7] offset:8 glc dlc
; GFX10_W32-NEXT: s_waitcnt vmcnt(0)
; GFX10_W32-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10_W32-NEXT: s_cmp_lg_u32 s0, 0
; GFX10_W32-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10_W32-NEXT: s_cselect_b32 s0, 1, 0
; GFX10_W32-NEXT: s_and_b32 s0, 1, s0 ; GFX10_W32-NEXT: s_and_b32 s0, 1, s0
; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 ; GFX10_W32-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
; GFX10_W32-NEXT: s_and_b32 vcc_lo, vcc_lo, s0 ; GFX10_W32-NEXT: s_and_b32 vcc_lo, vcc_lo, s0
; GFX10_W32-NEXT: s_waitcnt vmcnt(0)
; GFX10_W32-NEXT: v_div_fmas_f32 v0, v2, v3, v1 ; GFX10_W32-NEXT: v_div_fmas_f32 v0, v2, v3, v1
; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W32-NEXT: v_mov_b32_e32 v1, 0
; GFX10_W32-NEXT: global_store_dword v1, v0, s[4:5] offset:8 ; GFX10_W32-NEXT: global_store_dword v1, v0, s[4:5] offset:8
; GFX10_W32-NEXT: s_endpgm ; GFX10_W32-NEXT: s_endpgm
; ;
; GFX10_W64-LABEL: test_div_fmas_f32_logical_cond_to_vcc: ; GFX10_W64-LABEL: test_div_fmas_f32_logical_cond_to_vcc:
; GFX10_W64: ; %bb.0: ; GFX10_W64: ; %bb.0:
; GFX10_W64-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX10_W64-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX10_W64-NEXT: v_lshlrev_b32_e32 v1, 2, v0 ; GFX10_W64-NEXT: v_lshlrev_b32_e32 v1, 2, v0
; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x54 ; GFX10_W64-NEXT: s_load_dword s0, s[0:1], 0x54
; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 ; GFX10_W64-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0
; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0) ; GFX10_W64-NEXT: s_waitcnt lgkmcnt(0)
; GFX10_W64-NEXT: s_clause 0x2 ; GFX10_W64-NEXT: global_load_dword v2, v1, s[6:7] glc dlc
; GFX10_W64-NEXT: global_load_dword v2, v1, s[6:7] ; GFX10_W64-NEXT: s_waitcnt vmcnt(0)
; GFX10_W64-NEXT: global_load_dword v3, v1, s[6:7] offset:4 ; GFX10_W64-NEXT: global_load_dword v3, v1, s[6:7] offset:4 glc dlc
; GFX10_W64-NEXT: global_load_dword v1, v1, s[6:7] offset:8 ; GFX10_W64-NEXT: s_waitcnt vmcnt(0)
; GFX10_W64-NEXT: global_load_dword v1, v1, s[6:7] offset:8 glc dlc
; GFX10_W64-NEXT: s_waitcnt vmcnt(0)
; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0 ; GFX10_W64-NEXT: s_cmp_lg_u32 s0, 0
; GFX10_W64-NEXT: s_cselect_b32 s0, 1, 0 ; GFX10_W64-NEXT: s_cselect_b32 s0, 1, 0
; GFX10_W64-NEXT: s_and_b32 s0, 1, s0 ; GFX10_W64-NEXT: s_and_b32 s0, 1, s0
; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0 ; GFX10_W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, s0
; GFX10_W64-NEXT: s_and_b64 vcc, vcc, s[0:1] ; GFX10_W64-NEXT: s_and_b64 vcc, vcc, s[0:1]
; GFX10_W64-NEXT: s_waitcnt vmcnt(0)
; GFX10_W64-NEXT: v_div_fmas_f32 v0, v2, v3, v1 ; GFX10_W64-NEXT: v_div_fmas_f32 v0, v2, v3, v1
; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0 ; GFX10_W64-NEXT: v_mov_b32_e32 v1, 0
; GFX10_W64-NEXT: global_store_dword v1, v0, s[4:5] offset:8 ; GFX10_W64-NEXT: global_store_dword v1, v0, s[4:5] offset:8
; GFX10_W64-NEXT: s_endpgm ; GFX10_W64-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
%gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
▲ Show 20 Lines • Show All 175 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck --check-prefix=GFX7 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck --check-prefix=GFX7 %s
; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s ; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefix=GFX10 %s
define amdgpu_kernel void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) { define amdgpu_kernel void @test_div_scale_f32_1(float addrspace(1)* %out, float addrspace(1)* %in) {
; GFX7-LABEL: test_div_scale_f32_1: ; GFX7-LABEL: test_div_scale_f32_1:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_mov_b64 s[4:5], s[2:3] ; GFX7-NEXT: s_mov_b64 s[4:5], s[2:3]
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s6, -1 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 offset:4 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: v_div_scale_f32 v0, s[2:3], v0, v0, v2 ; GFX7-NEXT: v_div_scale_f32 v0, s[2:3], v0, v0, v2
; GFX7-NEXT: s_mov_b64 s[2:3], s[6:7] ; GFX7-NEXT: s_mov_b64 s[2:3], s[6:7]
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_div_scale_f32_1: ; GFX8-LABEL: test_div_scale_f32_1:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1] ; GFX8-NEXT: flat_load_dword v0, v[0:1] glc
; GFX8-NEXT: flat_load_dword v1, v[2:3] ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dword v1, v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0 ; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_div_scale_f32_1: ; GFX10-LABEL: test_div_scale_f32_1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
; GFX10-NEXT: global_load_dword v1, v0, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] offset:4 ; GFX10-NEXT: global_load_dword v0, v0, s[2:3] offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_div_scale_f32 v0, s2, v0, v0, v1 ; GFX10-NEXT: v_div_scale_f32 v0, s2, v0, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
Show All 12 Lines
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_mov_b64 s[4:5], s[2:3] ; GFX7-NEXT: s_mov_b64 s[4:5], s[2:3]
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s6, -1 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 offset:4 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: v_div_scale_f32 v0, s[2:3], v2, v0, v2 ; GFX7-NEXT: v_div_scale_f32 v0, s[2:3], v2, v0, v2
; GFX7-NEXT: s_mov_b64 s[2:3], s[6:7] ; GFX7-NEXT: s_mov_b64 s[2:3], s[6:7]
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_div_scale_f32_2: ; GFX8-LABEL: test_div_scale_f32_2:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1] ; GFX8-NEXT: flat_load_dword v0, v[0:1] glc
; GFX8-NEXT: flat_load_dword v1, v[2:3] ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dword v1, v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v0, v1, v0 ; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v0, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_div_scale_f32_2: ; GFX10-LABEL: test_div_scale_f32_2:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
; GFX10-NEXT: global_load_dword v1, v0, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] offset:4 ; GFX10-NEXT: global_load_dword v0, v0, s[2:3] offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_div_scale_f32 v0, s2, v1, v0, v1 ; GFX10-NEXT: v_div_scale_f32 v0, s2, v1, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
Show All 15 Lines
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 8, v0 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[2:3] ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_div_scale_f64 v[0:1], s[2:3], v[2:3], v[2:3], v[0:1] ; GFX7-NEXT: v_div_scale_f64 v[0:1], s[2:3], v[2:3], v[2:3], v[0:1]
; GFX7-NEXT: v_mov_b32_e32 v3, s1 ; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0 ; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_div_scale_f64_1: ; GFX8-LABEL: test_div_scale_f64_1:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 8, v0 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[2:3] ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f64 v[0:1], s[2:3], v[2:3], v[2:3], v[0:1] ; GFX8-NEXT: v_div_scale_f64 v[0:1], s[2:3], v[2:3], v[2:3], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_div_scale_f64_1: ; GFX10-LABEL: test_div_scale_f64_1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] glc dlc
; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dwordx2 v[2:3], v2, s[2:3] offset:8 ; GFX10-NEXT: global_load_dwordx2 v[2:3], v2, s[2:3] offset:8 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_div_scale_f64 v[0:1], s2, v[2:3], v[2:3], v[0:1] ; GFX10-NEXT: v_div_scale_f64 v[0:1], s2, v[2:3], v[2:3], v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
Show All 15 Lines
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s2 ; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3 ; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX7-NEXT: v_add_i32_e32 v2, vcc, 8, v0 ; GFX7-NEXT: v_add_i32_e32 v2, vcc, 8, v0
; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; GFX7-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[2:3] ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_div_scale_f64 v[0:1], s[2:3], v[0:1], v[2:3], v[0:1] ; GFX7-NEXT: v_div_scale_f64 v[0:1], s[2:3], v[0:1], v[2:3], v[0:1]
; GFX7-NEXT: v_mov_b32_e32 v3, s1 ; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_mov_b32_e32 v2, s0 ; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX7-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_div_scale_f64_2: ; GFX8-LABEL: test_div_scale_f64_2:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 8, v0 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 8, v0
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[2:3] ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dwordx2 v[2:3], v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_div_scale_f64 v[0:1], s[2:3], v[0:1], v[2:3], v[0:1] ; GFX8-NEXT: v_div_scale_f64 v[0:1], s[2:3], v[0:1], v[2:3], v[0:1]
; GFX8-NEXT: v_mov_b32_e32 v3, s1 ; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_mov_b32_e32 v2, s0 ; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_div_scale_f64_2: ; GFX10-LABEL: test_div_scale_f64_2:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 ; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] glc dlc
; GFX10-NEXT: global_load_dwordx2 v[0:1], v2, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dwordx2 v[2:3], v2, s[2:3] offset:8 ; GFX10-NEXT: global_load_dwordx2 v[2:3], v2, s[2:3] offset:8 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_div_scale_f64 v[0:1], s2, v[0:1], v[2:3], v[0:1] ; GFX10-NEXT: v_div_scale_f64 v[0:1], s2, v[0:1], v[2:3], v[0:1]
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
▲ Show 20 Lines • Show All 784 Lines • ▼ Show 20 Lines
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_mov_b64 s[4:5], s[2:3] ; GFX7-NEXT: s_mov_b64 s[4:5], s[2:3]
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 offset:4 glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s6, -1 ; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: s_waitcnt vmcnt(1)
; GFX7-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2 ; GFX7-NEXT: v_and_b32_e32 v1, 0x7fffffff, v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_div_scale_f32 v0, s[2:3], v0, v0, v1 ; GFX7-NEXT: v_div_scale_f32 v0, s[2:3], v0, v0, v1
; GFX7-NEXT: s_mov_b64 s[2:3], s[6:7] ; GFX7-NEXT: s_mov_b64 s[2:3], s[6:7]
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_div_scale_f32_fabs_num: ; GFX8-LABEL: test_div_scale_f32_fabs_num:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1] ; GFX8-NEXT: flat_load_dword v0, v[0:1] glc
; GFX8-NEXT: flat_load_dword v1, v[2:3]
; GFX8-NEXT: s_waitcnt vmcnt(1)
; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dword v1, v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0 ; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_div_scale_f32_fabs_num: ; GFX10-LABEL: test_div_scale_f32_fabs_num:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
; GFX10-NEXT: global_load_dword v1, v0, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] offset:4 ; GFX10-NEXT: global_load_dword v0, v0, s[2:3] offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX10-NEXT: v_div_scale_f32 v0, s2, v0, v0, v1 ; GFX10-NEXT: v_div_scale_f32 v0, s2, v0, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
Show All 13 Lines
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: s_waitcnt lgkmcnt(0) ; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_mov_b64 s[4:5], s[2:3] ; GFX7-NEXT: s_mov_b64 s[4:5], s[2:3]
; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 offset:4 ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s6, -1 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 offset:4 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_mov_b32 s6, -1
; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX7-NEXT: v_div_scale_f32 v0, s[2:3], v0, v0, v2 ; GFX7-NEXT: v_div_scale_f32 v0, s[2:3], v0, v0, v2
; GFX7-NEXT: s_mov_b64 s[2:3], s[6:7] ; GFX7-NEXT: s_mov_b64 s[2:3], s[6:7]
; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX8-LABEL: test_div_scale_f32_fabs_den: ; GFX8-LABEL: test_div_scale_f32_fabs_den:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; GFX8-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX8-NEXT: s_waitcnt lgkmcnt(0) ; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s2 ; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v1, s3 ; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0 ; GFX8-NEXT: v_add_u32_e32 v2, vcc, 4, v0
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: flat_load_dword v0, v[0:1] ; GFX8-NEXT: flat_load_dword v0, v[0:1] glc
; GFX8-NEXT: flat_load_dword v1, v[2:3] ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: flat_load_dword v1, v[2:3] glc
; GFX8-NEXT: s_waitcnt vmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1 ; GFX8-NEXT: v_and_b32_e32 v1, 0x7fffffff, v1
; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0 ; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], v1, v1, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1 ; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2 ; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm ; GFX8-NEXT: s_endpgm
; ;
; GFX10-LABEL: test_div_scale_f32_fabs_den: ; GFX10-LABEL: test_div_scale_f32_fabs_den:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
; GFX10-NEXT: global_load_dword v1, v0, s[2:3] ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] offset:4 ; GFX10-NEXT: global_load_dword v0, v0, s[2:3] offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0
; GFX10-NEXT: v_div_scale_f32 v0, s2, v0, v0, v1 ; GFX10-NEXT: v_div_scale_f32 v0, s2, v0, v0, v1
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dword v1, v0, s[0:1] ; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
▲ Show 20 Lines • Show All 171 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll

Show All 10 Lines
; GCN-NEXT: s_cmp_lg_u32 s1, 0 ; GCN-NEXT: s_cmp_lg_u32 s1, 0
; GCN-NEXT: s_cselect_b32 s1, 1, 0 ; GCN-NEXT: s_cselect_b32 s1, 1, 0
; GCN-NEXT: s_and_b32 s1, s1, 1 ; GCN-NEXT: s_and_b32 s1, s1, 1
; GCN-NEXT: s_cmp_lg_u32 s1, 0 ; GCN-NEXT: s_cmp_lg_u32 s1, 0
; GCN-NEXT: s_cbranch_scc1 BB0_2 ; GCN-NEXT: s_cbranch_scc1 BB0_2
; GCN-NEXT: ; %bb.1: ; %mid ; GCN-NEXT: ; %bb.1: ; %mid
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt_vscnt null, 0x0
; GCN-NEXT: BB0_2: ; %bb ; GCN-NEXT: BB0_2: ; %bb
; GCN-NEXT: s_waitcnt_depctr 0xffe3 ; GCN-NEXT: s_waitcnt_depctr 0xffe3
; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0 ; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s0
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt_vscnt null, 0x0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg0, 0 %cond = icmp eq i32 %arg0, 0
br i1 %cond, label %mid, label %bb br i1 %cond, label %mid, label %bb
mid: mid:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
br label %bb br label %bb
bb: bb:
call void @llvm.amdgcn.end.cf.i32(i32 %saved) call void @llvm.amdgcn.end.cf.i32(i32 %saved)
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
ret void ret void
} }
declare void @llvm.amdgcn.end.cf.i32(i32 %val) declare void @llvm.amdgcn.end.cf.i32(i32 %val)

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll

Show All 9 Lines
; GCN-NEXT: s_cmp_lg_u32 s2, 0 ; GCN-NEXT: s_cmp_lg_u32 s2, 0
; GCN-NEXT: s_cselect_b32 s2, 1, 0 ; GCN-NEXT: s_cselect_b32 s2, 1, 0
; GCN-NEXT: s_and_b32 s2, s2, 1 ; GCN-NEXT: s_and_b32 s2, s2, 1
; GCN-NEXT: s_cmp_lg_u32 s2, 0 ; GCN-NEXT: s_cmp_lg_u32 s2, 0
; GCN-NEXT: s_cbranch_scc1 BB0_2 ; GCN-NEXT: s_cbranch_scc1 BB0_2
; GCN-NEXT: ; %bb.1: ; %mid ; GCN-NEXT: ; %bb.1: ; %mid
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: BB0_2: ; %bb ; GCN-NEXT: BB0_2: ; %bb
; GCN-NEXT: s_or_b64 exec, exec, s[0:1] ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg0, 0 %cond = icmp eq i32 %arg0, 0
br i1 %cond, label %mid, label %bb br i1 %cond, label %mid, label %bb
mid: mid:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
br label %bb br label %bb
bb: bb:
call void @llvm.amdgcn.end.cf.i64(i64 %saved) call void @llvm.amdgcn.end.cf.i64(i64 %saved)
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
ret void ret void
} }
declare void @llvm.amdgcn.end.cf.i64(i64 %val) declare void @llvm.amdgcn.end.cf.i64(i64 %val)

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll

Show All 9 Lines
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_eq_u32 s0, 0 ; GCN-NEXT: s_cmp_eq_u32 s0, 0
; GCN-NEXT: s_cselect_b32 s0, 1, 0 ; GCN-NEXT: s_cselect_b32 s0, 1, 0
; GCN-NEXT: s_and_b32 s0, 1, s0 ; GCN-NEXT: s_and_b32 s0, 1, s0
; GCN-NEXT: v_cmp_ne_u32_e64 s0, 0, s0 ; GCN-NEXT: v_cmp_ne_u32_e64 s0, 0, s0
; GCN-NEXT: s_or_b32 s0, s0, s1 ; GCN-NEXT: s_or_b32 s0, s0, s1
; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt_vscnt null, 0x0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg0, 0 %cond = icmp eq i32 %arg0, 0
%break = call i32 @llvm.amdgcn.if.break.i32(i1 %cond, i32 %saved) %break = call i32 @llvm.amdgcn.if.break.i32(i1 %cond, i32 %saved)
store volatile i32 %break, i32 addrspace(1)* undef store volatile i32 %break, i32 addrspace(1)* undef
ret void ret void
} }
declare i32 @llvm.amdgcn.if.break.i32(i1, i32) declare i32 @llvm.amdgcn.if.break.i32(i1, i32)

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll

Show All 9 Lines
; GCN-NEXT: s_cmp_eq_u32 s2, 0 ; GCN-NEXT: s_cmp_eq_u32 s2, 0
; GCN-NEXT: s_cselect_b32 s2, 1, 0 ; GCN-NEXT: s_cselect_b32 s2, 1, 0
; GCN-NEXT: s_and_b32 s2, 1, s2 ; GCN-NEXT: s_and_b32 s2, 1, s2
; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2 ; GCN-NEXT: v_cmp_ne_u32_e64 s[2:3], 0, s2
; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: v_mov_b32_e32 v1, s1
; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1] ; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg0, 0 %cond = icmp eq i32 %arg0, 0
%break = call i64 @llvm.amdgcn.if.break.i64(i1 %cond, i64 %saved) %break = call i64 @llvm.amdgcn.if.break.i64(i1 %cond, i64 %saved)
store volatile i64 %break, i64 addrspace(1)* undef store volatile i64 %break, i64 addrspace(1)* undef
ret void ret void
} }
declare i64 @llvm.amdgcn.if.break.i64(i1, i64) declare i64 @llvm.amdgcn.if.break.i64(i1, i64)

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.private.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
; TODO: Merge with DAG test ; TODO: Merge with DAG test
define amdgpu_kernel void @is_private_vgpr(i8* addrspace(1)* %ptr.ptr) { define amdgpu_kernel void @is_private_vgpr(i8* addrspace(1)* %ptr.ptr) {
; CI-LABEL: is_private_vgpr: ; CI-LABEL: is_private_vgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s0 ; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_load_dword s0, s[4:5], 0x11 ; CI-NEXT: s_load_dword s0, s[4:5], 0x11
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 ; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1
; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; CI-NEXT: flat_store_dword v[0:1], v0 ; CI-NEXT: flat_store_dword v[0:1], v0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: is_private_vgpr: ; GFX9-LABEL: is_private_vgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] ; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16)
; GFX9-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id
%ptr = load volatile i8*, i8* addrspace(1)* %gep %ptr = load volatile i8*, i8* addrspace(1)* %gep
%val = call i1 @llvm.amdgcn.is.private(i8* %ptr) %val = call i1 @llvm.amdgcn.is.private(i8* %ptr)
Show All 12 Lines
; CI-NEXT: s_cmp_lg_u32 s1, s0 ; CI-NEXT: s_cmp_lg_u32 s1, s0
; CI-NEXT: s_cselect_b32 s0, 1, 0 ; CI-NEXT: s_cselect_b32 s0, 1, 0
; CI-NEXT: s_and_b32 s0, s0, 1 ; CI-NEXT: s_and_b32 s0, s0, 1
; CI-NEXT: s_cmp_lg_u32 s0, 0 ; CI-NEXT: s_cmp_lg_u32 s0, 0
; CI-NEXT: s_cbranch_scc1 BB1_2 ; CI-NEXT: s_cbranch_scc1 BB1_2
; CI-NEXT: ; %bb.1: ; %bb0 ; CI-NEXT: ; %bb.1: ; %bb0
; CI-NEXT: v_mov_b32_e32 v0, 0 ; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: flat_store_dword v[0:1], v0 ; CI-NEXT: flat_store_dword v[0:1], v0
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: BB1_2: ; %bb1 ; CI-NEXT: BB1_2: ; %bb1
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: is_private_sgpr: ; GFX9-LABEL: is_private_sgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16) ; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 0, 16)
; GFX9-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: s_cmp_lg_u32 s1, s0 ; GFX9-NEXT: s_cmp_lg_u32 s1, s0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s0, s0, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cbranch_scc1 BB1_2 ; GFX9-NEXT: s_cbranch_scc1 BB1_2
; GFX9-NEXT: ; %bb.1: ; %bb0 ; GFX9-NEXT: ; %bb.1: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_2: ; %bb1 ; GFX9-NEXT: BB1_2: ; %bb1
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%val = call i1 @llvm.amdgcn.is.private(i8* %ptr) %val = call i1 @llvm.amdgcn.is.private(i8* %ptr)
br i1 %val, label %bb0, label %bb1 br i1 %val, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
br label %bb1 br label %bb1
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.is.shared.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=CI %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9 %s
; TODO: Merge with DAG test ; TODO: Merge with DAG test
define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) { define amdgpu_kernel void @is_local_vgpr(i8* addrspace(1)* %ptr.ptr) {
; CI-LABEL: is_local_vgpr: ; CI-LABEL: is_local_vgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s0 ; CI-NEXT: v_mov_b32_e32 v0, s0
; CI-NEXT: v_mov_b32_e32 v1, s1 ; CI-NEXT: v_mov_b32_e32 v1, s1
; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; CI-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_load_dword s0, s[4:5], 0x10 ; CI-NEXT: s_load_dword s0, s[4:5], 0x10
; CI-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 ; CI-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1
; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; CI-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; CI-NEXT: flat_store_dword v[0:1], v0 ; CI-NEXT: flat_store_dword v[0:1], v0
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: is_local_vgpr: ; GFX9-LABEL: is_local_vgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] ; GFX9-NEXT: global_load_dwordx2 v[0:1], v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1 ; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, s0, v1
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id %gep = getelementptr inbounds i8*, i8* addrspace(1)* %ptr.ptr, i32 %id
%ptr = load volatile i8*, i8* addrspace(1)* %gep %ptr = load volatile i8*, i8* addrspace(1)* %gep
%val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr)
Show All 12 Lines
; CI-NEXT: s_cmp_lg_u32 s1, s0 ; CI-NEXT: s_cmp_lg_u32 s1, s0
; CI-NEXT: s_cselect_b32 s0, 1, 0 ; CI-NEXT: s_cselect_b32 s0, 1, 0
; CI-NEXT: s_and_b32 s0, s0, 1 ; CI-NEXT: s_and_b32 s0, s0, 1
; CI-NEXT: s_cmp_lg_u32 s0, 0 ; CI-NEXT: s_cmp_lg_u32 s0, 0
; CI-NEXT: s_cbranch_scc1 BB1_2 ; CI-NEXT: s_cbranch_scc1 BB1_2
; CI-NEXT: ; %bb.1: ; %bb0 ; CI-NEXT: ; %bb.1: ; %bb0
; CI-NEXT: v_mov_b32_e32 v0, 0 ; CI-NEXT: v_mov_b32_e32 v0, 0
; CI-NEXT: flat_store_dword v[0:1], v0 ; CI-NEXT: flat_store_dword v[0:1], v0
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: BB1_2: ; %bb1 ; CI-NEXT: BB1_2: ; %bb1
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: is_local_sgpr: ; GFX9-LABEL: is_local_sgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[6:7], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-NEXT: s_getreg_b32 s0, hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9-NEXT: s_lshl_b32 s0, s0, 16 ; GFX9-NEXT: s_lshl_b32 s0, s0, 16
; GFX9-NEXT: s_cmp_lg_u32 s1, s0 ; GFX9-NEXT: s_cmp_lg_u32 s1, s0
; GFX9-NEXT: s_cselect_b32 s0, 1, 0 ; GFX9-NEXT: s_cselect_b32 s0, 1, 0
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s0, s0, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cbranch_scc1 BB1_2 ; GFX9-NEXT: s_cbranch_scc1 BB1_2
; GFX9-NEXT: ; %bb.1: ; %bb0 ; GFX9-NEXT: ; %bb.1: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_2: ; %bb1 ; GFX9-NEXT: BB1_2: ; %bb1
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%val = call i1 @llvm.amdgcn.is.shared(i8* %ptr) %val = call i1 @llvm.amdgcn.is.shared(i8* %ptr)
br i1 %val, label %bb0, label %bb1 br i1 %val, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* undef store volatile i32 0, i32 addrspace(1)* undef
br label %bb1 br label %bb1
Show All 9 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll

Show All 26 Lines
; CI-LABEL: s_trig_preop_f64: ; CI-LABEL: s_trig_preop_f64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; CI-NEXT: s_load_dword s2, s[4:5], 0x2 ; CI-NEXT: s_load_dword s2, s[4:5], 0x2
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v0, s2 ; CI-NEXT: v_mov_b32_e32 v0, s2
; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 ; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0
; CI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; VI-LABEL: s_trig_preop_f64: ; VI-LABEL: s_trig_preop_f64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; VI-NEXT: s_load_dword s2, s[4:5], 0x8 ; VI-NEXT: s_load_dword s2, s[4:5], 0x8
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 ; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0
; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: s_trig_preop_f64: ; GFX9-LABEL: s_trig_preop_f64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8 ; GFX9-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s2 ; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 ; GFX9-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0
; GFX9-NEXT: flat_store_dwordx2 v[0:1], v[0:1] ; GFX9-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b) %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 %b)
store volatile double %result, double* undef store volatile double %result, double* undef
ret void ret void
} }
define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) { define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) {
; GCN-LABEL: s_trig_preop_f64_imm: ; GCN-LABEL: s_trig_preop_f64_imm:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 ; GCN-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7
; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1] ; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7) %result = call double @llvm.amdgcn.trig.preop.f64(double %a, i32 7)
store volatile double %result, double* undef store volatile double %result, double* undef
ret void ret void
} }
declare double @llvm.amdgcn.trig.preop.f64(double, i32) #0 declare double @llvm.amdgcn.trig.preop.f64(double, i32) #0
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }

llvm/test/CodeGen/AMDGPU/GlobalISel/localizer.ll

Show All 11 Lines
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_xor_b32 s1, s1, -1 ; GFX9-NEXT: s_xor_b32 s1, s1, -1
; GFX9-NEXT: s_and_b32 s1, s1, 1 ; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0 ; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_cbranch_scc0 BB0_2 ; GFX9-NEXT: s_cbranch_scc0 BB0_2
; GFX9-NEXT: ; %bb.1: ; %bb1 ; GFX9-NEXT: ; %bb.1: ; %bb1
; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX9-NEXT: s_mov_b32 s0, 0 ; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB0_2: ; %Flow ; GFX9-NEXT: BB0_2: ; %Flow
; GFX9-NEXT: s_xor_b32 s0, s0, -1 ; GFX9-NEXT: s_xor_b32 s0, s0, -1
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s0, s0, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cbranch_scc1 BB0_4 ; GFX9-NEXT: s_cbranch_scc1 BB0_4
; GFX9-NEXT: ; %bb.3: ; %bb0 ; GFX9-NEXT: ; %bb.3: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b ; GFX9-NEXT: v_mov_b32_e32 v0, 0x7b
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c8
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e7
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x3e8
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x1c7
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6 ; GFX9-NEXT: v_mov_b32_e32 v0, 0x5be6
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB0_4: ; %bb2 ; GFX9-NEXT: BB0_4: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
entry: entry:
br i1 %cond, label %bb0, label %bb1 br i1 %cond, label %bb0, label %bb1
bb0: bb0:
store volatile i32 123, i32 addrspace(1)* undef store volatile i32 123, i32 addrspace(1)* undef
store volatile i32 456, i32 addrspace(1)* undef store volatile i32 456, i32 addrspace(1)* undef
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_addc_u32 s3, s3, gv3@gotpcrel32@hi+12 ; GFX9-NEXT: s_addc_u32 s3, s3, gv3@gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: s_mov_b32 s0, 0 ; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v0, v0, s[4:5] ; GFX9-NEXT: global_store_dword v0, v0, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v0, v1, s[2:3] ; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_2: ; %Flow ; GFX9-NEXT: BB1_2: ; %Flow
; GFX9-NEXT: s_xor_b32 s0, s0, -1 ; GFX9-NEXT: s_xor_b32 s0, s0, -1
; GFX9-NEXT: s_and_b32 s0, s0, 1 ; GFX9-NEXT: s_and_b32 s0, s0, 1
; GFX9-NEXT: s_cmp_lg_u32 s0, 0 ; GFX9-NEXT: s_cmp_lg_u32 s0, 0
; GFX9-NEXT: s_cbranch_scc1 BB1_4 ; GFX9-NEXT: s_cbranch_scc1 BB1_4
; GFX9-NEXT: ; %bb.3: ; %bb0 ; GFX9-NEXT: ; %bb.3: ; %bb0
; GFX9-NEXT: s_getpc_b64 s[0:1] ; GFX9-NEXT: s_getpc_b64 s[0:1]
; GFX9-NEXT: s_add_u32 s0, s0, gv0@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s0, s0, gv0@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s1, s1, gv0@gotpcrel32@hi+12 ; GFX9-NEXT: s_addc_u32 s1, s1, gv0@gotpcrel32@hi+12
; GFX9-NEXT: s_getpc_b64 s[2:3] ; GFX9-NEXT: s_getpc_b64 s[2:3]
; GFX9-NEXT: s_add_u32 s2, s2, gv1@gotpcrel32@lo+4 ; GFX9-NEXT: s_add_u32 s2, s2, gv1@gotpcrel32@lo+4
; GFX9-NEXT: s_addc_u32 s3, s3, gv1@gotpcrel32@hi+12 ; GFX9-NEXT: s_addc_u32 s3, s3, gv1@gotpcrel32@hi+12
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_store_dword v0, v0, s[0:1] ; GFX9-NEXT: global_store_dword v0, v0, s[0:1]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v0, v1, s[2:3] ; GFX9-NEXT: global_store_dword v0, v1, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_4: ; %bb2 ; GFX9-NEXT: BB1_4: ; %bb2
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
entry: entry:
br i1 %cond, label %bb0, label %bb1 br i1 %cond, label %bb0, label %bb1
bb0: bb0:
store volatile i32 0, i32 addrspace(1)* @gv0 store volatile i32 0, i32 addrspace(1)* @gv0
store volatile i32 1, i32 addrspace(1)* @gv1 store volatile i32 1, i32 addrspace(1)* @gv1
Show All 25 Lines
; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7] ; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[6:7]
; GFX9-NEXT: s_cbranch_execz BB2_2 ; GFX9-NEXT: s_cbranch_execz BB2_2
; GFX9-NEXT: ; %bb.1: ; %bb1 ; GFX9-NEXT: ; %bb.1: ; %bb1
; GFX9-NEXT: s_getpc_b64 s[6:7] ; GFX9-NEXT: s_getpc_b64 s[6:7]
; GFX9-NEXT: s_add_u32 s6, s6, static.gv2@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv2@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s7, s7, static.gv2@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv2@rel32@hi+12
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_store_dword v0, v0, s[6:7] ; GFX9-NEXT: global_store_dword v0, v0, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_getpc_b64 s[6:7] ; GFX9-NEXT: s_getpc_b64 s[6:7]
; GFX9-NEXT: s_add_u32 s6, s6, static.gv3@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv3@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s7, s7, static.gv3@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv3@rel32@hi+12
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: global_store_dword v0, v1, s[6:7] ; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB2_2: ; %Flow ; GFX9-NEXT: BB2_2: ; %Flow
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[4:5] ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], s[4:5]
; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_xor_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_cbranch_execz BB2_4 ; GFX9-NEXT: s_cbranch_execz BB2_4
; GFX9-NEXT: ; %bb.3: ; %bb0 ; GFX9-NEXT: ; %bb.3: ; %bb0
; GFX9-NEXT: s_getpc_b64 s[6:7] ; GFX9-NEXT: s_getpc_b64 s[6:7]
; GFX9-NEXT: s_add_u32 s6, s6, static.gv0@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv0@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s7, s7, static.gv0@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv0@rel32@hi+12
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: global_store_dword v0, v0, s[6:7] ; GFX9-NEXT: global_store_dword v0, v0, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_getpc_b64 s[6:7] ; GFX9-NEXT: s_getpc_b64 s[6:7]
; GFX9-NEXT: s_add_u32 s6, s6, static.gv1@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s6, s6, static.gv1@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s7, s7, static.gv1@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s7, s7, static.gv1@rel32@hi+12
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: global_store_dword v0, v1, s[6:7] ; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB2_4: ; %bb2 ; GFX9-NEXT: BB2_4: ; %bb2
; GFX9-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
entry: entry:
br i1 %cond, label %bb0, label %bb1 br i1 %cond, label %bb0, label %bb1
bb0: bb0:
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll

Show First 20 Lines • Show All 462 Lines • ▼ Show 20 Lines
define amdgpu_ps float @mubuf_load_sgpr_ptr(float addrspace(1)* inreg %ptr) { define amdgpu_ps float @mubuf_load_sgpr_ptr(float addrspace(1)* inreg %ptr) {
; GFX6-LABEL: mubuf_load_sgpr_ptr: ; GFX6-LABEL: mubuf_load_sgpr_ptr:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr: ; GFX7-LABEL: mubuf_load_sgpr_ptr:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%val = load volatile float, float addrspace(1)* %ptr %val = load volatile float, float addrspace(1)* %ptr
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095(float addrspace(1)* inreg %ptr) { define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095(float addrspace(1)* inreg %ptr) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4095: ; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4095:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc ; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], s4 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4095: ; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4095:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc ; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s4 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i64 4095 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4095
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4294967296(float addrspace(1)* inreg %ptr) { define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4294967296(float addrspace(1)* inreg %ptr) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4294967296: ; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4294967296:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s4, 0 ; GFX6-NEXT: s_mov_b32 s4, 0
; GFX6-NEXT: s_mov_b32 s5, 4 ; GFX6-NEXT: s_mov_b32 s5, 4
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, s4 ; GFX6-NEXT: s_mov_b32 s2, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s5 ; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4294967296: ; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4294967296:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s4, 0 ; GFX7-NEXT: s_mov_b32 s4, 0
; GFX7-NEXT: s_mov_b32 s5, 4 ; GFX7-NEXT: s_mov_b32 s5, 4
; GFX7-NEXT: v_mov_b32_e32 v0, s4 ; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, s4 ; GFX7-NEXT: s_mov_b32 s2, s4
; GFX7-NEXT: v_mov_b32_e32 v1, s5 ; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i64 4294967296 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4294967296
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4294967297(float addrspace(1)* inreg %ptr) { define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4294967297(float addrspace(1)* inreg %ptr) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4294967297: ; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4294967297:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s4, 4 ; GFX6-NEXT: s_mov_b32 s4, 4
; GFX6-NEXT: s_mov_b32 s5, s4 ; GFX6-NEXT: s_mov_b32 s5, s4
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: v_mov_b32_e32 v1, s5 ; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4294967297: ; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4294967297:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s4, 4 ; GFX7-NEXT: s_mov_b32 s4, 4
; GFX7-NEXT: s_mov_b32 s5, s4 ; GFX7-NEXT: s_mov_b32 s5, s4
; GFX7-NEXT: v_mov_b32_e32 v0, s4 ; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: v_mov_b32_e32 v1, s5 ; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i64 4294967297 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4294967297
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4096(float addrspace(1)* inreg %ptr) { define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4096(float addrspace(1)* inreg %ptr) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4096: ; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4096:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s2, -1 ; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_movk_i32 s4, 0x4000 ; GFX6-NEXT: s_movk_i32 s4, 0x4000
; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], s4 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4096: ; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4096:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, -1 ; GFX7-NEXT: s_mov_b32 s2, -1
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_movk_i32 s4, 0x4000 ; GFX7-NEXT: s_movk_i32 s4, 0x4000
; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; GFX7-NEXT: buffer_load_dword v0, off, s[0:3], s4 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i64 4096 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4096
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4095(float addrspace(1)* %ptr) { define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4095(float addrspace(1)* %ptr) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4095: ; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4095:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b64 s[0:1], 0 ; GFX6-NEXT: s_mov_b64 s[0:1], 0
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc ; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4095: ; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4095:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b64 s[0:1], 0 ; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc ; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i64 4095 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4095
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4294967296(float addrspace(1)* %ptr) { define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4294967296(float addrspace(1)* %ptr) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4294967296: ; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4294967296:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s0, 0 ; GFX6-NEXT: s_mov_b32 s0, 0
; GFX6-NEXT: s_mov_b32 s1, 4 ; GFX6-NEXT: s_mov_b32 s1, 4
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, s0 ; GFX6-NEXT: s_mov_b32 s2, s0
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4294967296: ; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4294967296:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s0, 0 ; GFX7-NEXT: s_mov_b32 s0, 0
; GFX7-NEXT: s_mov_b32 s1, 4 ; GFX7-NEXT: s_mov_b32 s1, 4
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, s0 ; GFX7-NEXT: s_mov_b32 s2, s0
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i64 4294967296 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4294967296
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4294967297(float addrspace(1)* %ptr) { define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4294967297(float addrspace(1)* %ptr) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4294967297: ; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4294967297:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s0, 4 ; GFX6-NEXT: s_mov_b32 s0, 4
; GFX6-NEXT: s_mov_b32 s1, s0 ; GFX6-NEXT: s_mov_b32 s1, s0
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4294967297: ; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4294967297:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s0, 4 ; GFX7-NEXT: s_mov_b32 s0, 4
; GFX7-NEXT: s_mov_b32 s1, s0 ; GFX7-NEXT: s_mov_b32 s1, s0
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i64 4294967297 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4294967297
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4096(float addrspace(1)* %ptr) { define amdgpu_ps float @mubuf_load_vgpr_ptr_offset4096(float addrspace(1)* %ptr) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4096: ; GFX6-LABEL: mubuf_load_vgpr_ptr_offset4096:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b64 s[0:1], 0 ; GFX6-NEXT: s_mov_b64 s[0:1], 0
; GFX6-NEXT: s_movk_i32 s4, 0x4000 ; GFX6-NEXT: s_movk_i32 s4, 0x4000
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4096: ; GFX7-LABEL: mubuf_load_vgpr_ptr_offset4096:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b64 s[0:1], 0 ; GFX7-NEXT: s_mov_b64 s[0:1], 0
; GFX7-NEXT: s_movk_i32 s4, 0x4000 ; GFX7-NEXT: s_movk_i32 s4, 0x4000
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i64 4096 %gep = getelementptr float, float addrspace(1)* %ptr, i64 4096
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_sgpr_offset(float addrspace(1)* inreg %ptr, i32 inreg %soffset) { define amdgpu_ps float @mubuf_load_sgpr_ptr_sgpr_offset(float addrspace(1)* inreg %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_sgpr_offset: ; GFX6-LABEL: mubuf_load_sgpr_ptr_sgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x200000
; GFX6-NEXT: s_lshl_b64 s[4:5], s[2:3], 2 ; GFX6-NEXT: s_lshl_b64 s[4:5], s[2:3], 2
; GFX6-NEXT: v_mov_b32_e32 v0, s4 ; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: v_mov_b32_e32 v1, s5 ; GFX6-NEXT: v_mov_b32_e32 v1, s5
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_sgpr_offset: ; GFX7-LABEL: mubuf_load_sgpr_ptr_sgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x200000
; GFX7-NEXT: s_lshl_b64 s[4:5], s[2:3], 2 ; GFX7-NEXT: s_lshl_b64 s[4:5], s[2:3], 2
; GFX7-NEXT: v_mov_b32_e32 v0, s4 ; GFX7-NEXT: v_mov_b32_e32 v0, s4
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: v_mov_b32_e32 v1, s5 ; GFX7-NEXT: v_mov_b32_e32 v1, s5
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %soffset %gep = getelementptr float, float addrspace(1)* %ptr, i32 %soffset
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset(float addrspace(1)* %ptr, i32 inreg %soffset) { define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset(float addrspace(1)* %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset: ; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset: ; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX7-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX7-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %soffset %gep = getelementptr float, float addrspace(1)* %ptr, i32 %soffset
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset_offset256(float addrspace(1)* %ptr, i32 inreg %soffset) { define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset_offset256(float addrspace(1)* %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256: ; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256: ; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX7-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX7-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 offset:1024 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep0 = getelementptr float, float addrspace(1)* %ptr, i32 %soffset %gep0 = getelementptr float, float addrspace(1)* %ptr, i32 %soffset
%gep1 = getelementptr float, float addrspace(1)* %gep0, i32 256 %gep1 = getelementptr float, float addrspace(1)* %gep0, i32 256
%val = load volatile float, float addrspace(1)* %gep1 %val = load volatile float, float addrspace(1)* %gep1
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset256_offset(float addrspace(1)* %ptr, i32 inreg %soffset) { define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset256_offset(float addrspace(1)* %ptr, i32 inreg %soffset) {
; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset: ; GFX6-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_movk_i32 s4, 0x400 ; GFX6-NEXT: s_movk_i32 s4, 0x400
; GFX6-NEXT: s_mov_b32 s5, 0 ; GFX6-NEXT: s_mov_b32 s5, 0
; GFX6-NEXT: v_mov_b32_e32 v2, s4 ; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX6-NEXT: v_mov_b32_e32 v3, s5 ; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX6-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, s5 ; GFX6-NEXT: s_mov_b32 s2, s5
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset: ; GFX7-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: s_movk_i32 s4, 0x400 ; GFX7-NEXT: s_movk_i32 s4, 0x400
; GFX7-NEXT: s_mov_b32 s5, 0 ; GFX7-NEXT: s_mov_b32 s5, 0
; GFX7-NEXT: v_mov_b32_e32 v2, s4 ; GFX7-NEXT: v_mov_b32_e32 v2, s4
; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000 ; GFX7-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x200000
; GFX7-NEXT: v_mov_b32_e32 v3, s5 ; GFX7-NEXT: v_mov_b32_e32 v3, s5
; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2 ; GFX7-NEXT: v_add_i32_e32 v0, vcc, v0, v2
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; GFX7-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; GFX7-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX7-NEXT: s_lshl_b64 s[0:1], s[0:1], 2
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_mov_b32 s2, s5 ; GFX7-NEXT: s_mov_b32 s2, s5
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 256 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 256
%gep1 = getelementptr float, float addrspace(1)* %gep0, i32 %soffset %gep1 = getelementptr float, float addrspace(1)* %gep0, i32 %soffset
%val = load volatile float, float addrspace(1)* %gep1 %val = load volatile float, float addrspace(1)* %gep1
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset(float addrspace(1)* inreg %ptr, i32 %voffset) { define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset(float addrspace(1)* inreg %ptr, i32 %voffset) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset: ; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset: ; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep = getelementptr float, float addrspace(1)* %ptr, i32 %voffset %gep = getelementptr float, float addrspace(1)* %ptr, i32 %voffset
%val = load volatile float, float addrspace(1)* %gep %val = load volatile float, float addrspace(1)* %gep
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset_offset4095(float addrspace(1)* inreg %ptr, i32 %voffset) { define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset_offset4095(float addrspace(1)* inreg %ptr, i32 %voffset) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095: ; GFX6-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; GFX6-NEXT: s_mov_b32 s0, s2 ; GFX6-NEXT: s_mov_b32 s0, s2
; GFX6-NEXT: s_mov_b32 s1, s3 ; GFX6-NEXT: s_mov_b32 s1, s3
; GFX6-NEXT: s_mov_b32 s2, 0 ; GFX6-NEXT: s_mov_b32 s2, 0
; GFX6-NEXT: s_mov_b32 s3, 0xf000 ; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_movk_i32 s4, 0x3ffc ; GFX6-NEXT: s_movk_i32 s4, 0x3ffc
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095: ; GFX7-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; GFX7-NEXT: s_mov_b32 s0, s2 ; GFX7-NEXT: s_mov_b32 s0, s2
; GFX7-NEXT: s_mov_b32 s1, s3 ; GFX7-NEXT: s_mov_b32 s1, s3
; GFX7-NEXT: s_mov_b32 s2, 0 ; GFX7-NEXT: s_mov_b32 s2, 0
; GFX7-NEXT: s_mov_b32 s3, 0xf000 ; GFX7-NEXT: s_mov_b32 s3, 0xf000
; GFX7-NEXT: s_movk_i32 s4, 0x3ffc ; GFX7-NEXT: s_movk_i32 s4, 0x3ffc
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[0:3], s4 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep0 = getelementptr float, float addrspace(1)* %ptr, i32 %voffset %gep0 = getelementptr float, float addrspace(1)* %ptr, i32 %voffset
%gep1 = getelementptr float, float addrspace(1)* %gep0, i64 4095 %gep1 = getelementptr float, float addrspace(1)* %gep0, i64 4095
%val = load volatile float, float addrspace(1)* %gep1 %val = load volatile float, float addrspace(1)* %gep1
ret float %val ret float %val
} }
define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095_vgpr_offset(float addrspace(1)* inreg %ptr, i32 %voffset) { define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095_vgpr_offset(float addrspace(1)* inreg %ptr, i32 %voffset) {
; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset: ; GFX6-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX6-NEXT: s_add_u32 s4, s2, 0x3ffc ; GFX6-NEXT: s_add_u32 s4, s2, 0x3ffc
; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; GFX6-NEXT: s_mov_b32 s6, 0 ; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_addc_u32 s5, s3, 0 ; GFX6-NEXT: s_addc_u32 s5, s3, 0
; GFX6-NEXT: s_mov_b32 s7, 0xf000 ; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 ; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset: ; GFX7-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset:
; GFX7: ; %bb.0: ; GFX7: ; %bb.0:
; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0
; GFX7-NEXT: s_add_u32 s4, s2, 0x3ffc ; GFX7-NEXT: s_add_u32 s4, s2, 0x3ffc
; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2 ; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2
; GFX7-NEXT: s_mov_b32 s6, 0 ; GFX7-NEXT: s_mov_b32 s6, 0
; GFX7-NEXT: s_addc_u32 s5, s3, 0 ; GFX7-NEXT: s_addc_u32 s5, s3, 0
; GFX7-NEXT: s_mov_b32 s7, 0xf000 ; GFX7-NEXT: s_mov_b32 s7, 0xf000
; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 ; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 glc
; GFX7-NEXT: s_waitcnt vmcnt(0) ; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: ; return to shader part epilog ; GFX7-NEXT: ; return to shader part epilog
%gep0 = getelementptr float, float addrspace(1)* %ptr, i64 4095 %gep0 = getelementptr float, float addrspace(1)* %ptr, i64 4095
%gep1 = getelementptr float, float addrspace(1)* %gep0, i32 %voffset %gep1 = getelementptr float, float addrspace(1)* %gep0, i32 %voffset
%val = load volatile float, float addrspace(1)* %gep1 %val = load volatile float, float addrspace(1)* %gep1
ret float %val ret float %val
} }
▲ Show 20 Lines • Show All 378 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/non-entry-alloca.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_u32_e32 v0, v2, v0 ; GCN-NEXT: v_add_u32_e32 v0, v2, v0
; GCN-NEXT: global_store_dword v1, v0, s[6:7] ; GCN-NEXT: global_store_dword v1, v0, s[6:7]
; GCN-NEXT: BB0_3: ; %bb.2 ; GCN-NEXT: BB0_3: ; %bb.2
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond0 = icmp eq i32 %arg.cond0, 0 %cond0 = icmp eq i32 %arg.cond0, 0
br i1 %cond0, label %bb.0, label %bb.2 br i1 %cond0, label %bb.0, label %bb.2
bb.0: bb.0:
%alloca = alloca [16 x i32], align 4, addrspace(5) %alloca = alloca [16 x i32], align 4, addrspace(5)
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: v_mov_b32_e32 v2, s4
; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen ; GCN-NEXT: buffer_load_dword v2, v2, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_u32_e32 v0, v2, v0 ; GCN-NEXT: v_add_u32_e32 v0, v2, v0
; GCN-NEXT: global_store_dword v1, v0, s[6:7] ; GCN-NEXT: global_store_dword v1, v0, s[6:7]
; GCN-NEXT: BB1_2: ; %bb.1 ; GCN-NEXT: BB1_2: ; %bb.1
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg.cond, 0 %cond = icmp eq i32 %arg.cond, 0
br i1 %cond, label %bb.0, label %bb.1 br i1 %cond, label %bb.0, label %bb.1
bb.0: bb.0:
%alloca = alloca [16 x i32], align 64, addrspace(5) %alloca = alloca [16 x i32], align 64, addrspace(5)
%gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0 %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v5 ; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v5
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_u32_e32 v2, v2, v3 ; GCN-NEXT: v_add_u32_e32 v2, v2, v3
; GCN-NEXT: global_store_dword v[0:1], v2, off ; GCN-NEXT: global_store_dword v[0:1], v2, off
; GCN-NEXT: BB2_3: ; %bb.2 ; GCN-NEXT: BB2_3: ; %bb.2
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_sub_u32 s32, s32, 0x400 ; GCN-NEXT: s_sub_u32 s32, s32, 0x400
; GCN-NEXT: s_mov_b32 s33, s8 ; GCN-NEXT: s_mov_b32 s33, s8
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%cond0 = icmp eq i32 %arg.cond0, 0 %cond0 = icmp eq i32 %arg.cond0, 0
br i1 %cond0, label %bb.0, label %bb.2 br i1 %cond0, label %bb.0, label %bb.2
bb.0: bb.0:
%alloca = alloca [16 x i32], align 4, addrspace(5) %alloca = alloca [16 x i32], align 4, addrspace(5)
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v4 ; GCN-NEXT: v_and_b32_e32 v3, 0x3ff, v4
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_u32_e32 v2, v2, v3 ; GCN-NEXT: v_add_u32_e32 v2, v2, v3
; GCN-NEXT: global_store_dword v[0:1], v2, off ; GCN-NEXT: global_store_dword v[0:1], v2, off
; GCN-NEXT: BB3_2: ; %bb.1 ; GCN-NEXT: BB3_2: ; %bb.1
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: global_store_dword v[0:1], v0, off ; GCN-NEXT: global_store_dword v[0:1], v0, off
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_sub_u32 s32, s32, 0x2000 ; GCN-NEXT: s_sub_u32 s32, s32, 0x2000
; GCN-NEXT: s_mov_b32 s33, s8 ; GCN-NEXT: s_mov_b32 s33, s8
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%cond = icmp eq i32 %arg.cond, 0 %cond = icmp eq i32 %arg.cond, 0
br i1 %cond, label %bb.0, label %bb.1 br i1 %cond, label %bb.0, label %bb.1
bb.0: bb.0:
%alloca = alloca [16 x i32], align 64, addrspace(5) %alloca = alloca [16 x i32], align 64, addrspace(5)
%gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0 %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/amdgcn-ieee.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}kernel_ieee_mode_default: ; GCN-LABEL: {{^}}kernel_ieee_mode_default:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]] ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]] ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define amdgpu_kernel void @kernel_ieee_mode_default() #0 { define amdgpu_kernel void @kernel_ieee_mode_default() #0 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}kernel_ieee_mode_on: ; GCN-LABEL: {{^}}kernel_ieee_mode_on:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]] ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]] ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define amdgpu_kernel void @kernel_ieee_mode_on() #1 { define amdgpu_kernel void @kernel_ieee_mode_on() #1 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}kernel_ieee_mode_off: ; GCN-LABEL: {{^}}kernel_ieee_mode_off:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-NOT: [[VAL0]] ; GCN-NOT: [[VAL0]]
; GCN-NOT: [[VAL1]] ; GCN-NOT: [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define amdgpu_kernel void @kernel_ieee_mode_off() #2 { define amdgpu_kernel void @kernel_ieee_mode_off() #2 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}func_ieee_mode_default: ; GCN-LABEL: {{^}}func_ieee_mode_default:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]] ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]] ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define void @func_ieee_mode_default() #0 { define void @func_ieee_mode_default() #0 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}func_ieee_mode_on: ; GCN-LABEL: {{^}}func_ieee_mode_on:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]] ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]] ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define void @func_ieee_mode_on() #1 { define void @func_ieee_mode_on() #1 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}func_ieee_mode_off: ; GCN-LABEL: {{^}}func_ieee_mode_off:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-NOT: [[VAL0]] ; GCN-NOT: [[VAL0]]
; GCN-NOT: [[VAL1]] ; GCN-NOT: [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define void @func_ieee_mode_off() #2 { define void @func_ieee_mode_off() #2 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}cs_ieee_mode_default: ; GCN-LABEL: {{^}}cs_ieee_mode_default:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-NOT: [[VAL0]] ; GCN-NOT: [[VAL0]]
; GCN-NOT: [[VAL1]] ; GCN-NOT: [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define amdgpu_cs void @cs_ieee_mode_default() #0 { define amdgpu_cs void @cs_ieee_mode_default() #0 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}cs_ieee_mode_on: ; GCN-LABEL: {{^}}cs_ieee_mode_on:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]] ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]] ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define amdgpu_cs void @cs_ieee_mode_on() #1 { define amdgpu_cs void @cs_ieee_mode_on() #1 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}cs_ieee_mode_off: ; GCN-LABEL: {{^}}cs_ieee_mode_off:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-NOT: [[VAL0]] ; GCN-NOT: [[VAL0]]
; GCN-NOT: [[VAL1]] ; GCN-NOT: [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define amdgpu_cs void @cs_ieee_mode_off() #2 { define amdgpu_cs void @cs_ieee_mode_off() #2 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}ps_ieee_mode_default: ; GCN-LABEL: {{^}}ps_ieee_mode_default:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-NOT: [[VAL0]] ; GCN-NOT: [[VAL0]]
; GCN-NOT: [[VAL1]] ; GCN-NOT: [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define amdgpu_ps void @ps_ieee_mode_default() #0 { define amdgpu_ps void @ps_ieee_mode_default() #0 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}ps_ieee_mode_on: ; GCN-LABEL: {{^}}ps_ieee_mode_on:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]] ; GCN-DAG: v_mul_f32_e32 [[QUIET0:v[0-9]+]], 1.0, [[VAL0]]
; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]] ; GCN-DAG: v_mul_f32_e32 [[QUIET1:v[0-9]+]], 1.0, [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[QUIET0]], [[QUIET1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define amdgpu_ps void @ps_ieee_mode_on() #1 { define amdgpu_ps void @ps_ieee_mode_on() #1 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
store volatile float %min, float addrspace(1)* undef store volatile float %min, float addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}ps_ieee_mode_off: ; GCN-LABEL: {{^}}ps_ieee_mode_off:
; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL0:v[0-9]+]]
; GCN-NEXT: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]] ; GCN: {{buffer|global|flat}}_load_dword [[VAL1:v[0-9]+]]
; GCN-NOT: [[VAL0]] ; GCN-NOT: [[VAL0]]
; GCN-NOT: [[VAL1]] ; GCN-NOT: [[VAL1]]
; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]] ; GCN: v_min_f32_e32 [[MIN:v[0-9]+]], [[VAL0]], [[VAL1]]
; GCN-NOT: v_mul_f32 ; GCN-NOT: v_mul_f32
define amdgpu_ps void @ps_ieee_mode_off() #2 { define amdgpu_ps void @ps_ieee_mode_off() #2 {
%val0 = load volatile float, float addrspace(1)* undef %val0 = load volatile float, float addrspace(1)* undef
%val1 = load volatile float, float addrspace(1)* undef %val1 = load volatile float, float addrspace(1)* undef
%min = call float @llvm.minnum.f32(float %val0, float %val1) %min = call float @llvm.minnum.f32(float %val0, float %val1)
Show All 10 Lines

llvm/test/CodeGen/AMDGPU/branch-relaxation-gfx10-branch-offset-bug.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1030 %s ; RUN: llc -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1030 %s
; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1010 %s ; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs -amdgpu-s-branch-bits=7 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX1010 %s
; For gfx1010, overestimate the branch size in case we need to insert ; For gfx1010, overestimate the branch size in case we need to insert
; a nop for the buggy offset. ; a nop for the buggy offset.
; GCN-LABEL: long_forward_scc_branch_3f_offset_bug: ; GCN-LABEL: long_forward_scc_branch_3f_offset_bug:
; GFX1030: s_cmp_lg_u32 ; GFX1030: s_cmp_lg_u32
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/branch-relaxation.ll

Show First 20 Lines • Show All 239 Lines • ▼ Show 20 Lines
; GCN: ;;#ASMEND ; GCN: ;;#ASMEND
; GCN: [[BB3]]: ; GCN: [[BB3]]:
; GCN: v_mov_b32_e32 [[BB2_K:v[0-9]+]], 17 ; GCN: v_mov_b32_e32 [[BB2_K:v[0-9]+]], 17
; GCN: buffer_store_dword [[BB2_K]] ; GCN: buffer_store_dword [[BB2_K]]
; GCN: v_mov_b32_e32 [[BB4_K:v[0-9]+]], 63 ; GCN: v_mov_b32_e32 [[BB4_K:v[0-9]+]], 63
; GCN: buffer_store_dword [[BB4_K]] ; GCN: buffer_store_dword [[BB4_K]]
; GCN-NEXT: s_endpgm ; GCN: s_endpgm
; GCN-NEXT: .Lfunc_end{{[0-9]+}}: ; GCN-NEXT: .Lfunc_end{{[0-9]+}}:
define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %arg1) { define amdgpu_kernel void @uniform_unconditional_min_long_forward_branch(i32 addrspace(1)* %arg, i32 %arg1) {
bb0: bb0:
%tmp = icmp ne i32 %arg1, 0 %tmp = icmp ne i32 %arg1, 0
br i1 %tmp, label %bb2, label %bb3 br i1 %tmp, label %bb2, label %bb3
bb2: bb2:
store volatile i32 17, i32 addrspace(1)* undef store volatile i32 17, i32 addrspace(1)* undef
▲ Show 20 Lines • Show All 277 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/byval-frame-setup.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope --check-prefix=GCN %s
%struct.ByValStruct = type { [4 x i32] } %struct.ByValStruct = type { [4 x i32] }
; Make sure the offset is folded and function's frame register is used ; Make sure the offset is folded and function's frame register is used
; rather than the global scratch wave offset. ; rather than the global scratch wave offset.
; GCN-LABEL: {{^}}void_func_byval_struct_use_outside_entry_block: ; GCN-LABEL: {{^}}void_func_byval_struct_use_outside_entry_block:
; GCN-NOT: v_lshrrev_b32 ; GCN-NOT: v_lshrrev_b32
; GCN-NOT: s_sub_u32 ; GCN-NOT: s_sub_u32
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: s_cbranch_execz [[BB1:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_execz [[BB1:BB[0-9]+_[0-9]+]]
; GCN: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s32{{$}} ; GCN: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s32 glc{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], s32{{$}} ; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], s32{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s32 offset:16{{$}} ; GCN: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s32 offset:16 glc{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_store_dword [[LOAD1]], off, s[0:3], s32 offset:16{{$}} ; GCN: buffer_store_dword [[LOAD1]], off, s[0:3], s32 offset:16{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: [[BB1]] ; GCN: [[BB1]]
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
define hidden void @void_func_byval_struct_use_outside_entry_block(%struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg1, i1 %cond) #1 { define hidden void @void_func_byval_struct_use_outside_entry_block(%struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval(%struct.ByValStruct) noalias nocapture align 4 %arg1, i1 %cond) #1 {
entry: entry:
Show All 25 Lines

llvm/test/CodeGen/AMDGPU/call-argument-types.ll

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; HSA: buffer_load_ubyte [[VAR:v[0-9]+]] ; HSA: buffer_load_ubyte [[VAR:v[0-9]+]]
; HSA: s_mov_b32 s32, 0 ; HSA: s_mov_b32 s32, 0
; MESA-DAG: buffer_load_ubyte [[VAR:v[0-9]+]] ; MESA-DAG: buffer_load_ubyte [[VAR:v[0-9]+]]
; MESA-DAG: s_mov_b32 s32, 0{{$}} ; MESA-DAG: s_mov_b32 s32, 0{{$}}
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_signext@rel32@lo+4 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_signext@rel32@lo+4
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_signext@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_signext@rel32@hi+12
; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: v_bfe_i32 v0, v0, 0, 1 ; GCN-NEXT: v_bfe_i32 v0, v0, 0, 1
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i1_signext(i32) #0 {
%var = load volatile i1, i1 addrspace(1)* undef %var = load volatile i1, i1 addrspace(1)* undef
call void @external_void_func_i1_signext(i1 %var) call void @external_void_func_i1_signext(i1 %var)
ret void ret void
} }
; FIXME: load should be scheduled before getpc ; FIXME: load should be scheduled before getpc
; GCN-LABEL: {{^}}test_call_external_void_func_i1_zeroext: ; GCN-LABEL: {{^}}test_call_external_void_func_i1_zeroext:
; HSA: buffer_load_ubyte v0 ; HSA: buffer_load_ubyte v0
; HSA-DAG: s_mov_b32 s32, 0{{$}} ; HSA-DAG: s_mov_b32 s32, 0{{$}}
; MESA: buffer_load_ubyte v0 ; MESA: buffer_load_ubyte v0
; MESA-DAG: s_mov_b32 s32, 0{{$}} ; MESA-DAG: s_mov_b32 s32, 0{{$}}
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_zeroext@rel32@lo+4 ; GCN-NEXT: s_add_u32 s[[PC_LO]], s[[PC_LO]], external_void_func_i1_zeroext@rel32@lo+4
; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_zeroext@rel32@hi+12 ; GCN-NEXT: s_addc_u32 s[[PC_HI]], s[[PC_HI]], external_void_func_i1_zeroext@rel32@hi+12
; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: v_and_b32_e32 v0, 1, v0 ; GCN-NEXT: v_and_b32_e32 v0, 1, v0
; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}} ; GCN-NEXT: s_swappc_b64 s[30:31], s{{\[}}[[PC_LO]]:[[PC_HI]]{{\]}}
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_i1_zeroext(i32) #0 {
%var = load volatile i1, i1 addrspace(1)* undef %var = load volatile i1, i1 addrspace(1)* undef
call void @external_void_func_i1_zeroext(i1 %var) call void @external_void_func_i1_zeroext(i1 %var)
ret void ret void
} }
▲ Show 20 Lines • Show All 794 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; MUBUF-NEXT: s_mov_b32 [[FP_COPY:s4]], s33 ; MUBUF-NEXT: s_mov_b32 [[FP_COPY:s4]], s33
; FLATSCR-NEXT: s_mov_b32 [[FP_COPY:s0]], s33 ; FLATSCR-NEXT: s_mov_b32 [[FP_COPY:s0]], s33
; GCN-NEXT: s_mov_b32 s33, s32 ; GCN-NEXT: s_mov_b32 s33, s32
; MUBUF-NEXT: s_add_u32 s32, s32, 0x200 ; MUBUF-NEXT: s_add_u32 s32, s32, 0x200
; FLATSCR-NEXT: s_add_u32 s32, s32, 8 ; FLATSCR-NEXT: s_add_u32 s32, s32, 8
; GCN-NEXT: v_mov_b32_e32 v0, 0{{$}} ; GCN-NEXT: v_mov_b32_e32 v0, 0{{$}}
; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4{{$}} ; MUBUF-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4{{$}}
; FLATSCR-NEXT: scratch_store_dword off, v0, s33 offset:4{{$}} ; FLATSCR-NEXT: scratch_store_dword off, v0, s33 offset:4{{$}}
; GCN-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_sub_u32 s32, s32, 0x200 ; MUBUF-NEXT: s_sub_u32 s32, s32, 0x200
; FLATSCR-NEXT: s_sub_u32 s32, s32, 8 ; FLATSCR-NEXT: s_sub_u32 s32, s32, 8
; GCN-NEXT: s_mov_b32 s33, [[FP_COPY]] ; GCN-NEXT: s_mov_b32 s33, [[FP_COPY]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @callee_with_stack_no_fp_elim_all() #1 { define void @callee_with_stack_no_fp_elim_all() #1 {
%alloca = alloca i32, addrspace(5) %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
ret void ret void
} }
; GCN-LABEL: {{^}}callee_with_stack_no_fp_elim_non_leaf: ; GCN-LABEL: {{^}}callee_with_stack_no_fp_elim_non_leaf:
▲ Show 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
; FLATSCR-NEXT: s_mov_b32 [[FP_COPY:s0]], s33 ; FLATSCR-NEXT: s_mov_b32 [[FP_COPY:s0]], s33
; MUBUF-NEXT: s_and_b32 s33, [[SCRATCH]], 0xfff80000 ; MUBUF-NEXT: s_and_b32 s33, [[SCRATCH]], 0xfff80000
; FLATSCR-NEXT: s_and_b32 s33, [[SCRATCH]], 0xffffe000 ; FLATSCR-NEXT: s_and_b32 s33, [[SCRATCH]], 0xffffe000
; MUBUF-NEXT: s_add_u32 s32, s32, 0x100000 ; MUBUF-NEXT: s_add_u32 s32, s32, 0x100000
; FLATSCR-NEXT: s_add_u32 s32, s32, 0x4000 ; FLATSCR-NEXT: s_add_u32 s32, s32, 0x4000
; GCN-NEXT: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 ; GCN-NEXT: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
; MUBUF-NEXT: buffer_store_dword [[ZERO]], off, s[0:3], s33 ; MUBUF-NEXT: buffer_store_dword [[ZERO]], off, s[0:3], s33
; FLATSCR-NEXT: scratch_store_dword off, [[ZERO]], s33 ; FLATSCR-NEXT: scratch_store_dword off, [[ZERO]], s33
; GCN-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_sub_u32 s32, s32, 0x100000 ; MUBUF-NEXT: s_sub_u32 s32, s32, 0x100000
; FLATSCR-NEXT: s_sub_u32 s32, s32, 0x4000 ; FLATSCR-NEXT: s_sub_u32 s32, s32, 0x4000
; GCN-NEXT: s_mov_b32 s33, [[FP_COPY]] ; GCN-NEXT: s_mov_b32 s33, [[FP_COPY]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @realign_stack_no_fp_elim() #1 { define void @realign_stack_no_fp_elim() #1 {
%alloca = alloca i32, align 8192, addrspace(5) %alloca = alloca i32, align 8192, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
ret void ret void
} }
; GCN-LABEL: {{^}}no_unused_non_csr_sgpr_for_fp: ; GCN-LABEL: {{^}}no_unused_non_csr_sgpr_for_fp:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: v_writelane_b32 v1, s33, 2 ; GCN-NEXT: v_writelane_b32 v1, s33, 2
; GCN-NEXT: v_writelane_b32 v1, s30, 0 ; GCN-NEXT: v_writelane_b32 v1, s30, 0
; GCN-NEXT: s_mov_b32 s33, s32 ; GCN-NEXT: s_mov_b32 s33, s32
; GCN: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0 ; GCN: v_mov_b32_e32 [[ZERO:v[0-9]+]], 0
; GCN: v_writelane_b32 v1, s31, 1 ; GCN: v_writelane_b32 v1, s31, 1
; MUBUF: buffer_store_dword [[ZERO]], off, s[0:3], s33 offset:4 ; MUBUF: buffer_store_dword [[ZERO]], off, s[0:3], s33 offset:4
; FLATSCR: scratch_store_dword off, [[ZERO]], s33 offset:4 ; FLATSCR: scratch_store_dword off, [[ZERO]], s33 offset:4
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN: ;;#ASMSTART ; GCN: ;;#ASMSTART
; MUBUF: v_readlane_b32 s4, v1, 0 ; MUBUF: v_readlane_b32 s4, v1, 0
; MUBUF-NEXT: s_add_u32 s32, s32, 0x200 ; MUBUF-NEXT: s_add_u32 s32, s32, 0x200
; MUBUF-NEXT: v_readlane_b32 s5, v1, 1 ; MUBUF-NEXT: v_readlane_b32 s5, v1, 1
; FLATSCR: v_readlane_b32 s0, v1, 0 ; FLATSCR: v_readlane_b32 s0, v1, 0
; FLATSCR-NEXT: s_add_u32 s32, s32, 8 ; FLATSCR-NEXT: s_add_u32 s32, s32, 8
; FLATSCR-NEXT: v_readlane_b32 s1, v1, 1 ; FLATSCR-NEXT: v_readlane_b32 s1, v1, 1
; MUBUF-NEXT: s_sub_u32 s32, s32, 0x200 ; MUBUF-NEXT: s_sub_u32 s32, s32, 0x200
; FLATSCR-NEXT: s_sub_u32 s32, s32, 8 ; FLATSCR-NEXT: s_sub_u32 s32, s32, 8
; GCN-NEXT: v_readlane_b32 s33, v1, 2 ; GCN-NEXT: v_readlane_b32 s33, v1, 2
; GCN-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_setpc_b64 s[4:5] ; MUBUF-NEXT: s_setpc_b64 s[4:5]
; FLATSCR-NEXT: s_setpc_b64 s[0:1] ; FLATSCR-NEXT: s_setpc_b64 s[0:1]
define void @no_unused_non_csr_sgpr_for_fp() #1 { define void @no_unused_non_csr_sgpr_for_fp() #1 {
%alloca = alloca i32, addrspace(5) %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
; Use all clobberable registers, so FP has to spill to a VGPR. ; Use all clobberable registers, so FP has to spill to a VGPR.
call void asm sideeffect "", call void asm sideeffect "",
▲ Show 20 Lines • Show All 251 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll

Show First 20 Lines • Show All 393 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @kern_indirect_other_arg_use_workitem_id_z() #1 {
call void @other_arg_use_workitem_id_z(i32 555) call void @other_arg_use_workitem_id_z(i32 555)
ret void ret void
} }
; GCN-LABEL: {{^}}too_many_args_use_workitem_id_x: ; GCN-LABEL: {{^}}too_many_args_use_workitem_id_x:
; VARABI: buffer_load_dword v32, off, s[0:3], s32{{$}} ; VARABI: buffer_load_dword v32, off, s[0:3], s32{{$}}
; VARABI: v_and_b32_e32 v32, 0x3ff, v32 ; VARABI: v_and_b32_e32 v32, 0x3ff, v32
; VARABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, v32 ; VARABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, v32
; VARABI: s_setpc_b64
; VARABI: s_waitcnt
; VARABI-NEXT: s_setpc_b64
; FIXEDABI: v_and_b32_e32 v31, 0x3ff, v31 ; FIXEDABI: v_and_b32_e32 v31, 0x3ff, v31
; FIXEDABI: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32{{$}} ; FIXEDABI: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32{{$}}
define void @too_many_args_use_workitem_id_x( define void @too_many_args_use_workitem_id_x(
i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7,
i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31) #1 { i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31) #1 {
▲ Show 20 Lines • Show All 127 Lines • ▼ Show 20 Lines
; frame[1] = stack passed workitem ID x ; frame[1] = stack passed workitem ID x
; frame[2] = VGPR spill slot ; frame[2] = VGPR spill slot
; GCN-LABEL: {{^}}too_many_args_use_workitem_id_x_byval: ; GCN-LABEL: {{^}}too_many_args_use_workitem_id_x_byval:
; VARABI: buffer_load_dword v32, off, s[0:3], s32 offset:4 ; VARABI: buffer_load_dword v32, off, s[0:3], s32 offset:4
; VARABI-NEXT: s_waitcnt ; VARABI-NEXT: s_waitcnt
; VARABI-NEXT: v_and_b32_e32 v32, 0x3ff, v32 ; VARABI-NEXT: v_and_b32_e32 v32, 0x3ff, v32
; VARABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, v32 ; VARABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, v32
; VARABI: buffer_load_dword v0, off, s[0:3], s32{{$}} ; VARABI: buffer_load_dword v0, off, s[0:3], s32 glc{{$}}
; VARABI: s_setpc_b64 ; VARABI: s_setpc_b64
; FIXEDABI: v_and_b32_e32 v31, 0x3ff, v31 ; FIXEDABI: v_and_b32_e32 v31, 0x3ff, v31
; FIXEDABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, v31 ; FIXEDABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, v31
; FIXEDABI: buffer_load_dword v0, off, s[0:3], s32{{$}} ; FIXEDABI: buffer_load_dword v0, off, s[0:3], s32{{$}}
; FIXEDABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; FIXEDABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; FIXEDABI: buffer_load_dword v0, off, s[0:3], s32 offset:4{{$}} ; FIXEDABI: buffer_load_dword v0, off, s[0:3], s32 offset:4 glc{{$}}
; FIXEDABI: s_setpc_b64 ; FIXEDABI: s_setpc_b64
define void @too_many_args_use_workitem_id_x_byval( define void @too_many_args_use_workitem_id_x_byval(
i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7,
i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval(i32) %arg32) #1 { i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval(i32) %arg32) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x() %val = call i32 @llvm.amdgcn.workitem.id.x()
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
▲ Show 20 Lines • Show All 133 Lines • ▼ Show 20 Lines
; VARABI: v_and_b32_e32 [[AND_X:v[0-9]+]], 0x3ff, v32 ; VARABI: v_and_b32_e32 [[AND_X:v[0-9]+]], 0x3ff, v32
; VARABI-NOT: buffer_load_dword ; VARABI-NOT: buffer_load_dword
; VARABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[AND_X]] ; VARABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[AND_X]]
; VARABI-NOT: buffer_load_dword ; VARABI-NOT: buffer_load_dword
; VARABI: v_bfe_u32 [[BFE_Y:v[0-9]+]], v32, 10, 10 ; VARABI: v_bfe_u32 [[BFE_Y:v[0-9]+]], v32, 10, 10
; VARABI-NEXT: v_bfe_u32 [[BFE_Z:v[0-9]+]], v32, 20, 10 ; VARABI-NEXT: v_bfe_u32 [[BFE_Z:v[0-9]+]], v32, 20, 10
; VARABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[BFE_Y]] ; VARABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[BFE_Y]]
; VARABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[BFE_Z]] ; VARABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[BFE_Z]]
; VARABI: s_setpc_b64
; VARABI: s_waitcnt
; VARABI-NEXT: s_setpc_b64
; FIXEDABI: v_and_b32_e32 [[AND_X:v[0-9]+]], 0x3ff, v31 ; FIXEDABI: v_and_b32_e32 [[AND_X:v[0-9]+]], 0x3ff, v31
; FIXEDABI-NOT: buffer_load_dword ; FIXEDABI-NOT: buffer_load_dword
; FIXEDABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[AND_X]] ; FIXEDABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[AND_X]]
; FIXEDABI-NOT: buffer_load_dword ; FIXEDABI-NOT: buffer_load_dword
; FIXEDABI: v_bfe_u32 [[BFE_Y:v[0-9]+]], v31, 10, 10 ; FIXEDABI: v_bfe_u32 [[BFE_Y:v[0-9]+]], v31, 10, 10
; FIXEDABI-NEXT: v_bfe_u32 [[BFE_Z:v[0-9]+]], v31, 20, 10 ; FIXEDABI-NEXT: v_bfe_u32 [[BFE_Z:v[0-9]+]], v31, 20, 10
; FIXEDABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[BFE_Y]] ; FIXEDABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[BFE_Y]]
; FIXEDABI-NEXT: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[BFE_Z]] ; FIXEDABI: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[BFE_Z]]
define void @too_many_args_use_workitem_id_xyz( define void @too_many_args_use_workitem_id_xyz(
i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7,
i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31) #1 { i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31) #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x() %val0 = call i32 @llvm.amdgcn.workitem.id.x()
store volatile i32 %val0, i32 addrspace(1)* undef store volatile i32 %val0, i32 addrspace(1)* undef
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}too_many_args_use_workitem_id_x_stack_yz: ; GCN-LABEL: {{^}}too_many_args_use_workitem_id_x_stack_yz:
; GCN-DAG: v_and_b32_e32 [[IDX:v[0-9]+]], 0x3ff, v31 ; GCN-DAG: v_and_b32_e32 [[IDX:v[0-9]+]], 0x3ff, v31
; GCN-DAG: {{flat|global}}_store_dword v[0:1], [[IDX]] ; GCN-DAG: {{flat|global}}_store_dword v[0:1], [[IDX]]
; GCN-DAG: v_bfe_u32 [[IDY:v[0-9]+]], v31, 10, 10 ; GCN-DAG: v_bfe_u32 [[IDY:v[0-9]+]], v31, 10, 10
; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[IDY]] ; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[IDY]]
; GCN-DAG: v_bfe_u32 [[IDZ:v[0-9]+]], v31, 20, 10 ; GCN-DAG: v_bfe_u32 [[IDZ:v[0-9]+]], v31, 20, 10
; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[IDZ]] ; GCN-DAG: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+]}}, [[IDZ]]
; GCN: s_setpc_b64
; GCN: s_waitcnt
; GCN-NEXT: s_setpc_b64
; GCN: ScratchSize: 0 ; GCN: ScratchSize: 0
define void @too_many_args_use_workitem_id_x_stack_yz( define void @too_many_args_use_workitem_id_x_stack_yz(
i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7,
i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30) #1 { i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30) #1 {
%val0 = call i32 @llvm.amdgcn.workitem.id.x() %val0 = call i32 @llvm.amdgcn.workitem.id.x()
store volatile i32 %val0, i32 addrspace(1)* undef store volatile i32 %val0, i32 addrspace(1)* undef
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/cc-update.ll

Show All 23 Lines
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_add_u32 s4, s4, s7 ; GFX803-NEXT: s_add_u32 s4, s4, s7
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8 ; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; GFX803-NEXT: s_add_u32 s0, s0, s7 ; GFX803-NEXT: s_add_u32 s0, s0, s7
; GFX803-NEXT: s_addc_u32 s1, s1, 0 ; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_mov_b32_e32 v0, 0 ; GFX803-NEXT: v_mov_b32_e32 v0, 0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5 ; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5
; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_endpgm ; GFX803-NEXT: s_endpgm
; ;
; GFX900-LABEL: test_kern_stack: ; GFX900-LABEL: test_kern_stack:
; GFX900: ; %bb.0: ; %entry ; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7 ; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7
; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX900-NEXT: s_add_u32 s0, s0, s7 ; GFX900-NEXT: s_add_u32 s0, s0, s7
; GFX900-NEXT: s_addc_u32 s1, s1, 0 ; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX1010-LABEL: test_kern_stack: ; GFX1010-LABEL: test_kern_stack:
; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: s_endpgm
entry: entry:
%x = alloca i32, align 4, addrspace(5) %x = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %x, align 4 store volatile i32 0, i32 addrspace(5)* %x, align 4
ret void ret void
} }
define amdgpu_kernel void @test_kern_call() local_unnamed_addr #0 { define amdgpu_kernel void @test_kern_call() local_unnamed_addr #0 {
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; GFX803-NEXT: s_addc_u32 s1, s1, 0 ; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_mov_b32_e32 v0, 0 ; GFX803-NEXT: v_mov_b32_e32 v0, 0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5 ; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5
; GFX803-NEXT: s_getpc_b64 s[4:5] ; GFX803-NEXT: s_getpc_b64 s[4:5]
; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12 ; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX803-NEXT: s_movk_i32 s32, 0x400 ; GFX803-NEXT: s_movk_i32 s32, 0x400
; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX803-NEXT: s_endpgm ; GFX803-NEXT: s_endpgm
; ;
; GFX900-LABEL: test_kern_stack_and_call: ; GFX900-LABEL: test_kern_stack_and_call:
; GFX900: ; %bb.0: ; %entry ; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7 ; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7
; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX900-NEXT: s_add_u32 s0, s0, s7 ; GFX900-NEXT: s_add_u32 s0, s0, s7
; GFX900-NEXT: s_addc_u32 s1, s1, 0 ; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: s_getpc_b64 s[4:5] ; GFX900-NEXT: s_getpc_b64 s[4:5]
; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12 ; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX900-NEXT: s_movk_i32 s32, 0x400 ; GFX900-NEXT: s_movk_i32 s32, 0x400
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX1010-LABEL: test_kern_stack_and_call: ; GFX1010-LABEL: test_kern_stack_and_call:
; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_movk_i32 s32, 0x200 ; GFX1010-NEXT: s_movk_i32 s32, 0x200
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5] ; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12 ; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: s_endpgm
entry: entry:
%x = alloca i32, align 4, addrspace(5) %x = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %x, align 4 store volatile i32 0, i32 addrspace(5)* %x, align 4
tail call void @ex() #0 tail call void @ex() #0
ret void ret void
} }
Show All 23 Lines
; GFX803-NEXT: s_add_u32 s4, s4, s7 ; GFX803-NEXT: s_add_u32 s4, s4, s7
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8 ; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; GFX803-NEXT: s_add_u32 s0, s0, s7 ; GFX803-NEXT: s_add_u32 s0, s0, s7
; GFX803-NEXT: s_mov_b32 s33, 0 ; GFX803-NEXT: s_mov_b32 s33, 0
; GFX803-NEXT: s_addc_u32 s1, s1, 0 ; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_mov_b32_e32 v0, 0 ; GFX803-NEXT: v_mov_b32_e32 v0, 0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5 ; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5
; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_endpgm ; GFX803-NEXT: s_endpgm
; ;
; GFX900-LABEL: test_force_fp_kern_stack: ; GFX900-LABEL: test_force_fp_kern_stack:
; GFX900: ; %bb.0: ; %entry ; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7 ; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7
; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX900-NEXT: s_add_u32 s0, s0, s7 ; GFX900-NEXT: s_add_u32 s0, s0, s7
; GFX900-NEXT: s_mov_b32 s33, 0 ; GFX900-NEXT: s_mov_b32 s33, 0
; GFX900-NEXT: s_addc_u32 s1, s1, 0 ; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX1010-LABEL: test_force_fp_kern_stack: ; GFX1010-LABEL: test_force_fp_kern_stack:
; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_mov_b32 s33, 0 ; GFX1010-NEXT: s_mov_b32 s33, 0
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: s_endpgm
entry: entry:
%x = alloca i32, align 4, addrspace(5) %x = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %x, align 4 store volatile i32 0, i32 addrspace(5)* %x, align 4
ret void ret void
} }
define amdgpu_kernel void @test_force_fp_kern_call() local_unnamed_addr #2 { define amdgpu_kernel void @test_force_fp_kern_call() local_unnamed_addr #2 {
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; GFX803-NEXT: s_addc_u32 s1, s1, 0 ; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: v_mov_b32_e32 v0, 0 ; GFX803-NEXT: v_mov_b32_e32 v0, 0
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5 ; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5
; GFX803-NEXT: s_getpc_b64 s[4:5] ; GFX803-NEXT: s_getpc_b64 s[4:5]
; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX803-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12 ; GFX803-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX803-NEXT: s_movk_i32 s32, 0x400 ; GFX803-NEXT: s_movk_i32 s32, 0x400
; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX803-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX803-NEXT: s_endpgm ; GFX803-NEXT: s_endpgm
; ;
; GFX900-LABEL: test_force_fp_kern_stack_and_call: ; GFX900-LABEL: test_force_fp_kern_stack_and_call:
; GFX900: ; %bb.0: ; %entry ; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7 ; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7
; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX900-NEXT: s_add_u32 s0, s0, s7 ; GFX900-NEXT: s_add_u32 s0, s0, s7
; GFX900-NEXT: s_addc_u32 s1, s1, 0 ; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: s_mov_b32 s33, 0 ; GFX900-NEXT: s_mov_b32 s33, 0
; GFX900-NEXT: v_mov_b32_e32 v0, 0 ; GFX900-NEXT: v_mov_b32_e32 v0, 0
; GFX900-NEXT: s_getpc_b64 s[4:5] ; GFX900-NEXT: s_getpc_b64 s[4:5]
; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX900-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12 ; GFX900-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX900-NEXT: s_movk_i32 s32, 0x400 ; GFX900-NEXT: s_movk_i32 s32, 0x400
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX900-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX1010-LABEL: test_force_fp_kern_stack_and_call: ; GFX1010-LABEL: test_force_fp_kern_stack_and_call:
; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_movk_i32 s32, 0x200 ; GFX1010-NEXT: s_movk_i32 s32, 0x200
; GFX1010-NEXT: s_mov_b32 s33, 0 ; GFX1010-NEXT: s_mov_b32 s33, 0
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: v_mov_b32_e32 v0, 0 ; GFX1010-NEXT: v_mov_b32_e32 v0, 0
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: s_getpc_b64 s[4:5] ; GFX1010-NEXT: s_getpc_b64 s[4:5]
; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4 ; GFX1010-NEXT: s_add_u32 s4, s4, ex@rel32@lo+4
; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12 ; GFX1010-NEXT: s_addc_u32 s5, s5, ex@rel32@hi+12
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4 ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s33 offset:4
; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX1010-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: s_endpgm
entry: entry:
%x = alloca i32, align 4, addrspace(5) %x = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %x, align 4 store volatile i32 0, i32 addrspace(5)* %x, align 4
tail call void @ex() #2 tail call void @ex() #2
ret void ret void
} }
define amdgpu_kernel void @test_sgpr_offset_kernel() #1 { define amdgpu_kernel void @test_sgpr_offset_kernel() #1 {
; GFX803-LABEL: test_sgpr_offset_kernel: ; GFX803-LABEL: test_sgpr_offset_kernel:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_add_u32 s4, s4, s7 ; GFX803-NEXT: s_add_u32 s4, s4, s7
; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8 ; GFX803-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; GFX803-NEXT: s_add_u32 s0, s0, s7 ; GFX803-NEXT: s_add_u32 s0, s0, s7
; GFX803-NEXT: s_addc_u32 s1, s1, 0 ; GFX803-NEXT: s_addc_u32 s1, s1, 0
; GFX803-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 ; GFX803-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_mov_b32 s4, 0x40000 ; GFX803-NEXT: s_mov_b32 s4, 0x40000
; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5 ; GFX803-NEXT: s_mov_b32 flat_scratch_lo, s5
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill ; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], s4 ; 4-byte Folded Spill
; GFX803-NEXT: ;;#ASMSTART ; GFX803-NEXT: ;;#ASMSTART
; GFX803-NEXT: ;;#ASMEND ; GFX803-NEXT: ;;#ASMEND
; GFX803-NEXT: s_mov_b32 s4, 0x40000 ; GFX803-NEXT: s_mov_b32 s4, 0x40000
; GFX803-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload ; GFX803-NEXT: buffer_load_dword v0, off, s[0:3], s4 ; 4-byte Folded Reload
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8 ; GFX803-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_endpgm ; GFX803-NEXT: s_endpgm
; ;
; GFX900-LABEL: test_sgpr_offset_kernel: ; GFX900-LABEL: test_sgpr_offset_kernel:
; GFX900: ; %bb.0: ; %entry ; GFX900: ; %bb.0: ; %entry
; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7 ; GFX900-NEXT: s_add_u32 flat_scratch_lo, s4, s7
; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX900-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX900-NEXT: s_add_u32 s0, s0, s7 ; GFX900-NEXT: s_add_u32 s0, s0, s7
; GFX900-NEXT: s_addc_u32 s1, s1, 0 ; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc
; GFX900-NEXT: s_mov_b32 s6, 0x40000
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_mov_b32 s6, 0x40000
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX900-NEXT: ;;#ASMSTART ; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ;;#ASMEND ; GFX900-NEXT: ;;#ASMEND
; GFX900-NEXT: s_mov_b32 s6, 0x40000 ; GFX900-NEXT: s_mov_b32 s6, 0x40000
; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s6 ; 4-byte Folded Reload ; GFX900-NEXT: buffer_load_dword v0, off, s[0:3], s6 ; 4-byte Folded Reload
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8 ; GFX900-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; GFX1010-LABEL: test_sgpr_offset_kernel: ; GFX1010-LABEL: test_sgpr_offset_kernel:
; GFX1010: ; %bb.0: ; %entry ; GFX1010: ; %bb.0: ; %entry
; GFX1010-NEXT: s_add_u32 s4, s4, s7 ; GFX1010-NEXT: s_add_u32 s4, s4, s7
; GFX1010-NEXT: s_addc_u32 s5, s5, 0 ; GFX1010-NEXT: s_addc_u32 s5, s5, 0
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX1010-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX1010-NEXT: s_add_u32 s0, s0, s7 ; GFX1010-NEXT: s_add_u32 s0, s0, s7
; GFX1010-NEXT: s_addc_u32 s1, s1, 0 ; GFX1010-NEXT: s_addc_u32 s1, s1, 0
; GFX1010-NEXT: s_mov_b32 s6, 0x20000 ; GFX1010-NEXT: s_mov_b32 s6, 0x20000
; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 ; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:8 glc dlc
; GFX1010-NEXT: s_waitcnt vmcnt(0) ; GFX1010-NEXT: s_waitcnt vmcnt(0)
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], s6 ; 4-byte Folded Spill
; GFX1010-NEXT: s_waitcnt_depctr 0xffe3 ; GFX1010-NEXT: s_waitcnt_depctr 0xffe3
; GFX1010-NEXT: s_mov_b32 s6, 0x20000 ; GFX1010-NEXT: s_mov_b32 s6, 0x20000
; GFX1010-NEXT: ;;#ASMSTART ; GFX1010-NEXT: ;;#ASMSTART
; GFX1010-NEXT: ;;#ASMEND ; GFX1010-NEXT: ;;#ASMEND
; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], s6 ; 4-byte Folded Reload ; GFX1010-NEXT: buffer_load_dword v0, off, s[0:3], s6 ; 4-byte Folded Reload
; GFX1010-NEXT: s_waitcnt vmcnt(0) ; GFX1010-NEXT: s_waitcnt vmcnt(0)
; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8 ; GFX1010-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
; GFX1010-NEXT: s_waitcnt_vscnt null, 0x0
; GFX1010-NEXT: s_endpgm ; GFX1010-NEXT: s_endpgm
entry: entry:
; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not ; Occupy 4096 bytes of scratch, so the offset of the spill of %a does not
; fit in the instruction, and has to live in the SGPR offset. ; fit in the instruction, and has to live in the SGPR offset.
%alloca = alloca i8, i32 4092, align 4, addrspace(5) %alloca = alloca i8, i32 4092, align 4, addrspace(5)
%buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)* %buf = bitcast i8 addrspace(5)* %alloca to i32 addrspace(5)*
%aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1 %aptr = getelementptr i32, i32 addrspace(5)* %buf, i32 1
Show All 19 Lines

llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-gfx908.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S -codegenprepare -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=OPT %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx908 < %s | FileCheck -check-prefix=GCN %s
; Make sure we match the addressing mode offset of globla.atomic.fadd intrinsics across blocks. ; Make sure we match the addressing mode offset of globla.atomic.fadd intrinsics across blocks.
define amdgpu_kernel void @test_sink_small_offset_global_atomic_fadd_f32(float addrspace(1)* %out, float addrspace(1)* %in) { define amdgpu_kernel void @test_sink_small_offset_global_atomic_fadd_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
; OPT-LABEL: @test_sink_small_offset_global_atomic_fadd_f32( ; OPT-LABEL: @test_sink_small_offset_global_atomic_fadd_f32(
Show All 22 Lines
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc ; GCN-NEXT: s_and_saveexec_b64 s[4:5], vcc
; GCN-NEXT: s_cbranch_execz BB0_2 ; GCN-NEXT: s_cbranch_execz BB0_2
; GCN-NEXT: ; %bb.1: ; %if ; GCN-NEXT: ; %bb.1: ; %if
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: v_mov_b32_e32 v1, 2.0 ; GCN-NEXT: v_mov_b32_e32 v1, 2.0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: global_atomic_add_f32 v0, v1, s[2:3] offset:28 ; GCN-NEXT: global_atomic_add_f32 v0, v1, s[2:3] offset:28
; GCN-NEXT: global_load_dword v0, v[0:1], off ; GCN-NEXT: global_load_dword v0, v[0:1], off glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: BB0_2: ; %endif ; GCN-NEXT: BB0_2: ; %endif
; GCN-NEXT: s_or_b64 exec, exec, s[4:5] ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
; GCN-NEXT: v_mov_b32_e32 v1, 0x3d0000 ; GCN-NEXT: v_mov_b32_e32 v1, 0x3d0000
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: global_store_dword v1, v0, s[0:1] offset:2300 ; GCN-NEXT: global_store_dword v1, v0, s[0:1] offset:2300
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%out.gep = getelementptr float, float addrspace(1)* %out, i32 999999 %out.gep = getelementptr float, float addrspace(1)* %out, i32 999999
Show All 25 Lines

llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll

Show First 20 Lines • Show All 131 Lines • ▼ Show 20 Lines
; OPT-LABEL: @test_sink_scratch_small_offset_i32( ; OPT-LABEL: @test_sink_scratch_small_offset_i32(
; OPT-NOT: getelementptr [512 x i32] ; OPT-NOT: getelementptr [512 x i32]
; OPT: br i1 ; OPT: br i1
; OPT: getelementptr i8, ; OPT: getelementptr i8,
; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32: ; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4092{{$}} ; GCN: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4092{{$}}
; GCN: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4092{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 offset:4092 glc{{$}}
; GCN: {{^}}BB4_2: ; GCN: {{^}}BB4_2:
define amdgpu_kernel void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { define amdgpu_kernel void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) {
entry: entry:
%alloca = alloca [512 x i32], align 4, addrspace(5) %alloca = alloca [512 x i32], align 4, addrspace(5)
%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%add.arg = add i32 %arg, 8 %add.arg = add i32 %arg, 8
%alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1022 %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1022
Show All 23 Lines
; OPT: br i1 ; OPT: br i1
; OPT: getelementptr i8, ; OPT: getelementptr i8,
; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32_reserved: ; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32_reserved:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: v_mov_b32_e32 [[BASE_FI0:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[BASE_FI0:v[0-9]+]], 4
; GCN: buffer_store_dword {{v[0-9]+}}, [[BASE_FI0]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen offset:4092{{$}} ; GCN: buffer_store_dword {{v[0-9]+}}, [[BASE_FI0]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen offset:4092{{$}}
; GCN: v_mov_b32_e32 [[BASE_FI1:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[BASE_FI1:v[0-9]+]], 4
; GCN: buffer_load_dword {{v[0-9]+}}, [[BASE_FI1]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen offset:4092{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, [[BASE_FI1]], {{s\[[0-9]+:[0-9]+\]}}, 0 offen offset:4092 glc{{$}}
; GCN: {{^BB[0-9]+}}_2: ; GCN: {{^BB[0-9]+}}_2:
define amdgpu_kernel void @test_sink_scratch_small_offset_i32_reserved(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { define amdgpu_kernel void @test_sink_scratch_small_offset_i32_reserved(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) {
entry: entry:
%alloca = alloca [512 x i32], align 4, addrspace(5) %alloca = alloca [512 x i32], align 4, addrspace(5)
%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%add.arg = add i32 %arg, 8 %add.arg = add i32 %arg, 8
Show All 21 Lines
; OPT-LABEL: @test_no_sink_scratch_large_offset_i32( ; OPT-LABEL: @test_no_sink_scratch_large_offset_i32(
; OPT: %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024 ; OPT: %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024
; OPT: br i1 ; OPT: br i1
; OPT-NOT: ptrtoint ; OPT-NOT: ptrtoint
; GCN-LABEL: {{^}}test_no_sink_scratch_large_offset_i32: ; GCN-LABEL: {{^}}test_no_sink_scratch_large_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}} ; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc{{$}}
; GCN: {{^BB[0-9]+}}_2: ; GCN: {{^BB[0-9]+}}_2:
define amdgpu_kernel void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { define amdgpu_kernel void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) {
entry: entry:
%alloca = alloca [512 x i32], align 4, addrspace(5) %alloca = alloca [512 x i32], align 4, addrspace(5)
%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%add.arg = add i32 %arg, 8 %add.arg = add i32 %arg, 8
%alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024 %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024
▲ Show 20 Lines • Show All 588 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll

Show First 20 Lines • Show All 227 Lines • ▼ Show 20 Lines
; GFX900-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0 ; GFX900-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; GFX900-NEXT: v_mov_b32_e32 v2, 0 ; GFX900-NEXT: v_mov_b32_e32 v2, 0
; GFX900-NEXT: s_add_u32 s0, s0, s9 ; GFX900-NEXT: s_add_u32 s0, s0, s9
; GFX900-NEXT: s_addc_u32 s1, s1, 0 ; GFX900-NEXT: s_addc_u32 s1, s1, 0
; GFX900-NEXT: s_waitcnt lgkmcnt(0) ; GFX900-NEXT: s_waitcnt lgkmcnt(0)
; GFX900-NEXT: global_load_ushort v0, v2, s[4:5] ; GFX900-NEXT: global_load_ushort v0, v2, s[4:5]
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4 ; GFX900-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: global_load_ushort v0, v2, s[4:5] offset:2 ; GFX900-NEXT: global_load_ushort v0, v2, s[4:5] offset:2
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:6 ; GFX900-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:6
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: global_load_ushort v0, v2, s[4:5] offset:4 ; GFX900-NEXT: global_load_ushort v0, v2, s[4:5] offset:4
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:8 ; GFX900-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:8
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4 ; GFX900-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4
; GFX900-NEXT: buffer_load_ushort v3, off, s[0:3], 0 offset:6 ; GFX900-NEXT: buffer_load_ushort v3, off, s[0:3], 0 offset:6
; GFX900-NEXT: s_waitcnt vmcnt(1) ; GFX900-NEXT: s_waitcnt vmcnt(1)
; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX900-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: v_mov_b32_e32 v1, v3 ; GFX900-NEXT: v_mov_b32_e32 v1, v3
; GFX900-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], 0 offset:8 ; GFX900-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], 0 offset:8
; GFX900-NEXT: v_lshl_or_b32 v0, v3, 16, v0 ; GFX900-NEXT: v_lshl_or_b32 v0, v3, 16, v0
; GFX900-NEXT: s_waitcnt vmcnt(0) ; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7] ; GFX900-NEXT: global_store_dwordx2 v2, v[0:1], s[6:7]
; GFX900-NEXT: s_endpgm ; GFX900-NEXT: s_endpgm
; ;
; FLATSCR-LABEL: vload2_private: ; FLATSCR-LABEL: vload2_private:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; FLATSCR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0 ; FLATSCR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x0
; FLATSCR-NEXT: v_mov_b32_e32 v2, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1] ; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1]
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:4 ; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:4
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1] offset:2 ; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1] offset:2
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:6 ; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:6
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1] offset:4 ; FLATSCR-NEXT: global_load_ushort v0, v2, s[0:1] offset:4
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:8 ; FLATSCR-NEXT: scratch_store_short off, v0, vcc_hi offset:8
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; FLATSCR-NEXT: scratch_load_dword v0, off, vcc_hi offset:4
; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0 ; FLATSCR-NEXT: s_mov_b32 vcc_hi, 0
; FLATSCR-NEXT: scratch_load_dword v1, off, vcc_hi offset:6 ; FLATSCR-NEXT: scratch_load_dword v1, off, vcc_hi offset:6
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3] ; FLATSCR-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
; FLATSCR-NEXT: s_endpgm ; FLATSCR-NEXT: s_endpgm
entry: entry:
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Linesbb:
%result = insertelement <2 x i16> %op.hi, i16 %load_lo, i32 0 %result = insertelement <2 x i16> %op.hi, i16 %load_lo, i32 0
ret <2 x i16> %result ret <2 x i16> %result
} }
define <2 x i16> @chain_hi_to_lo_global_other_dep(i16 addrspace(1)* %ptr) { define <2 x i16> @chain_hi_to_lo_global_other_dep(i16 addrspace(1)* %ptr) {
; GCN-LABEL: chain_hi_to_lo_global_other_dep: ; GCN-LABEL: chain_hi_to_lo_global_other_dep:
; GCN: ; %bb.0: ; %bb ; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: global_load_ushort v2, v[0:1], off offset:2 ; GCN-NEXT: global_load_ushort v2, v[0:1], off offset:2 glc
; GCN-NEXT: global_load_short_d16_hi v0, v[0:1], off
; GCN-NEXT: v_mov_b32_e32 v1, 0xffff
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: global_load_short_d16_hi v0, v[0:1], off glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, 0xffff
; GCN-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0] ; GCN-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
; GCN-NEXT: v_bfi_b32 v0, v1, v2, v0 ; GCN-NEXT: v_bfi_b32 v0, v1, v2, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%gep_lo = getelementptr inbounds i16, i16 addrspace(1)* %ptr, i64 1 %gep_lo = getelementptr inbounds i16, i16 addrspace(1)* %ptr, i64 1
%load_lo = load volatile i16, i16 addrspace(1)* %gep_lo %load_lo = load volatile i16, i16 addrspace(1)* %gep_lo
%gep_hi = getelementptr inbounds i16, i16 addrspace(1)* %ptr, i64 0 %gep_hi = getelementptr inbounds i16, i16 addrspace(1)* %ptr, i64 0
%load_hi = load volatile i16, i16 addrspace(1)* %gep_hi %load_hi = load volatile i16, i16 addrspace(1)* %gep_hi
%to.hi = insertelement <2 x i16> undef, i16 %load_hi, i32 1 %to.hi = insertelement <2 x i16> undef, i16 %load_hi, i32 1
%op.hi = add <2 x i16> %to.hi, <i16 12, i16 12> %op.hi = add <2 x i16> %to.hi, <i16 12, i16 12>
%result = insertelement <2 x i16> %op.hi, i16 %load_lo, i32 0 %result = insertelement <2 x i16> %op.hi, i16 %load_lo, i32 0
ret <2 x i16> %result ret <2 x i16> %result
} }
define <2 x i16> @chain_hi_to_lo_flat_other_dep(i16 addrspace(0)* %ptr) { define <2 x i16> @chain_hi_to_lo_flat_other_dep(i16 addrspace(0)* %ptr) {
; GCN-LABEL: chain_hi_to_lo_flat_other_dep: ; GCN-LABEL: chain_hi_to_lo_flat_other_dep:
; GCN: ; %bb.0: ; %bb ; GCN: ; %bb.0: ; %bb
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: flat_load_ushort v2, v[0:1] offset:2 ; GCN-NEXT: flat_load_ushort v2, v[0:1] offset:2 glc
; GCN-NEXT: flat_load_short_d16_hi v0, v[0:1] ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_load_short_d16_hi v0, v[0:1] glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v1, 0xffff ; GCN-NEXT: v_mov_b32_e32 v1, 0xffff
; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0] ; GCN-NEXT: v_pk_sub_u16 v0, v0, -12 op_sel_hi:[1,0]
; GCN-NEXT: v_bfi_b32 v0, v1, v2, v0 ; GCN-NEXT: v_bfi_b32 v0, v1, v2, v0
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%gep_lo = getelementptr inbounds i16, i16 addrspace(0)* %ptr, i64 1 %gep_lo = getelementptr inbounds i16, i16 addrspace(0)* %ptr, i64 1
%load_lo = load volatile i16, i16 addrspace(0)* %gep_lo %load_lo = load volatile i16, i16 addrspace(0)* %gep_lo
%gep_hi = getelementptr inbounds i16, i16 addrspace(0)* %ptr, i64 0 %gep_hi = getelementptr inbounds i16, i16 addrspace(0)* %ptr, i64 0
%load_hi = load volatile i16, i16 addrspace(0)* %gep_hi %load_hi = load volatile i16, i16 addrspace(0)* %gep_hi
Show All 29 Lines

llvm/test/CodeGen/AMDGPU/commute_modifiers.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @commute_add_lit_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
%x = load float, float addrspace(1)* %gep.0 %x = load float, float addrspace(1)* %gep.0
%x.fabs = call float @llvm.fabs.f32(float %x) #1 %x.fabs = call float @llvm.fabs.f32(float %x) #1
%z = fadd float 1024.0, %x.fabs %z = fadd float 1024.0, %x.fabs
store float %z, float addrspace(1)* %out store float %z, float addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: @commute_add_fabs_f32 ; FUNC-LABEL: @commute_add_fabs_f32
; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; SI: v_add_f32_e64 [[REG:v[0-9]+]], [[X]], |[[Y]]| ; SI: v_add_f32_e64 [[REG:v[0-9]+]], [[X]], |[[Y]]|
; SI: buffer_store_dword [[REG]] ; SI: buffer_store_dword [[REG]]
define amdgpu_kernel void @commute_add_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { define amdgpu_kernel void @commute_add_fabs_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%x = load volatile float, float addrspace(1)* %gep.0 %x = load volatile float, float addrspace(1)* %gep.0
%y = load volatile float, float addrspace(1)* %gep.1 %y = load volatile float, float addrspace(1)* %gep.1
%y.fabs = call float @llvm.fabs.f32(float %y) #1 %y.fabs = call float @llvm.fabs.f32(float %y) #1
%z = fadd float %x, %y.fabs %z = fadd float %x, %y.fabs
store float %z, float addrspace(1)* %out store float %z, float addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: @commute_mul_fneg_f32 ; FUNC-LABEL: @commute_mul_fneg_f32
; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; SI: v_mul_f32_e64 [[REG:v[0-9]+]], [[X]], -[[Y]] ; SI: v_mul_f32_e64 [[REG:v[0-9]+]], [[X]], -[[Y]]
; SI: buffer_store_dword [[REG]] ; SI: buffer_store_dword [[REG]]
define amdgpu_kernel void @commute_mul_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { define amdgpu_kernel void @commute_mul_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%x = load volatile float, float addrspace(1)* %gep.0 %x = load volatile float, float addrspace(1)* %gep.0
%y = load volatile float, float addrspace(1)* %gep.1 %y = load volatile float, float addrspace(1)* %gep.1
%y.fneg = fsub float -0.000000e+00, %y %y.fneg = fsub float -0.000000e+00, %y
%z = fmul float %x, %y.fneg %z = fmul float %x, %y.fneg
store float %z, float addrspace(1)* %out store float %z, float addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: @commute_mul_fabs_fneg_f32 ; FUNC-LABEL: @commute_mul_fabs_fneg_f32
; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; SI: v_mul_f32_e64 [[REG:v[0-9]+]], [[X]], -|[[Y]]| ; SI: v_mul_f32_e64 [[REG:v[0-9]+]], [[X]], -|[[Y]]|
; SI: buffer_store_dword [[REG]] ; SI: buffer_store_dword [[REG]]
define amdgpu_kernel void @commute_mul_fabs_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { define amdgpu_kernel void @commute_mul_fabs_fneg_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%x = load volatile float, float addrspace(1)* %gep.0 %x = load volatile float, float addrspace(1)* %gep.0
%y = load volatile float, float addrspace(1)* %gep.1 %y = load volatile float, float addrspace(1)* %gep.1
%y.fabs = call float @llvm.fabs.f32(float %y) #1 %y.fabs = call float @llvm.fabs.f32(float %y) #1
%y.fabs.fneg = fsub float -0.000000e+00, %y.fabs %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
%z = fmul float %x, %y.fabs.fneg %z = fmul float %x, %y.fabs.fneg
store float %z, float addrspace(1)* %out store float %z, float addrspace(1)* %out
ret void ret void
} }
; There's no reason to commute this. ; There's no reason to commute this.
; FUNC-LABEL: @commute_mul_fabs_x_fabs_y_f32 ; FUNC-LABEL: @commute_mul_fabs_x_fabs_y_f32
; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; SI: v_mul_f32_e64 [[REG:v[0-9]+]], |[[X]]|, |[[Y]]| ; SI: v_mul_f32_e64 [[REG:v[0-9]+]], |[[X]]|, |[[Y]]|
; SI: buffer_store_dword [[REG]] ; SI: buffer_store_dword [[REG]]
define amdgpu_kernel void @commute_mul_fabs_x_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { define amdgpu_kernel void @commute_mul_fabs_x_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%x = load volatile float, float addrspace(1)* %gep.0 %x = load volatile float, float addrspace(1)* %gep.0
%y = load volatile float, float addrspace(1)* %gep.1 %y = load volatile float, float addrspace(1)* %gep.1
%x.fabs = call float @llvm.fabs.f32(float %x) #1 %x.fabs = call float @llvm.fabs.f32(float %x) #1
%y.fabs = call float @llvm.fabs.f32(float %y) #1 %y.fabs = call float @llvm.fabs.f32(float %y) #1
%z = fmul float %x.fabs, %y.fabs %z = fmul float %x.fabs, %y.fabs
store float %z, float addrspace(1)* %out store float %z, float addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: @commute_mul_fabs_x_fneg_fabs_y_f32 ; FUNC-LABEL: @commute_mul_fabs_x_fneg_fabs_y_f32
; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[X:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI-DAG: buffer_load_dword [[Y:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; SI: v_mul_f32_e64 [[REG:v[0-9]+]], |[[X]]|, -|[[Y]]| ; SI: v_mul_f32_e64 [[REG:v[0-9]+]], |[[X]]|, -|[[Y]]|
; SI: buffer_store_dword [[REG]] ; SI: buffer_store_dword [[REG]]
define amdgpu_kernel void @commute_mul_fabs_x_fneg_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 { define amdgpu_kernel void @commute_mul_fabs_x_fneg_fabs_y_f32(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%x = load volatile float, float addrspace(1)* %gep.0 %x = load volatile float, float addrspace(1)* %gep.0
%y = load volatile float, float addrspace(1)* %gep.1 %y = load volatile float, float addrspace(1)* %gep.1
%x.fabs = call float @llvm.fabs.f32(float %x) #1 %x.fabs = call float @llvm.fabs.f32(float %x) #1
%y.fabs = call float @llvm.fabs.f32(float %y) #1 %y.fabs = call float @llvm.fabs.f32(float %y) #1
%y.fabs.fneg = fsub float -0.000000e+00, %y.fabs %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
%z = fmul float %x.fabs, %y.fabs.fneg %z = fmul float %x.fabs, %y.fabs.fneg
store float %z, float addrspace(1)* %out store float %z, float addrspace(1)* %out
ret void ret void
} }
; Make sure we commute the multiply part for the constant in src0 even ; Make sure we commute the multiply part for the constant in src0 even
; though we have negate modifier on src2. ; though we have negate modifier on src2.
; SI-LABEL: {{^}}fma_a_2.0_neg_b_f32 ; SI-LABEL: {{^}}fma_a_2.0_neg_b_f32
; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[R1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI-DAG: buffer_load_dword [[R2:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, |[[R2]]| ; SI: v_fma_f32 [[RESULT:v[0-9]+]], [[R1]], 2.0, |[[R2]]|
; SI: buffer_store_dword [[RESULT]] ; SI: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @fma_a_2.0_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) { define amdgpu_kernel void @fma_a_2.0_neg_b_f32(float addrspace(1)* %out, float addrspace(1)* %in) {
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %out, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid %gep.out = getelementptr float, float addrspace(1)* %out, i32 %tid
Show All 13 Lines

llvm/test/CodeGen/AMDGPU/copy-illegal-type.ll

Show First 20 Lines • Show All 561 Lines • ▼ Show 20 Lines
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s6, s2 ; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_mov_b32 s7, s3 ; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_load_dword v0, off, s[4:7], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_copy_v4i8_volatile_load: ; VI-LABEL: test_copy_v4i8_volatile_load:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s6, s2 ; VI-NEXT: s_mov_b32 s6, s2
; VI-NEXT: s_mov_b32 s7, s3 ; VI-NEXT: s_mov_b32 s7, s3
; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_load_dword v0, off, s[4:7], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%val = load volatile <4 x i8>, <4 x i8> addrspace(1)* %in, align 4 %val = load volatile <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4 store <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
ret void ret void
} }
Show All 11 Lines
; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 ; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1 ; SI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1
; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2 ; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:3 ; SI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:3
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_byte v3, off, s[0:3], 0 offset:3 ; SI-NEXT: buffer_store_byte v3, off, s[0:3], 0 offset:3
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_byte v2, off, s[0:3], 0 offset:2 ; SI-NEXT: buffer_store_byte v2, off, s[0:3], 0 offset:2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:1 ; SI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: test_copy_v4i8_volatile_store: ; VI-LABEL: test_copy_v4i8_volatile_store:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s6 ; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7 ; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 ; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1 ; VI-NEXT: buffer_load_ubyte v1, off, s[8:11], 0 offset:1
; VI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2 ; VI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2
; VI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:3 ; VI-NEXT: buffer_load_ubyte v3, off, s[8:11], 0 offset:3
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_byte v3, off, s[0:3], 0 offset:3 ; VI-NEXT: buffer_store_byte v3, off, s[0:3], 0 offset:3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_byte v2, off, s[0:3], 0 offset:2 ; VI-NEXT: buffer_store_byte v2, off, s[0:3], 0 offset:2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:1 ; VI-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_byte v0, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4 %val = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4
store volatile <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4 store volatile <4 x i8> %val, <4 x i8> addrspace(1)* %out, align 4
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/ds-sub-offset.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CI-NEXT: s_mov_b32 s0, 0 ; CI-NEXT: s_mov_b32 s0, 0
; CI-NEXT: v_div_fmas_f32 v1, v1, v1, v1 ; CI-NEXT: v_div_fmas_f32 v1, v1, v1, v1
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s1, s0 ; CI-NEXT: s_mov_b32 s1, s0
; CI-NEXT: ds_write_b32 v0, v2 offset:12 ; CI-NEXT: ds_write_b32 v0, v2 offset:12
; CI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; CI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: write_ds_sub0_offset0_global_clamp_bit: ; GFX9-LABEL: write_ds_sub0_offset0_global_clamp_bit:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 vcc, 0 ; GFX9-NEXT: s_mov_b64 vcc, 0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, 0, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_div_fmas_f32 v2, v1, v1, v1 ; GFX9-NEXT: v_div_fmas_f32 v2, v1, v1, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX9-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX9-NEXT: ds_write_b32 v0, v1 offset:12 ; GFX9-NEXT: ds_write_b32 v0, v1 offset:12
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
entry: entry:
%x.i = call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #1
%sub1 = sub i32 0, %x.i %sub1 = sub i32 0, %x.i
%tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1 %tmp0 = getelementptr [256 x i32], [256 x i32] addrspace(3)* @lds.obj, i32 0, i32 %sub1
%arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3 %arrayidx = getelementptr inbounds i32, i32 addrspace(3)* %tmp0, i32 3
store i32 123, i32 addrspace(3)* %arrayidx store i32 123, i32 addrspace(3)* %arrayidx
%fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false) %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
▲ Show 20 Lines • Show All 155 Lines • ▼ Show 20 Lines
; CI-NEXT: v_div_fmas_f32 v1, v1, v1, v1 ; CI-NEXT: v_div_fmas_f32 v1, v1, v1, v1
; CI-NEXT: v_mov_b32_e32 v3, 0 ; CI-NEXT: v_mov_b32_e32 v3, 0
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, -1 ; CI-NEXT: s_mov_b32 s2, -1
; CI-NEXT: s_mov_b32 s1, s0 ; CI-NEXT: s_mov_b32 s1, s0
; CI-NEXT: ds_write2_b32 v0, v2, v3 offset1:1 ; CI-NEXT: ds_write2_b32 v0, v2, v3 offset1:1
; CI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; CI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit: ; GFX9-LABEL: add_x_shl_neg_to_sub_misaligned_i64_max_offset_clamp_bit:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-NEXT: s_mov_b64 vcc, 0 ; GFX9-NEXT: s_mov_b64 vcc, 0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_sub_u32_e32 v0, 0x3fb, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, 0x3fb, v0
; GFX9-NEXT: v_mov_b32_e32 v3, 0 ; GFX9-NEXT: v_mov_b32_e32 v3, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s0 ; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_div_fmas_f32 v2, v1, v1, v1 ; GFX9-NEXT: v_div_fmas_f32 v2, v1, v1, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX9-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX9-NEXT: ds_write2_b32 v0, v1, v3 offset1:1 ; GFX9-NEXT: ds_write2_b32 v0, v1, v3 offset1:1
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%x.i = call i32 @llvm.amdgcn.workitem.id.x() #0 %x.i = call i32 @llvm.amdgcn.workitem.id.x() #0
%neg = sub i32 0, %x.i %neg = sub i32 0, %x.i
%shl = shl i32 %neg, 2 %shl = shl i32 %neg, 2
%add = add i32 1019, %shl %add = add i32 1019, %shl
%ptr = inttoptr i32 %add to i64 addrspace(3)* %ptr = inttoptr i32 %add to i64 addrspace(3)*
store i64 123, i64 addrspace(3)* %ptr, align 4 store i64 123, i64 addrspace(3)* %ptr, align 4
%fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false) %fmas = call float @llvm.amdgcn.div.fmas.f32(float %dummy.val, float %dummy.val, float %dummy.val, i1 false)
Show All 37 Lines

llvm/test/CodeGen/AMDGPU/ds_write2.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CI-LABEL: simple_write2_two_val_f32: ; CI-LABEL: simple_write2_two_val_f32:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc
; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64 offset:4 ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64 offset:4 glc
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: ds_write2_b32 v0, v2, v1 offset1:8 ; CI-NEXT: ds_write2_b32 v0, v2, v1 offset1:8
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: simple_write2_two_val_f32: ; GFX9-LABEL: simple_write2_two_val_f32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[0:1] ; GFX9-NEXT: global_load_dword v1, v0, s[0:1] glc
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] offset:4 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:8 ; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:8
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
%in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
%val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4
%val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4
Show All 12 Lines
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[4:5] ; CI-NEXT: s_mov_b64 s[0:1], s[4:5]
; CI-NEXT: s_mov_b64 s[4:5], s[6:7] ; CI-NEXT: s_mov_b64 s[4:5], s[6:7]
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc
; CI-NEXT: buffer_load_dword v1, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: buffer_load_dword v1, v[0:1], s[4:7], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: ds_write_b32 v0, v2 ; CI-NEXT: ds_write_b32 v0, v2
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: ds_write_b32 v0, v1 offset:32 ; CI-NEXT: ds_write_b32 v0, v1 offset:32
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: simple_write2_two_val_f32_volatile_0: ; GFX9-LABEL: simple_write2_two_val_f32_volatile_0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[0:1] ; GFX9-NEXT: global_load_dword v1, v0, s[0:1] glc
; GFX9-NEXT: global_load_dword v2, v0, s[2:3] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: global_load_dword v2, v0, s[2:3] glc
; GFX9-NEXT: ds_write_b32 v0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ds_write_b32 v0, v1
; GFX9-NEXT: ds_write_b32 v0, v2 offset:32 ; GFX9-NEXT: ds_write_b32 v0, v2 offset:32
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
%in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
%val0 = load volatile float, float addrspace(1)* %in0.gep, align 4 %val0 = load volatile float, float addrspace(1)* %in0.gep, align 4
%val1 = load volatile float, float addrspace(1)* %in1.gep, align 4 %val1 = load volatile float, float addrspace(1)* %in1.gep, align 4
%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
Show All 11 Lines
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: s_mov_b64 s[0:1], s[4:5] ; CI-NEXT: s_mov_b64 s[0:1], s[4:5]
; CI-NEXT: s_mov_b64 s[4:5], s[6:7] ; CI-NEXT: s_mov_b64 s[4:5], s[6:7]
; CI-NEXT: s_mov_b64 s[6:7], s[2:3] ; CI-NEXT: s_mov_b64 s[6:7], s[2:3]
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc
; CI-NEXT: buffer_load_dword v1, v[0:1], s[4:7], 0 addr64 ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: buffer_load_dword v1, v[0:1], s[4:7], 0 addr64 glc
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: ds_write_b32 v0, v2 ; CI-NEXT: ds_write_b32 v0, v2
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: ds_write_b32 v0, v1 offset:32 ; CI-NEXT: ds_write_b32 v0, v1 offset:32
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: simple_write2_two_val_f32_volatile_1: ; GFX9-LABEL: simple_write2_two_val_f32_volatile_1:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x2c
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[0:1] ; GFX9-NEXT: global_load_dword v1, v0, s[0:1] glc
; GFX9-NEXT: global_load_dword v2, v0, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: ds_write_b32 v0, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ds_write_b32 v0, v1
; GFX9-NEXT: ds_write_b32 v0, v2 offset:32 ; GFX9-NEXT: ds_write_b32 v0, v2 offset:32
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i %in0.gep = getelementptr float, float addrspace(1)* %in0, i32 %x.i
%in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i %in1.gep = getelementptr float, float addrspace(1)* %in1, i32 %x.i
%val0 = load volatile float, float addrspace(1)* %in0.gep, align 4 %val0 = load volatile float, float addrspace(1)* %in0.gep, align 4
%val1 = load volatile float, float addrspace(1)* %in1.gep, align 4 %val1 = load volatile float, float addrspace(1)* %in1.gep, align 4
%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
Show All 13 Lines
; CI-LABEL: simple_write2_two_val_subreg2_mixed_f32: ; CI-LABEL: simple_write2_two_val_subreg2_mixed_f32:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; CI-NEXT: v_lshlrev_b32_e32 v1, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v1, 3, v0
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_mov_b32_e32 v2, 0 ; CI-NEXT: v_mov_b32_e32 v2, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[0:3], 0 addr64 glc
; CI-NEXT: buffer_load_dwordx2 v[1:2], v[1:2], s[0:3], 0 addr64 offset:8 ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: buffer_load_dwordx2 v[1:2], v[1:2], s[0:3], 0 addr64 offset:8 glc
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: ds_write2_b32 v0, v3, v2 offset1:8 ; CI-NEXT: ds_write2_b32 v0, v3, v2 offset1:8
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: simple_write2_two_val_subreg2_mixed_f32: ; GFX9-LABEL: simple_write2_two_val_subreg2_mixed_f32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v3, 3, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[1:2], v3, s[0:1] ; GFX9-NEXT: global_load_dwordx2 v[1:2], v3, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[2:3], v3, s[0:1] offset:8 ; GFX9-NEXT: global_load_dwordx2 v[2:3], v3, s[0:1] offset:8 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ds_write2_b32 v0, v1, v3 offset1:8 ; GFX9-NEXT: ds_write2_b32 v0, v1, v3 offset1:8
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%in.gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i %in.gep.0 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in, i32 %x.i
%in.gep.1 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in.gep.0, i32 1 %in.gep.1 = getelementptr <2 x float>, <2 x float> addrspace(1)* %in.gep.0, i32 1
%val0 = load volatile <2 x float>, <2 x float> addrspace(1)* %in.gep.0, align 8 %val0 = load volatile <2 x float>, <2 x float> addrspace(1)* %in.gep.0, align 8
%val1 = load volatile <2 x float>, <2 x float> addrspace(1)* %in.gep.1, align 8 %val1 = load volatile <2 x float>, <2 x float> addrspace(1)* %in.gep.1, align 8
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines
; CI-LABEL: simple_write2_two_val_max_offset_f32: ; CI-LABEL: simple_write2_two_val_max_offset_f32:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc
; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64 offset:4 ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: buffer_load_dword v1, v[0:1], s[0:3], 0 addr64 offset:4 glc
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: ds_write2_b32 v0, v2, v1 offset1:255 ; CI-NEXT: ds_write2_b32 v0, v2, v1 offset1:255
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: simple_write2_two_val_max_offset_f32: ; GFX9-LABEL: simple_write2_two_val_max_offset_f32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[0:1] ; GFX9-NEXT: global_load_dword v1, v0, s[0:1] glc
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] offset:4 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:255 ; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:255
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
%in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
%val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4
%val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4
▲ Show 20 Lines • Show All 392 Lines • ▼ Show 20 Lines
; CI-LABEL: simple_write2_two_val_f64: ; CI-LABEL: simple_write2_two_val_f64:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb ; CI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; CI-NEXT: s_mov_b32 s3, 0xf000 ; CI-NEXT: s_mov_b32 s3, 0xf000
; CI-NEXT: s_mov_b32 s2, 0 ; CI-NEXT: s_mov_b32 s2, 0
; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v0, 3, v0
; CI-NEXT: v_mov_b32_e32 v1, 0 ; CI-NEXT: v_mov_b32_e32 v1, 0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 ; CI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64 glc
; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_mov_b32 m0, -1 ; CI-NEXT: buffer_load_dwordx2 v[4:5], v[0:1], s[0:3], 0 addr64 offset:8 glc
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: s_mov_b32 m0, -1
; CI-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset1:8 ; CI-NEXT: ds_write2_b64 v0, v[2:3], v[4:5] offset1:8
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
; ;
; GFX9-LABEL: simple_write2_two_val_f64: ; GFX9-LABEL: simple_write2_two_val_f64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x2c
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1] ; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[0:1] glc
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[0:1] offset:8 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[2:3], v4, s[0:1] offset:8 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:8 ; GFX9-NEXT: ds_write2_b64 v4, v[0:1], v[2:3] offset1:8
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i %in.gep.0 = getelementptr double, double addrspace(1)* %in, i32 %x.i
%in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1 %in.gep.1 = getelementptr double, double addrspace(1)* %in.gep.0, i32 1
%val0 = load volatile double, double addrspace(1)* %in.gep.0, align 8 %val0 = load volatile double, double addrspace(1)* %in.gep.0, align 8
%val1 = load volatile double, double addrspace(1)* %in.gep.1, align 8 %val1 = load volatile double, double addrspace(1)* %in.gep.1, align 8
▲ Show 20 Lines • Show All 308 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/ds_write2st64.ll

Show All 21 Linesdefine amdgpu_kernel void @simple_write2st64_one_val_f32_0_1(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
store float %val, float addrspace(3)* %arrayidx1, align 4 store float %val, float addrspace(3)* %arrayidx1, align 4
ret void ret void
} }
; GCN-LABEL: @simple_write2st64_two_val_f32_2_5 ; GCN-LABEL: @simple_write2st64_two_val_f32_2_5
; CI-DAG: s_mov_b32 m0 ; CI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]$}} ; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} glc{{$}}
; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4{{$}} ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4 glc{{$}}
; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}} ; GCN-DAG: v_lshlrev_b32_e32 [[VPTR:v[0-9]+]], 2, v{{[0-9]+}}
; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset0:2 offset1:5
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 { define amdgpu_kernel void @simple_write2st64_two_val_f32_2_5(float addrspace(1)* %C, float addrspace(1)* %in) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
%in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
%val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4
%val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4
%add.x.0 = add nsw i32 %x.i, 128 %add.x.0 = add nsw i32 %x.i, 128
%arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.0
store float %val0, float addrspace(3)* %arrayidx0, align 4 store float %val0, float addrspace(3)* %arrayidx0, align 4
%add.x.1 = add nsw i32 %x.i, 320 %add.x.1 = add nsw i32 %x.i, 320
%arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1 %arrayidx1 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %add.x.1
store float %val1, float addrspace(3)* %arrayidx1, align 4 store float %val1, float addrspace(3)* %arrayidx1, align 4
ret void ret void
} }
; GCN-LABEL: @simple_write2st64_two_val_max_offset_f32 ; GCN-LABEL: @simple_write2st64_two_val_max_offset_f32
; CI-DAG: s_mov_b32 m0 ; CI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; CI-DAG: buffer_load_dword [[VAL0:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; CI-DAG: buffer_load_dword [[VAL1:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}{{$}} ; GFX9-DAG: global_load_dword [[VAL0:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} glc{{$}}
; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4 ; GFX9-DAG: global_load_dword [[VAL1:v[0-9]+]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:4
; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v{{[0-9]+}} ; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 2, v{{[0-9]+}}
; GCN-DAG: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]] ; GCN-DAG: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]]
; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255 ; GCN: ds_write2st64_b32 [[VPTR]], [[VAL0]], [[VAL1]] offset1:255
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 { define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f32(float addrspace(1)* %C, float addrspace(1)* %in, float addrspace(3)* %lds) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i %in.gep.0 = getelementptr float, float addrspace(1)* %in, i32 %x.i
%in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1 %in.gep.1 = getelementptr float, float addrspace(1)* %in.gep.0, i32 1
%val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4 %val0 = load volatile float, float addrspace(1)* %in.gep.0, align 4
%val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4 %val1 = load volatile float, float addrspace(1)* %in.gep.1, align 4
%arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i %arrayidx0 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %x.i
store float %val0, float addrspace(3)* %arrayidx0, align 4 store float %val0, float addrspace(3)* %arrayidx0, align 4
%add.x = add nsw i32 %x.i, 16320 %add.x = add nsw i32 %x.i, 16320
%arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %lds, i32 %add.x
store float %val1, float addrspace(3)* %arrayidx1, align 4 store float %val1, float addrspace(3)* %arrayidx1, align 4
ret void ret void
} }
; GCN-LABEL: @simple_write2st64_two_val_max_offset_f64 ; GCN-LABEL: @simple_write2st64_two_val_max_offset_f64
; CI-DAG: s_mov_b32 m0 ; CI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; CI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; CI-DAG: buffer_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; CI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 ; CI-DAG: buffer_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
; GFX9-DAG: global_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]$}} ; GFX9-DAG: global_load_dwordx2 [[VAL0:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} glc{{$}}
; GFX9-DAG: global_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:8 ; GFX9-DAG: global_load_dwordx2 [[VAL1:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} offset:8
; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 3, v{{[0-9]+}} ; GCN-DAG: v_lshlrev_b32_e32 [[SHL:v[0-9]+]], 3, v{{[0-9]+}}
; GCN-DAG: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]] ; GCN-DAG: v_add_{{i|u}}32_e32 [[VPTR:v[0-9]+]], {{(vcc, )?}}s{{[0-9]+}}, [[SHL]]
; GCN: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127 ; GCN: ds_write2st64_b64 [[VPTR]], [[VAL0]], [[VAL1]] offset0:4 offset1:127
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 { define amdgpu_kernel void @simple_write2st64_two_val_max_offset_f64(double addrspace(1)* %C, double addrspace(1)* %in, double addrspace(3)* %lds) #0 {
%x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %x.i = tail call i32 @llvm.amdgcn.workitem.id.x() #1
Show All 38 Lines

llvm/test/CodeGen/AMDGPU/expand-scalar-carry-out-select-user.ll

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0 ; GFX7-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
; GFX7-NEXT: s_and_b64 vcc, exec, vcc ; GFX7-NEXT: s_and_b64 vcc, exec, vcc
; GFX7-NEXT: s_cbranch_vccnz BB1_2 ; GFX7-NEXT: s_cbranch_vccnz BB1_2
; GFX7-NEXT: ; %bb.1: ; %bb0 ; GFX7-NEXT: ; %bb.1: ; %bb0
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 9 ; GFX7-NEXT: v_mov_b32_e32 v2, 9
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: flat_store_dword v[0:1], v2 ; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: BB1_2: ; %bb1 ; GFX7-NEXT: BB1_2: ; %bb1
; GFX7-NEXT: v_mov_b32_e32 v0, 0 ; GFX7-NEXT: v_mov_b32_e32 v0, 0
; GFX7-NEXT: v_mov_b32_e32 v2, 10 ; GFX7-NEXT: v_mov_b32_e32 v2, 10
; GFX7-NEXT: v_mov_b32_e32 v1, 0 ; GFX7-NEXT: v_mov_b32_e32 v1, 0
; GFX7-NEXT: flat_store_dword v[0:1], v2 ; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_endpgm ; GFX7-NEXT: s_endpgm
; ;
; GFX9-LABEL: s_add_co_br_user: ; GFX9-LABEL: s_add_co_br_user:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX9-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_add_i32 s1, s0, s0 ; GFX9-NEXT: s_add_i32 s1, s0, s0
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0 ; GFX9-NEXT: v_cmp_lt_u32_e32 vcc, s1, v0
; GFX9-NEXT: s_cmp_lg_u64 vcc, 0 ; GFX9-NEXT: s_cmp_lg_u64 vcc, 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: s_addc_u32 s0, s0, 0 ; GFX9-NEXT: s_addc_u32 s0, s0, 0
; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0 ; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, s0, v0
; GFX9-NEXT: s_and_b64 vcc, exec, vcc ; GFX9-NEXT: s_and_b64 vcc, exec, vcc
; GFX9-NEXT: s_cbranch_vccnz BB1_2 ; GFX9-NEXT: s_cbranch_vccnz BB1_2
; GFX9-NEXT: ; %bb.1: ; %bb0 ; GFX9-NEXT: ; %bb.1: ; %bb0
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 9 ; GFX9-NEXT: v_mov_b32_e32 v2, 9
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: BB1_2: ; %bb1 ; GFX9-NEXT: BB1_2: ; %bb1
; GFX9-NEXT: v_mov_b32_e32 v0, 0 ; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: v_mov_b32_e32 v2, 10 ; GFX9-NEXT: v_mov_b32_e32 v2, 10
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: s_add_co_br_user: ; GFX10-LABEL: s_add_co_br_user:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0 ; GFX10-NEXT: s_load_dword s0, s[4:5], 0x0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_add_i32 s1, s0, s0 ; GFX10-NEXT: s_add_i32 s1, s0, s0
; GFX10-NEXT: v_cmp_lt_u32_e64 s1, s1, s0 ; GFX10-NEXT: v_cmp_lt_u32_e64 s1, s1, s0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1 ; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s1
; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0 ; GFX10-NEXT: s_cmpk_lg_u32 s1, 0x0
; GFX10-NEXT: s_addc_u32 s0, s0, 0 ; GFX10-NEXT: s_addc_u32 s0, s0, 0
; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0 ; GFX10-NEXT: v_cmp_ge_u32_e32 vcc_lo, s0, v0
; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo ; GFX10-NEXT: s_and_b32 vcc_lo, exec_lo, vcc_lo
; GFX10-NEXT: s_cbranch_vccnz BB1_2 ; GFX10-NEXT: s_cbranch_vccnz BB1_2
; GFX10-NEXT: ; %bb.1: ; %bb0 ; GFX10-NEXT: ; %bb.1: ; %bb0
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 9 ; GFX10-NEXT: v_mov_b32_e32 v2, 9
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: BB1_2: ; %bb1 ; GFX10-NEXT: BB1_2: ; %bb1
; GFX10-NEXT: v_mov_b32_e32 v0, 0 ; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: v_mov_b32_e32 v2, 10 ; GFX10-NEXT: v_mov_b32_e32 v2, 10
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
bb: bb:
%i1 = add i32 %i, %i %i1 = add i32 %i, %i
%i2 = icmp ult i32 %i1, %i %i2 = icmp ult i32 %i1, %i
%i3 = zext i1 %i2 to i32 %i3 = zext i1 %i2 to i32
%i4 = add nuw nsw i32 %i3, 0 %i4 = add nuw nsw i32 %i3, 0
%i5 = add i32 %i4, %i %i5 = add i32 %i4, %i
%i6 = icmp ult i32 %i5, %i4 %i6 = icmp ult i32 %i5, %i4
Show All 11 Lines

llvm/test/CodeGen/AMDGPU/extload-private.ll

Show All 29 Linesentry:
%tmp0 = alloca i16, addrspace(5) %tmp0 = alloca i16, addrspace(5)
%tmp1 = load i16, i16 addrspace(5)* %tmp0 %tmp1 = load i16, i16 addrspace(5)* %tmp0
%tmp2 = sext i16 %tmp1 to i32 %tmp2 = sext i16 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}load_i16_zext_private: ; FUNC-LABEL: {{^}}load_i16_zext_private:
; SI: buffer_load_ushort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4{{$}} ; SI: buffer_load_ushort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], 0 offset:4 glc{{$}}
define amdgpu_kernel void @load_i16_zext_private(i32 addrspace(1)* %out) { define amdgpu_kernel void @load_i16_zext_private(i32 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca i16, addrspace(5) %tmp0 = alloca i16, addrspace(5)
%tmp1 = load volatile i16, i16 addrspace(5)* %tmp0 %tmp1 = load volatile i16, i16 addrspace(5)* %tmp0
%tmp2 = zext i16 %tmp1 to i32 %tmp2 = zext i16 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/extractelt-to-trunc.ll

Show First 20 Lines • Show All 100 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_mov_b32 s10, s6 ; GCN-NEXT: s_mov_b32 s10, s6
; GCN-NEXT: s_mov_b32 s11, s7 ; GCN-NEXT: s_mov_b32 s11, s7
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s2 ; GCN-NEXT: s_mov_b32 s8, s2
; GCN-NEXT: s_mov_b32 s9, s3 ; GCN-NEXT: s_mov_b32 s9, s3
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s0 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in
%elt0 = extractelement <4 x i32> %vec, i32 0 %elt0 = extractelement <4 x i32> %vec, i32 0
store i32 %elt0, i32 addrspace(1)* %out store i32 %elt0, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @no_extract_volatile_load_extract2(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { define amdgpu_kernel void @no_extract_volatile_load_extract2(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in) {
; GCN-LABEL: no_extract_volatile_load_extract2: ; GCN-LABEL: no_extract_volatile_load_extract2:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_mov_b32 s10, s6 ; GCN-NEXT: s_mov_b32 s10, s6
; GCN-NEXT: s_mov_b32 s11, s7 ; GCN-NEXT: s_mov_b32 s11, s7
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s2 ; GCN-NEXT: s_mov_b32 s8, s2
; GCN-NEXT: s_mov_b32 s9, s3 ; GCN-NEXT: s_mov_b32 s9, s3
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b32 s4, s0 ; GCN-NEXT: s_mov_b32 s4, s0
; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: s_mov_b32 s5, s1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_store_dword v2, off, s[4:7], 0 ; GCN-NEXT: buffer_store_dword v2, off, s[4:7], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in
%elt2 = extractelement <4 x i32> %vec, i32 2 %elt2 = extractelement <4 x i32> %vec, i32 2
store i32 %elt2, i32 addrspace(1)* %out store i32 %elt2, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @no_extract_volatile_load_dynextract(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx) { define amdgpu_kernel void @no_extract_volatile_load_dynextract(i32 addrspace(1)* %out, <4 x i32> addrspace(1)* %in, i32 %idx) {
; GCN-LABEL: no_extract_volatile_load_dynextract: ; GCN-LABEL: no_extract_volatile_load_dynextract:
; GCN: ; %bb.0: ; %entry ; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 ; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_load_dword s12, s[0:1], 0xd ; GCN-NEXT: s_load_dword s12, s[0:1], 0xd
; GCN-NEXT: s_mov_b32 s10, s2 ; GCN-NEXT: s_mov_b32 s10, s2
; GCN-NEXT: s_mov_b32 s11, s3 ; GCN-NEXT: s_mov_b32 s11, s3
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6 ; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7 ; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 ; GCN-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s12, 1 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s12, 1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s12, 2 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s12, 2
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s12, 3 ; GCN-NEXT: v_cmp_eq_u32_e64 vcc, s12, 3
; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc ; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
entry: entry:
%vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in %vec = load volatile <4 x i32>, <4 x i32> addrspace(1)* %in
%eltN = extractelement <4 x i32> %vec, i32 %idx %eltN = extractelement <4 x i32> %vec, i32 %idx
store i32 %eltN, i32 addrspace(1)* %out store i32 %eltN, i32 addrspace(1)* %out
ret void ret void
} }

llvm/test/CodeGen/AMDGPU/fadd-fma-fmul-combine.ll

Show First 20 Lines • Show All 225 Lines • ▼ Show 20 Lines
; GCN: buffer_load_dword [[U:v[0-9]+]] ; GCN: buffer_load_dword [[U:v[0-9]+]]
; GCN: buffer_load_dword [[V:v[0-9]+]] ; GCN: buffer_load_dword [[V:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[U]], [[V]] ; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[U]], [[V]]
; GCN-FLUSH-NEXT: v_mac_f32_e32 [[MUL]], [[X]], [[Y]] ; GCN-FLUSH-NEXT: v_mac_f32_e32 [[MUL]], [[X]], [[Y]]
; GCN-FLUSH-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[MUL]], [[Z]] ; GCN-FLUSH-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[MUL]], [[Z]]
; GCN-FLUSH-NEXT: buffer_store_dword [[MUL]] ; GCN-FLUSH-NEXT: buffer_store_dword [[MUL]]
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0)
; GCN-FLUSH-NEXT: buffer_store_dword [[SUB]] ; GCN-FLUSH-NEXT: buffer_store_dword [[SUB]]
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0)
; GCN-FASTFMA-NEXT: v_fma_f32 [[FMA:v[0-9]+]], [[X]], [[Y]], [[U]] ; GCN-FASTFMA-NEXT: v_fma_f32 [[FMA:v[0-9]+]], [[X]], [[Y]], [[U]]
; GCN-FASTFMA-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[FMA]], [[Z]] ; GCN-FASTFMA-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[FMA]], [[Z]]
; GCN-FASTFMA-NEXT: buffer_store_dword [[FMA]] ; GCN-FASTFMA-NEXT: buffer_store_dword [[FMA]]
; GCN-FASTFMA-NEXT: s_waitcnt vmcnt(0)
; GCN-FASTFMA-NEXT: buffer_store_dword [[SUB]] ; GCN-FASTFMA-NEXT: buffer_store_dword [[SUB]]
; GCN-FASTFMA-NEXT: s_waitcnt vmcnt(0)
; GCN-SLOWFMA-DAG: v_mul_f32_e32 v{{[0-9]+}}, [[X]], [[Y]] ; GCN-SLOWFMA-DAG: v_mul_f32_e32 v{{[0-9]+}}, [[X]], [[Y]]
; GCN-SLOWFMA: v_add_f32_e32 ; GCN-SLOWFMA: v_add_f32_e32
; GCN-SLOWFMA: v_sub_f32_e32 ; GCN-SLOWFMA: v_sub_f32_e32
define amdgpu_kernel void @fast_sub_fmuladd_fmul_multi_use_fmuladd_lhs() #0 { define amdgpu_kernel void @fast_sub_fmuladd_fmul_multi_use_fmuladd_lhs() #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%z = load volatile float, float addrspace(1)* undef %z = load volatile float, float addrspace(1)* undef
Show All 14 Lines
; GCN: buffer_load_dword [[U:v[0-9]+]] ; GCN: buffer_load_dword [[U:v[0-9]+]]
; GCN: buffer_load_dword [[V:v[0-9]+]] ; GCN: buffer_load_dword [[V:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[U]], [[V]] ; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[U]], [[V]]
; GCN-FLUSH-NEXT: v_mac_f32_e32 [[MUL]], [[X]], [[Y]] ; GCN-FLUSH-NEXT: v_mac_f32_e32 [[MUL]], [[X]], [[Y]]
; GCN-FLUSH-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[Z]], [[MUL]] ; GCN-FLUSH-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[Z]], [[MUL]]
; GCN-FLUSH-NEXT: buffer_store_dword [[MUL]] ; GCN-FLUSH-NEXT: buffer_store_dword [[MUL]]
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0)
; GCN-FLUSH-NEXT: buffer_store_dword [[SUB]] ; GCN-FLUSH-NEXT: buffer_store_dword [[SUB]]
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0)
; GCN-FASTFMA-NEXT: v_fma_f32 [[FMA:v[0-9]+]], [[X]], [[Y]], [[U]] ; GCN-FASTFMA-NEXT: v_fma_f32 [[FMA:v[0-9]+]], [[X]], [[Y]], [[U]]
; GCN-FASTFMA-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[Z]], [[FMA]] ; GCN-FASTFMA-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[Z]], [[FMA]]
; GCN-FASTFMA-NEXT: buffer_store_dword [[FMA]] ; GCN-FASTFMA-NEXT: buffer_store_dword [[FMA]]
; GCN-FASTFMA-NEXT: s_waitcnt vmcnt(0)
; GCN-FASTFMA-NEXT: buffer_store_dword [[SUB]] ; GCN-FASTFMA-NEXT: buffer_store_dword [[SUB]]
; GCN-FASTFMA-NEXT: s_waitcnt vmcnt(0)
; GCN-SLOWFMA-DAG: v_mul_f32_e32 v{{[0-9]+}}, [[X]], [[Y]] ; GCN-SLOWFMA-DAG: v_mul_f32_e32 v{{[0-9]+}}, [[X]], [[Y]]
; GCN-SLOWFMA: v_add_f32_e32 ; GCN-SLOWFMA: v_add_f32_e32
; GCN-SLOWFMA: v_sub_f32_e32 ; GCN-SLOWFMA: v_sub_f32_e32
define amdgpu_kernel void @fast_sub_fmuladd_fmul_multi_use_fmuladd_rhs() #0 { define amdgpu_kernel void @fast_sub_fmuladd_fmul_multi_use_fmuladd_rhs() #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%z = load volatile float, float addrspace(1)* undef %z = load volatile float, float addrspace(1)* undef
Show All 16 Lines
; GCN-DAG: v_cvt_f32_f16_e32 [[UFLOAT:v[0-9]+]], [[U]] ; GCN-DAG: v_cvt_f32_f16_e32 [[UFLOAT:v[0-9]+]], [[U]]
; GCN-DAG: v_cvt_f32_f16_e32 [[VFLOAT:v[0-9]+]], [[V]] ; GCN-DAG: v_cvt_f32_f16_e32 [[VFLOAT:v[0-9]+]], [[V]]
; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[UFLOAT]], [[VFLOAT]] ; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[UFLOAT]], [[VFLOAT]]
; GCN-FLUSH-NEXT: v_mac_f32_e32 [[MUL]], [[X]], [[Y]] ; GCN-FLUSH-NEXT: v_mac_f32_e32 [[MUL]], [[X]], [[Y]]
; GCN-FLUSH-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[MUL]], [[Z]] ; GCN-FLUSH-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[MUL]], [[Z]]
; GCN-FLUSH-NEXT: buffer_store_dword [[MUL]] ; GCN-FLUSH-NEXT: buffer_store_dword [[MUL]]
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0)
; GCN-FLUSH-NEXT: buffer_store_dword [[SUB]] ; GCN-FLUSH-NEXT: buffer_store_dword [[SUB]]
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0)
; GCN-FASTFMA-NEXT: v_fma_f32 [[FMA:v[0-9]+]], [[X]], [[Y]], [[UFLOAT]] ; GCN-FASTFMA-NEXT: v_fma_f32 [[FMA:v[0-9]+]], [[X]], [[Y]], [[UFLOAT]]
; GCN-FASTFMA-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[FMA]], [[Z]] ; GCN-FASTFMA-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[FMA]], [[Z]]
; GCN-FASTFMA-NEXT: buffer_store_dword [[FMA]] ; GCN-FASTFMA-NEXT: buffer_store_dword [[FMA]]
; GCN-FASTFMA-NEXT: s_waitcnt vmcnt(0)
; GCN-FASTFMA-NEXT: buffer_store_dword [[SUB]] ; GCN-FASTFMA-NEXT: buffer_store_dword [[SUB]]
; GCN-FASTFMA-NEXT: s_waitcnt vmcnt(0)
; GCN-SLOWFMA-DAG: v_mul_f32_e32 v{{[0-9]+}}, [[X]], [[Y]] ; GCN-SLOWFMA-DAG: v_mul_f32_e32 v{{[0-9]+}}, [[X]], [[Y]]
; GCN-SLOWFMA: v_add_f32_e32 ; GCN-SLOWFMA: v_add_f32_e32
; GCN-SLOWFMA: v_sub_f32_e32 ; GCN-SLOWFMA: v_sub_f32_e32
define amdgpu_kernel void @fast_sub_fmuladd_fpext_fmul_multi_use_fmuladd_lhs() #0 { define amdgpu_kernel void @fast_sub_fmuladd_fpext_fmul_multi_use_fmuladd_lhs() #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%z = load volatile float, float addrspace(1)* undef %z = load volatile float, float addrspace(1)* undef
Show All 17 Lines
; GCN-DAG: v_cvt_f32_f16_e32 [[UFLOAT:v[0-9]+]], [[U]] ; GCN-DAG: v_cvt_f32_f16_e32 [[UFLOAT:v[0-9]+]], [[U]]
; GCN-DAG: v_cvt_f32_f16_e32 [[VFLOAT:v[0-9]+]], [[V]] ; GCN-DAG: v_cvt_f32_f16_e32 [[VFLOAT:v[0-9]+]], [[V]]
; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[UFLOAT]], [[VFLOAT]] ; GCN-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[UFLOAT]], [[VFLOAT]]
; GCN-FLUSH-NEXT: v_mac_f32_e32 [[MUL]], [[X]], [[Y]] ; GCN-FLUSH-NEXT: v_mac_f32_e32 [[MUL]], [[X]], [[Y]]
; GCN-FLUSH-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[Z]], [[MUL]] ; GCN-FLUSH-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[Z]], [[MUL]]
; GCN-FLUSH-NEXT: buffer_store_dword [[MUL]] ; GCN-FLUSH-NEXT: buffer_store_dword [[MUL]]
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0)
; GCN-FLUSH-NEXT: buffer_store_dword [[SUB]] ; GCN-FLUSH-NEXT: buffer_store_dword [[SUB]]
; GCN-FLUSH-NEXT: s_waitcnt vmcnt(0)
; GCN-FASTFMA-NEXT: v_fma_f32 [[FMA:v[0-9]+]], [[X]], [[Y]], [[UFLOAT]] ; GCN-FASTFMA-NEXT: v_fma_f32 [[FMA:v[0-9]+]], [[X]], [[Y]], [[UFLOAT]]
; GCN-FASTFMA-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[Z]], [[FMA]] ; GCN-FASTFMA-NEXT: v_sub_f32_e32 [[SUB:v[0-9]+]], [[Z]], [[FMA]]
; GCN-FASTFMA-NEXT: buffer_store_dword [[FMA]] ; GCN-FASTFMA-NEXT: buffer_store_dword [[FMA]]
; GCN-FASTFMA-NEXT: s_waitcnt vmcnt(0)
; GCN-FASTFMA-NEXT: buffer_store_dword [[SUB]] ; GCN-FASTFMA-NEXT: buffer_store_dword [[SUB]]
; GCN-FASTFMA-NEXT: s_waitcnt vmcnt(0)
; GCN-SLOWFMA-DAG: v_mul_f32_e32 v{{[0-9]+}}, [[X]], [[Y]] ; GCN-SLOWFMA-DAG: v_mul_f32_e32 v{{[0-9]+}}, [[X]], [[Y]]
; GCN-SLOWFMA: v_add_f32_e32 ; GCN-SLOWFMA: v_add_f32_e32
; GCN-SLOWFMA: v_sub_f32_e32 ; GCN-SLOWFMA: v_sub_f32_e32
define amdgpu_kernel void @fast_sub_fmuladd_fpext_fmul_multi_use_fmuladd_rhs() #0 { define amdgpu_kernel void @fast_sub_fmuladd_fpext_fmul_multi_use_fmuladd_rhs() #0 {
%x = load volatile float, float addrspace(1)* undef %x = load volatile float, float addrspace(1)* undef
%y = load volatile float, float addrspace(1)* undef %y = load volatile float, float addrspace(1)* undef
%z = load volatile float, float addrspace(1)* undef %z = load volatile float, float addrspace(1)* undef
Show All 16 Lines

llvm/test/CodeGen/AMDGPU/flat-address-space.ll

Show First 20 Lines • Show All 195 Lines • ▼ Show 20 Lines
; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} ; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @store_flat_i8_neg_offset(i8* %fptr, i8 %x) #0 { define amdgpu_kernel void @store_flat_i8_neg_offset(i8* %fptr, i8 %x) #0 {
%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2
store volatile i8 %x, i8* %fptr.offset store volatile i8 %x, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}load_flat_i8_max_offset: ; CHECK-LABEL: {{^}}load_flat_i8_max_offset:
; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}} ; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095 glc{{$}}
; GFX10: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}
define amdgpu_kernel void @load_flat_i8_max_offset(i8* %fptr) #0 { define amdgpu_kernel void @load_flat_i8_max_offset(i8* %fptr) #0 {
%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4095 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4095
%val = load volatile i8, i8* %fptr.offset %val = load volatile i8, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}load_flat_i8_max_offset_p1: ; CHECK-LABEL: {{^}}load_flat_i8_max_offset_p1:
; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GFX10: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc dlc{{$}}
define amdgpu_kernel void @load_flat_i8_max_offset_p1(i8* %fptr) #0 { define amdgpu_kernel void @load_flat_i8_max_offset_p1(i8* %fptr) #0 {
%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4096 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4096
%val = load volatile i8, i8* %fptr.offset %val = load volatile i8, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}load_flat_i8_neg_offset: ; CHECK-LABEL: {{^}}load_flat_i8_neg_offset:
; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s ; GFX9: v_add_co_u32_e64 v{{[0-9]+}}, vcc, -2, s
; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, -1, ; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc, -1,
; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
define amdgpu_kernel void @load_flat_i8_neg_offset(i8* %fptr) #0 { define amdgpu_kernel void @load_flat_i8_neg_offset(i8* %fptr) #0 {
%fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2
%val = load volatile i8, i8* %fptr.offset %val = load volatile i8, i8* %fptr.offset
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind convergent } attributes #1 = { nounwind convergent }

llvm/test/CodeGen/AMDGPU/flat-scratch.ll

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-NEXT: s_and_b32 s0, s0, 15 ; GFX9-NEXT: s_and_b32 s0, s0, 15
; GFX9-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-NEXT: s_add_u32 s1, 4, s1 ; GFX9-NEXT: s_add_u32 s1, 4, s1
; GFX9-NEXT: scratch_store_dword off, v0, s1 ; GFX9-NEXT: scratch_store_dword off, v0, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, 4, s0 ; GFX9-NEXT: s_add_u32 s0, 4, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_sindex_kernel: ; GFX10-LABEL: store_load_sindex_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s2, s2, s5 ; GFX10-NEXT: s_add_u32 s2, s2, s5
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-NEXT: v_mov_b32_e32 v0, 15
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s1, s0, 15 ; GFX10-NEXT: s_and_b32 s1, s0, 15
; GFX10-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-NEXT: s_add_u32 s0, 4, s0 ; GFX10-NEXT: s_add_u32 s0, 4, s0
; GFX10-NEXT: s_add_u32 s1, 4, s1 ; GFX10-NEXT: s_add_u32 s1, 4, s1
; GFX10-NEXT: scratch_store_dword off, v0, s0 ; GFX10-NEXT: scratch_store_dword off, v0, s0
; GFX10-NEXT: scratch_load_dword v0, off, s1 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_sindex_kernel: ; GFX9-PAL-LABEL: store_load_sindex_kernel:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[4:5] ; GFX9-PAL-NEXT: s_getpc_b64 s[4:5]
; GFX9-PAL-NEXT: s_mov_b32 s4, s0 ; GFX9-PAL-NEXT: s_mov_b32 s4, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX9-PAL-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-PAL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s5, s5, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s5, s5, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s4, s3 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s4, s3
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15 ; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15
; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-PAL-NEXT: s_add_u32 s1, 4, s1 ; GFX9-PAL-NEXT: s_add_u32 s1, 4, s1
; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 s0, 4, s0 ; GFX9-PAL-NEXT: s_add_u32 s0, 4, s0
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_sindex_kernel: ; GFX10-PAL-LABEL: store_load_sindex_kernel:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[4:5] ; GFX10-PAL-NEXT: s_getpc_b64 s[4:5]
; GFX10-PAL-NEXT: s_mov_b32 s4, s0 ; GFX10-PAL-NEXT: s_mov_b32 s4, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s5, s5, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s5, s5, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s4, s4, s3 ; GFX10-PAL-NEXT: s_add_u32 s4, s4, s3
; GFX10-PAL-NEXT: s_addc_u32 s5, s5, 0 ; GFX10-PAL-NEXT: s_addc_u32 s5, s5, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX10-PAL-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-PAL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15 ; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15
; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-PAL-NEXT: s_add_u32 s0, 4, s0 ; GFX10-PAL-NEXT: s_add_u32 s0, 4, s0
; GFX10-PAL-NEXT: s_add_u32 s1, 4, s1 ; GFX10-PAL-NEXT: s_add_u32 s1, 4, s1
; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0 ; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define amdgpu_ps void @store_load_sindex_foo(i32 inreg %idx) { define amdgpu_ps void @store_load_sindex_foo(i32 inreg %idx) {
; GFX9-LABEL: store_load_sindex_foo: ; GFX9-LABEL: store_load_sindex_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_lshl_b32 s0, s2, 2 ; GFX9-NEXT: s_lshl_b32 s0, s2, 2
; GFX9-NEXT: s_add_u32 s0, 4, s0 ; GFX9-NEXT: s_add_u32 s0, 4, s0
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: scratch_store_dword off, v0, s0 ; GFX9-NEXT: scratch_store_dword off, v0, s0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_and_b32 s0, s2, 15 ; GFX9-NEXT: s_and_b32 s0, s2, 15
; GFX9-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-NEXT: s_add_u32 s0, 4, s0 ; GFX9-NEXT: s_add_u32 s0, 4, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_sindex_foo: ; GFX10-LABEL: store_load_sindex_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: s_and_b32 s0, s2, 15 ; GFX10-NEXT: s_and_b32 s0, s2, 15
; GFX10-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-NEXT: v_mov_b32_e32 v0, 15
; GFX10-NEXT: s_lshl_b32 s1, s2, 2 ; GFX10-NEXT: s_lshl_b32 s1, s2, 2
; GFX10-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-NEXT: s_add_u32 s1, 4, s1 ; GFX10-NEXT: s_add_u32 s1, 4, s1
; GFX10-NEXT: s_add_u32 s0, 4, s0 ; GFX10-NEXT: s_add_u32 s0, 4, s0
; GFX10-NEXT: scratch_store_dword off, v0, s1 ; GFX10-NEXT: scratch_store_dword off, v0, s1
; GFX10-NEXT: scratch_load_dword v0, off, s0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s0 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_sindex_foo: ; GFX9-PAL-LABEL: store_load_sindex_foo:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15 ; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15
; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-PAL-NEXT: s_add_u32 s1, 4, s1 ; GFX9-PAL-NEXT: s_add_u32 s1, 4, s1
; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 s0, 4, s0 ; GFX9-PAL-NEXT: s_add_u32 s0, 4, s0
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_sindex_foo: ; GFX10-PAL-LABEL: store_load_sindex_foo:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX10-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1 ; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1
; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15 ; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-PAL-NEXT: s_add_u32 s0, 4, s0 ; GFX10-PAL-NEXT: s_add_u32 s0, 4, s0
; GFX10-PAL-NEXT: s_add_u32 s1, 4, s1 ; GFX10-PAL-NEXT: s_add_u32 s1, 4, s1
; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0 ; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define amdgpu_kernel void @store_load_vindex_kernel() { define amdgpu_kernel void @store_load_vindex_kernel() {
; GFX9-LABEL: store_load_vindex_kernel: ; GFX9-LABEL: store_load_vindex_kernel:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 4 ; GFX9-NEXT: v_mov_b32_e32 v1, 4
; GFX9-NEXT: v_add_u32_e32 v2, v1, v0 ; GFX9-NEXT: v_add_u32_e32 v2, v1, v0
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: scratch_store_dword v2, v3, off ; GFX9-NEXT: scratch_store_dword v2, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_vindex_kernel: ; GFX10-LABEL: store_load_vindex_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-NEXT: v_mov_b32_e32 v1, 4
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_add_nc_u32_e32 v2, v1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v1, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, v1, v0
; GFX10-NEXT: scratch_store_dword v2, v3, off ; GFX10-NEXT: scratch_store_dword v2, v3, off
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_vindex_kernel: ; GFX9-PAL-LABEL: store_load_vindex_kernel:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 4 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 4
; GFX9-PAL-NEXT: v_add_u32_e32 v2, v1, v0 ; GFX9-PAL-NEXT: v_add_u32_e32 v2, v1, v0
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off ; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_sub_u32_e32 v0, v1, v0 ; GFX9-PAL-NEXT: v_sub_u32_e32 v0, v1, v0
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_vindex_kernel: ; GFX10-PAL-LABEL: store_load_vindex_kernel:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX10-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1 ; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1
; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 4 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 4
; GFX10-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 15
; GFX10-PAL-NEXT: v_add_nc_u32_e32 v2, v1, v0 ; GFX10-PAL-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-PAL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 ; GFX10-PAL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
; GFX10-PAL-NEXT: scratch_store_dword v2, v3, off ; GFX10-PAL-NEXT: scratch_store_dword v2, v3, off
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i2 = tail call i32 @llvm.amdgcn.workitem.id.x() %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()
%i3 = zext i32 %i2 to i64 %i3 = zext i32 %i2 to i64
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
Show All 9 Lines
; GFX9-LABEL: store_load_vindex_foo: ; GFX9-LABEL: store_load_vindex_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, s32 ; GFX9-NEXT: v_mov_b32_e32 v1, s32
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: v_lshl_add_u32 v2, v0, 2, v1 ; GFX9-NEXT: v_lshl_add_u32 v2, v0, 2, v1
; GFX9-NEXT: v_and_b32_e32 v0, v0, v3 ; GFX9-NEXT: v_and_b32_e32 v0, v0, v3
; GFX9-NEXT: scratch_store_dword v2, v3, off ; GFX9-NEXT: scratch_store_dword v2, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX9-NEXT: scratch_load_dword v0, v0, off ; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_vindex_foo: ; GFX10-LABEL: store_load_vindex_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: v_mov_b32_e32 v2, s32 ; GFX10-NEXT: v_mov_b32_e32 v2, s32
; GFX10-NEXT: v_and_b32_e32 v3, v0, v1 ; GFX10-NEXT: v_and_b32_e32 v3, v0, v1
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, v2 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, v2
; GFX10-NEXT: v_lshl_add_u32 v2, v3, 2, v2 ; GFX10-NEXT: v_lshl_add_u32 v2, v3, 2, v2
; GFX10-NEXT: scratch_store_dword v0, v1, off ; GFX10-NEXT: scratch_store_dword v0, v1, off
; GFX10-NEXT: scratch_load_dword v0, v2, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v2, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: store_load_vindex_foo: ; GFX9-PAL-LABEL: store_load_vindex_foo:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s32 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s32
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15
; GFX9-PAL-NEXT: v_lshl_add_u32 v2, v0, 2, v1 ; GFX9-PAL-NEXT: v_lshl_add_u32 v2, v0, 2, v1
; GFX9-PAL-NEXT: v_and_b32_e32 v0, v0, v3 ; GFX9-PAL-NEXT: v_and_b32_e32 v0, v0, v3
; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off ; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v1 ; GFX9-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off ; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: store_load_vindex_foo: ; GFX10-PAL-LABEL: store_load_vindex_foo:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s32 ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s32
; GFX10-PAL-NEXT: v_and_b32_e32 v3, v0, v1 ; GFX10-PAL-NEXT: v_and_b32_e32 v3, v0, v1
; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v2 ; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v2
; GFX10-PAL-NEXT: v_lshl_add_u32 v2, v3, 2, v2 ; GFX10-PAL-NEXT: v_lshl_add_u32 v2, v3, 2, v2
; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off ; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off
; GFX10-PAL-NEXT: scratch_load_dword v0, v2, off
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, v2, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
} }
define amdgpu_kernel void @zero_init_small_offset_kernel() { define amdgpu_kernel void @zero_init_small_offset_kernel() {
; GFX9-LABEL: zero_init_small_offset_kernel: ; GFX9-LABEL: zero_init_small_offset_kernel:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, 0 ; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_mov_b32 s1, s0 ; GFX9-NEXT: s_mov_b32 s1, s0
; GFX9-NEXT: s_mov_b32 s2, s0 ; GFX9-NEXT: s_mov_b32 s2, s0
; GFX9-NEXT: s_mov_b32 s3, s0 ; GFX9-NEXT: s_mov_b32 s3, s0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:272 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:272
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:288 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:288
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:304 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:304
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:320 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:320
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: zero_init_small_offset_kernel: ; GFX10-LABEL: zero_init_small_offset_kernel:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_mov_b32 s0, 0 ; GFX10-NEXT: s_mov_b32 s0, 0
; GFX10-NEXT: s_mov_b32 s1, s0 ; GFX10-NEXT: s_mov_b32 s1, s0
; GFX10-NEXT: s_mov_b32 s2, s0 ; GFX10-NEXT: s_mov_b32 s2, s0
; GFX10-NEXT: s_mov_b32 s3, s0 ; GFX10-NEXT: s_mov_b32 s3, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:272 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:272
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:288 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:288
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:304 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:304
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:320 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:320
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: zero_init_small_offset_kernel: ; GFX9-PAL-LABEL: zero_init_small_offset_kernel:
; GFX9-PAL: ; %bb.0: ; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: s_mov_b32 s0, 0 ; GFX9-PAL-NEXT: s_mov_b32 s0, 0
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_mov_b32 s1, s0 ; GFX9-PAL-NEXT: s_mov_b32 s1, s0
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_mov_b32 s3, s0 ; GFX9-PAL-NEXT: s_mov_b32 s3, s0
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:272 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:272
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:288 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:288
Show All 9 Lines
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1 ; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1
; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_mov_b32 s0, 0 ; GFX10-PAL-NEXT: s_mov_b32 s0, 0
; GFX10-PAL-NEXT: s_mov_b32 s1, s0 ; GFX10-PAL-NEXT: s_mov_b32 s1, s0
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_mov_b32 s3, s0 ; GFX10-PAL-NEXT: s_mov_b32 s3, s0
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s2
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-PAL-NEXT: v_mov_b32_e32 v3, s3
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:272 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:272
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:288 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:288
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:304 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:304
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:320 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], off offset:320
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
%padding = alloca [64 x i32], align 4, addrspace(5) %padding = alloca [64 x i32], align 4, addrspace(5)
%alloca = alloca [32 x i16], align 2, addrspace(5) %alloca = alloca [32 x i16], align 2, addrspace(5)
%pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%cast = bitcast [32 x i16] addrspace(5)* %alloca to i8 addrspace(5)* %cast = bitcast [32 x i16] addrspace(5)* %alloca to i8 addrspace(5)*
call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false) call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false)
ret void ret void
} }
define void @zero_init_small_offset_foo() { define void @zero_init_small_offset_foo() {
; GFX9-LABEL: zero_init_small_offset_foo: ; GFX9-LABEL: zero_init_small_offset_foo:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: scratch_load_dword v0, off, s32 ; GFX9-NEXT: scratch_load_dword v0, off, s32 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, 0 ; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_mov_b32 s1, s0 ; GFX9-NEXT: s_mov_b32 s1, s0
; GFX9-NEXT: s_mov_b32 s2, s0 ; GFX9-NEXT: s_mov_b32 s2, s0
; GFX9-NEXT: s_mov_b32 s3, s0 ; GFX9-NEXT: s_mov_b32 s3, s0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: zero_init_small_offset_foo: ; GFX10-LABEL: zero_init_small_offset_foo:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s32 ; GFX10-NEXT: scratch_load_dword v0, off, s32 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_mov_b32 s0, 0 ; GFX10-NEXT: s_mov_b32 s0, 0
; GFX10-NEXT: s_mov_b32 s1, s0 ; GFX10-NEXT: s_mov_b32 s1, s0
; GFX10-NEXT: s_mov_b32 s2, s0 ; GFX10-NEXT: s_mov_b32 s2, s0
; GFX10-NEXT: s_mov_b32 s3, s0 ; GFX10-NEXT: s_mov_b32 s3, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: zero_init_small_offset_foo: ; GFX9-PAL-LABEL: zero_init_small_offset_foo:
; GFX9-PAL: ; %bb.0: ; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s32 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, s32 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_mov_b32 s0, 0 ; GFX9-PAL-NEXT: s_mov_b32 s0, 0
; GFX9-PAL-NEXT: s_mov_b32 s1, s0 ; GFX9-PAL-NEXT: s_mov_b32 s1, s0
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_mov_b32 s3, s0 ; GFX9-PAL-NEXT: s_mov_b32 s3, s0
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: zero_init_small_offset_foo: ; GFX10-PAL-LABEL: zero_init_small_offset_foo:
; GFX10-PAL: ; %bb.0: ; GFX10-PAL: ; %bb.0:
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s32 ; GFX10-PAL-NEXT: scratch_load_dword v0, off, s32 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_mov_b32 s0, 0 ; GFX10-PAL-NEXT: s_mov_b32 s0, 0
; GFX10-PAL-NEXT: s_mov_b32 s1, s0 ; GFX10-PAL-NEXT: s_mov_b32 s1, s0
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_mov_b32 s3, s0 ; GFX10-PAL-NEXT: s_mov_b32 s3, s0
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s2
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-PAL-NEXT: v_mov_b32_e32 v3, s3
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:256
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:272
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:288
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], s32 offset:304
Show All 10 Lines
define amdgpu_kernel void @store_load_sindex_small_offset_kernel(i32 %idx) { define amdgpu_kernel void @store_load_sindex_small_offset_kernel(i32 %idx) {
; GFX9-LABEL: store_load_sindex_small_offset_kernel: ; GFX9-LABEL: store_load_sindex_small_offset_kernel:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-NEXT: s_and_b32 s0, s0, 15 ; GFX9-NEXT: s_and_b32 s0, s0, 15
; GFX9-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: s_add_u32 s1, 0x104, s1 ; GFX9-NEXT: s_add_u32 s1, 0x104, s1
; GFX9-NEXT: scratch_store_dword off, v0, s1 ; GFX9-NEXT: scratch_store_dword off, v0, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, 0x104, s0 ; GFX9-NEXT: s_add_u32 s0, 0x104, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_sindex_small_offset_kernel: ; GFX10-LABEL: store_load_sindex_small_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s2, s2, s5 ; GFX10-NEXT: s_add_u32 s2, s2, s5
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-NEXT: v_mov_b32_e32 v0, 15
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s1, s0, 15 ; GFX10-NEXT: s_and_b32 s1, s0, 15
; GFX10-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-NEXT: s_add_u32 s0, 0x104, s0 ; GFX10-NEXT: s_add_u32 s0, 0x104, s0
; GFX10-NEXT: s_add_u32 s1, 0x104, s1 ; GFX10-NEXT: s_add_u32 s1, 0x104, s1
; GFX10-NEXT: scratch_store_dword off, v0, s0 ; GFX10-NEXT: scratch_store_dword off, v0, s0
; GFX10-NEXT: scratch_load_dword v0, off, s1 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_sindex_small_offset_kernel: ; GFX9-PAL-LABEL: store_load_sindex_small_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[4:5] ; GFX9-PAL-NEXT: s_getpc_b64 s[4:5]
; GFX9-PAL-NEXT: s_mov_b32 s4, s0 ; GFX9-PAL-NEXT: s_mov_b32 s4, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX9-PAL-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-PAL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s5, s5, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s5, s5, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s4, s3 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s4, s3
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15 ; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15
; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX9-PAL-NEXT: s_add_u32 s1, 0x104, s1 ; GFX9-PAL-NEXT: s_add_u32 s1, 0x104, s1
; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 s0, 0x104, s0 ; GFX9-PAL-NEXT: s_add_u32 s0, 0x104, s0
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_sindex_small_offset_kernel: ; GFX10-PAL-LABEL: store_load_sindex_small_offset_kernel:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[4:5] ; GFX10-PAL-NEXT: s_getpc_b64 s[4:5]
; GFX10-PAL-NEXT: s_mov_b32 s4, s0 ; GFX10-PAL-NEXT: s_mov_b32 s4, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s5, s5, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s5, s5, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s4, s4, s3 ; GFX10-PAL-NEXT: s_add_u32 s4, s4, s3
; GFX10-PAL-NEXT: s_addc_u32 s5, s5, 0 ; GFX10-PAL-NEXT: s_addc_u32 s5, s5, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX10-PAL-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-PAL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15 ; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15
; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-PAL-NEXT: s_add_u32 s0, 0x104, s0 ; GFX10-PAL-NEXT: s_add_u32 s0, 0x104, s0
; GFX10-PAL-NEXT: s_add_u32 s1, 0x104, s1 ; GFX10-PAL-NEXT: s_add_u32 s1, 0x104, s1
; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0 ; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%padding = alloca [64 x i32], align 4, addrspace(5) %padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define amdgpu_ps void @store_load_sindex_small_offset_foo(i32 inreg %idx) { define amdgpu_ps void @store_load_sindex_small_offset_foo(i32 inreg %idx) {
; GFX9-LABEL: store_load_sindex_small_offset_foo: ; GFX9-LABEL: store_load_sindex_small_offset_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: s_lshl_b32 s0, s2, 2 ; GFX9-NEXT: s_lshl_b32 s0, s2, 2
; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_add_u32 s0, 0x104, s0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, 0x104, s0
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: scratch_store_dword off, v0, s0 ; GFX9-NEXT: scratch_store_dword off, v0, s0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_and_b32 s0, s2, 15 ; GFX9-NEXT: s_and_b32 s0, s2, 15
; GFX9-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-NEXT: s_add_u32 s0, 0x104, s0 ; GFX9-NEXT: s_add_u32 s0, 0x104, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_sindex_small_offset_foo: ; GFX10-LABEL: store_load_sindex_small_offset_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-NEXT: s_and_b32 s0, s2, 15
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_and_b32 s0, s2, 15
; GFX10-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-NEXT: v_mov_b32_e32 v0, 15
; GFX10-NEXT: s_lshl_b32 s1, s2, 2 ; GFX10-NEXT: s_lshl_b32 s1, s2, 2
; GFX10-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-NEXT: s_add_u32 s1, 0x104, s1 ; GFX10-NEXT: s_add_u32 s1, 0x104, s1
; GFX10-NEXT: s_add_u32 s0, 0x104, s0 ; GFX10-NEXT: s_add_u32 s0, 0x104, s0
; GFX10-NEXT: scratch_store_dword off, v0, s1 ; GFX10-NEXT: scratch_store_dword off, v0, s1
; GFX10-NEXT: scratch_load_dword v0, off, s0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s0 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_sindex_small_offset_foo: ; GFX9-PAL-LABEL: store_load_sindex_small_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15 ; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15
; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-PAL-NEXT: s_add_u32 s1, 0x104, s1 ; GFX9-PAL-NEXT: s_add_u32 s1, 0x104, s1
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 s0, 0x104, s0 ; GFX9-PAL-NEXT: s_add_u32 s0, 0x104, s0
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_sindex_small_offset_foo: ; GFX10-PAL-LABEL: store_load_sindex_small_offset_foo:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX10-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1 ; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1
; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-PAL-NEXT: s_add_u32 s0, 0x104, s0 ; GFX10-PAL-NEXT: s_add_u32 s0, 0x104, s0
; GFX10-PAL-NEXT: s_add_u32 s1, 0x104, s1 ; GFX10-PAL-NEXT: s_add_u32 s1, 0x104, s1
; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0 ; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%padding = alloca [64 x i32], align 4, addrspace(5) %padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define amdgpu_kernel void @store_load_vindex_small_offset_kernel() { define amdgpu_kernel void @store_load_vindex_small_offset_kernel() {
; GFX9-LABEL: store_load_vindex_small_offset_kernel: ; GFX9-LABEL: store_load_vindex_small_offset_kernel:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 ; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x104 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x104
; GFX9-NEXT: v_add_u32_e32 v2, v1, v0 ; GFX9-NEXT: v_add_u32_e32 v2, v1, v0
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: scratch_store_dword v2, v3, off ; GFX9-NEXT: scratch_store_dword v2, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_vindex_small_offset_kernel: ; GFX10-LABEL: store_load_vindex_small_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_mov_b32_e32 v1, 0x104 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x104
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_add_nc_u32_e32 v2, v1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v1, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, v1, v0
; GFX10-NEXT: scratch_load_dword v1, off, off offset:4 ; GFX10-NEXT: scratch_load_dword v1, off, off offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: scratch_store_dword v2, v3, off ; GFX10-NEXT: scratch_store_dword v2, v3, off
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_vindex_small_offset_kernel: ; GFX9-PAL-LABEL: store_load_vindex_small_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 ; GFX9-PAL-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 0x104 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 0x104
; GFX9-PAL-NEXT: v_add_u32_e32 v2, v1, v0 ; GFX9-PAL-NEXT: v_add_u32_e32 v2, v1, v0
; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off ; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_sub_u32_e32 v0, v1, v0 ; GFX9-PAL-NEXT: v_sub_u32_e32 v0, v1, v0
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_vindex_small_offset_kernel: ; GFX10-PAL-LABEL: store_load_vindex_small_offset_kernel:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX10-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1 ; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1
; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 0x104 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 0x104
; GFX10-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 15
; GFX10-PAL-NEXT: v_add_nc_u32_e32 v2, v1, v0 ; GFX10-PAL-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-PAL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 ; GFX10-PAL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
; GFX10-PAL-NEXT: scratch_load_dword v1, off, off offset:4 ; GFX10-PAL-NEXT: scratch_load_dword v1, off, off offset:4 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: scratch_store_dword v2, v3, off ; GFX10-PAL-NEXT: scratch_store_dword v2, v3, off
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%padding = alloca [64 x i32], align 4, addrspace(5) %padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i2 = tail call i32 @llvm.amdgcn.workitem.id.x() %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()
%i3 = zext i32 %i2 to i64 %i3 = zext i32 %i2 to i64
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = sub nsw i32 31, %i2 %i9 = sub nsw i32 31, %i2
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define void @store_load_vindex_small_offset_foo(i32 %idx) { define void @store_load_vindex_small_offset_foo(i32 %idx) {
; GFX9-LABEL: store_load_vindex_small_offset_foo: ; GFX9-LABEL: store_load_vindex_small_offset_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: scratch_load_dword v1, off, s32 ; GFX9-NEXT: scratch_load_dword v1, off, s32 glc
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x100
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x100
; GFX9-NEXT: v_mov_b32_e32 v1, vcc_hi ; GFX9-NEXT: v_mov_b32_e32 v1, vcc_hi
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: v_lshl_add_u32 v2, v0, 2, v1 ; GFX9-NEXT: v_lshl_add_u32 v2, v0, 2, v1
; GFX9-NEXT: v_and_b32_e32 v0, v0, v3 ; GFX9-NEXT: v_and_b32_e32 v0, v0, v3
; GFX9-NEXT: scratch_store_dword v2, v3, off ; GFX9-NEXT: scratch_store_dword v2, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX9-NEXT: scratch_load_dword v0, v0, off ; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_vindex_small_offset_foo: ; GFX10-LABEL: store_load_vindex_small_offset_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x100 ; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x100
; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo
; GFX10-NEXT: v_and_b32_e32 v3, v0, v1 ; GFX10-NEXT: v_and_b32_e32 v3, v0, v1
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, v2 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, v2
; GFX10-NEXT: v_lshl_add_u32 v2, v3, 2, v2 ; GFX10-NEXT: v_lshl_add_u32 v2, v3, 2, v2
; GFX10-NEXT: scratch_load_dword v3, off, s32 ; GFX10-NEXT: scratch_load_dword v3, off, s32 glc dlc
; GFX10-NEXT: scratch_store_dword v0, v1, off
; GFX10-NEXT: scratch_load_dword v0, v2, off
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: scratch_store_dword v0, v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v2, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: store_load_vindex_small_offset_foo: ; GFX9-PAL-LABEL: store_load_vindex_small_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dword v1, off, s32 ; GFX9-PAL-NEXT: scratch_load_dword v1, off, s32 glc
; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x100
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x100
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, vcc_hi ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, vcc_hi
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15
; GFX9-PAL-NEXT: v_lshl_add_u32 v2, v0, 2, v1 ; GFX9-PAL-NEXT: v_lshl_add_u32 v2, v0, 2, v1
; GFX9-PAL-NEXT: v_and_b32_e32 v0, v0, v3 ; GFX9-PAL-NEXT: v_and_b32_e32 v0, v0, v3
; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off ; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v1 ; GFX9-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off ; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: store_load_vindex_small_offset_foo: ; GFX10-PAL-LABEL: store_load_vindex_small_offset_foo:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x100 ; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x100
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, vcc_lo ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, vcc_lo
; GFX10-PAL-NEXT: v_and_b32_e32 v3, v0, v1 ; GFX10-PAL-NEXT: v_and_b32_e32 v3, v0, v1
; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v2 ; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v2
; GFX10-PAL-NEXT: v_lshl_add_u32 v2, v3, 2, v2 ; GFX10-PAL-NEXT: v_lshl_add_u32 v2, v3, 2, v2
; GFX10-PAL-NEXT: scratch_load_dword v3, off, s32 ; GFX10-PAL-NEXT: scratch_load_dword v3, off, s32 glc dlc
; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off
; GFX10-PAL-NEXT: scratch_load_dword v0, v2, off
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, v2, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%padding = alloca [64 x i32], align 4, addrspace(5) %padding = alloca [64 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define amdgpu_kernel void @zero_init_large_offset_kernel() { define amdgpu_kernel void @zero_init_large_offset_kernel() {
; GFX9-LABEL: zero_init_large_offset_kernel: ; GFX9-LABEL: zero_init_large_offset_kernel:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, 0 ; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_mov_b32 s1, s0 ; GFX9-NEXT: s_mov_b32 s1, s0
; GFX9-NEXT: s_mov_b32 s2, s0 ; GFX9-NEXT: s_mov_b32 s2, s0
; GFX9-NEXT: s_mov_b32 s3, s0 ; GFX9-NEXT: s_mov_b32 s3, s0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-NEXT: s_movk_i32 vcc_hi, 0x4010
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: zero_init_large_offset_kernel: ; GFX10-LABEL: zero_init_large_offset_kernel:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_mov_b32 s0, 0 ; GFX10-NEXT: s_mov_b32 s0, 0
; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010
; GFX10-NEXT: s_mov_b32 s1, s0 ; GFX10-NEXT: s_mov_b32 s1, s0
; GFX10-NEXT: s_mov_b32 s2, s0 ; GFX10-NEXT: s_mov_b32 s2, s0
; GFX10-NEXT: s_mov_b32 s3, s0 ; GFX10-NEXT: s_mov_b32 s3, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-NEXT: s_movk_i32 vcc_lo, 0x4010
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: zero_init_large_offset_kernel: ; GFX9-PAL-LABEL: zero_init_large_offset_kernel:
; GFX9-PAL: ; %bb.0: ; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: s_mov_b32 s0, 0 ; GFX9-PAL-NEXT: s_mov_b32 s0, 0
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_mov_b32 s1, s0 ; GFX9-PAL-NEXT: s_mov_b32 s1, s0
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_mov_b32 s3, s0 ; GFX9-PAL-NEXT: s_mov_b32 s3, s0
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4010
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4010 ; GFX9-PAL-NEXT: s_movk_i32 vcc_hi, 0x4010
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
Show All 9 Lines
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1 ; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1
; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_mov_b32 s0, 0 ; GFX10-PAL-NEXT: s_mov_b32 s0, 0
; GFX10-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010
; GFX10-PAL-NEXT: s_mov_b32 s1, s0 ; GFX10-PAL-NEXT: s_mov_b32 s1, s0
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_mov_b32 s3, s0 ; GFX10-PAL-NEXT: s_mov_b32 s3, s0
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s2
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-PAL-NEXT: v_mov_b32_e32 v3, s3
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
; GFX10-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
; GFX10-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010 ; GFX10-PAL-NEXT: s_movk_i32 vcc_lo, 0x4010
Show All 9 Lines; GFX10-PAL-NEXT: s_endpgm
call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false) call void @llvm.memset.p5i8.i64(i8 addrspace(5)* align 2 dereferenceable(64) %cast, i8 0, i64 64, i1 false)
ret void ret void
} }
define void @zero_init_large_offset_foo() { define void @zero_init_large_offset_foo() {
; GFX9-LABEL: zero_init_large_offset_foo: ; GFX9-LABEL: zero_init_large_offset_foo:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: scratch_load_dword v0, off, s32 ; GFX9-NEXT: scratch_load_dword v0, off, s32 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, 0 ; GFX9-NEXT: s_mov_b32 s0, 0
; GFX9-NEXT: s_mov_b32 s1, s0 ; GFX9-NEXT: s_mov_b32 s1, s0
; GFX9-NEXT: s_mov_b32 s2, s0 ; GFX9-NEXT: s_mov_b32 s2, s0
; GFX9-NEXT: s_mov_b32 s3, s0 ; GFX9-NEXT: s_mov_b32 s3, s0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-NEXT: v_mov_b32_e32 v3, s3
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000 ; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000 ; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000 ; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000 ; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 ; GFX9-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: zero_init_large_offset_foo: ; GFX10-LABEL: zero_init_large_offset_foo:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s32 ; GFX10-NEXT: scratch_load_dword v0, off, s32 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_mov_b32 s0, 0 ; GFX10-NEXT: s_mov_b32 s0, 0
; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000
; GFX10-NEXT: s_mov_b32 s1, s0 ; GFX10-NEXT: s_mov_b32 s1, s0
; GFX10-NEXT: s_mov_b32 s2, s0 ; GFX10-NEXT: s_mov_b32 s2, s0
; GFX10-NEXT: s_mov_b32 s3, s0 ; GFX10-NEXT: s_mov_b32 s3, s0
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-NEXT: v_mov_b32_e32 v1, s1
; GFX10-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-NEXT: v_mov_b32_e32 v2, s2
; GFX10-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-NEXT: v_mov_b32_e32 v3, s3
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:32
; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000
; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48 ; GFX10-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:48
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: zero_init_large_offset_foo: ; GFX9-PAL-LABEL: zero_init_large_offset_foo:
; GFX9-PAL: ; %bb.0: ; GFX9-PAL: ; %bb.0:
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s32 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, s32 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_mov_b32 s0, 0 ; GFX9-PAL-NEXT: s_mov_b32 s0, 0
; GFX9-PAL-NEXT: s_mov_b32 s1, s0 ; GFX9-PAL-NEXT: s_mov_b32 s1, s0
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_mov_b32 s3, s0 ; GFX9-PAL-NEXT: s_mov_b32 s3, s0
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, s1
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, s2
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, s3
; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000 ; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi
; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000 ; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:16
; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000 ; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:32
; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000 ; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48 ; GFX9-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_hi offset:48
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: zero_init_large_offset_foo: ; GFX10-PAL-LABEL: zero_init_large_offset_foo:
; GFX10-PAL: ; %bb.0: ; GFX10-PAL: ; %bb.0:
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s32 ; GFX10-PAL-NEXT: scratch_load_dword v0, off, s32 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_mov_b32 s0, 0 ; GFX10-PAL-NEXT: s_mov_b32 s0, 0
; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x4000
; GFX10-PAL-NEXT: s_mov_b32 s1, s0 ; GFX10-PAL-NEXT: s_mov_b32 s1, s0
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_mov_b32 s3, s0 ; GFX10-PAL-NEXT: s_mov_b32 s3, s0
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, s0 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, s0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, s1 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, s1
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s2 ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, s2
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, s3 ; GFX10-PAL-NEXT: v_mov_b32_e32 v3, s3
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo
; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x4000
; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16 ; GFX10-PAL-NEXT: scratch_store_dwordx4 off, v[0:3], vcc_lo offset:16
; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x4000
Show All 13 Lines
define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) { define amdgpu_kernel void @store_load_sindex_large_offset_kernel(i32 %idx) {
; GFX9-LABEL: store_load_sindex_large_offset_kernel: ; GFX9-LABEL: store_load_sindex_large_offset_kernel:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-NEXT: s_and_b32 s0, s0, 15 ; GFX9-NEXT: s_and_b32 s0, s0, 15
; GFX9-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: s_add_u32 s1, 0x4004, s1 ; GFX9-NEXT: s_add_u32 s1, 0x4004, s1
; GFX9-NEXT: scratch_store_dword off, v0, s1 ; GFX9-NEXT: scratch_store_dword off, v0, s1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX9-NEXT: s_add_u32 s0, 0x4004, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_sindex_large_offset_kernel: ; GFX10-LABEL: store_load_sindex_large_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s2, s2, s5 ; GFX10-NEXT: s_add_u32 s2, s2, s5
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-NEXT: v_mov_b32_e32 v0, 15
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_and_b32 s1, s0, 15 ; GFX10-NEXT: s_and_b32 s1, s0, 15
; GFX10-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX10-NEXT: s_add_u32 s0, 0x4004, s0
; GFX10-NEXT: s_add_u32 s1, 0x4004, s1 ; GFX10-NEXT: s_add_u32 s1, 0x4004, s1
; GFX10-NEXT: scratch_store_dword off, v0, s0 ; GFX10-NEXT: scratch_store_dword off, v0, s0
; GFX10-NEXT: scratch_load_dword v0, off, s1 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_sindex_large_offset_kernel: ; GFX9-PAL-LABEL: store_load_sindex_large_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[4:5] ; GFX9-PAL-NEXT: s_getpc_b64 s[4:5]
; GFX9-PAL-NEXT: s_mov_b32 s4, s0 ; GFX9-PAL-NEXT: s_mov_b32 s4, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX9-PAL-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-PAL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s5, s5, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s5, s5, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s4, s3 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s4, s3
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15 ; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15
; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX9-PAL-NEXT: s_add_u32 s1, 0x4004, s1 ; GFX9-PAL-NEXT: s_add_u32 s1, 0x4004, s1
; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX9-PAL-NEXT: s_add_u32 s0, 0x4004, s0
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_sindex_large_offset_kernel: ; GFX10-PAL-LABEL: store_load_sindex_large_offset_kernel:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[4:5] ; GFX10-PAL-NEXT: s_getpc_b64 s[4:5]
; GFX10-PAL-NEXT: s_mov_b32 s4, s0 ; GFX10-PAL-NEXT: s_mov_b32 s4, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s5, s5, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s5, s5, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s4, s4, s3 ; GFX10-PAL-NEXT: s_add_u32 s4, s4, s3
; GFX10-PAL-NEXT: s_addc_u32 s5, s5, 0 ; GFX10-PAL-NEXT: s_addc_u32 s5, s5, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX10-PAL-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-PAL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15 ; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15
; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-PAL-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX10-PAL-NEXT: s_add_u32 s0, 0x4004, s0
; GFX10-PAL-NEXT: s_add_u32 s1, 0x4004, s1 ; GFX10-PAL-NEXT: s_add_u32 s1, 0x4004, s1
; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0 ; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%padding = alloca [4096 x i32], align 4, addrspace(5) %padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define amdgpu_ps void @store_load_sindex_large_offset_foo(i32 inreg %idx) { define amdgpu_ps void @store_load_sindex_large_offset_foo(i32 inreg %idx) {
; GFX9-LABEL: store_load_sindex_large_offset_foo: ; GFX9-LABEL: store_load_sindex_large_offset_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: s_lshl_b32 s0, s2, 2 ; GFX9-NEXT: s_lshl_b32 s0, s2, 2
; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-NEXT: s_add_u32 s0, 0x4004, s0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, 0x4004, s0
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: scratch_store_dword off, v0, s0 ; GFX9-NEXT: scratch_store_dword off, v0, s0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_and_b32 s0, s2, 15 ; GFX9-NEXT: s_and_b32 s0, s2, 15
; GFX9-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX9-NEXT: s_add_u32 s0, 0x4004, s0
; GFX9-NEXT: scratch_load_dword v0, off, s0 ; GFX9-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_sindex_large_offset_foo: ; GFX10-LABEL: store_load_sindex_large_offset_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-NEXT: s_and_b32 s0, s2, 15
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_and_b32 s0, s2, 15
; GFX10-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-NEXT: v_mov_b32_e32 v0, 15
; GFX10-NEXT: s_lshl_b32 s1, s2, 2 ; GFX10-NEXT: s_lshl_b32 s1, s2, 2
; GFX10-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-NEXT: s_add_u32 s1, 0x4004, s1 ; GFX10-NEXT: s_add_u32 s1, 0x4004, s1
; GFX10-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX10-NEXT: s_add_u32 s0, 0x4004, s0
; GFX10-NEXT: scratch_store_dword off, v0, s1 ; GFX10-NEXT: scratch_store_dword off, v0, s1
; GFX10-NEXT: scratch_load_dword v0, off, s0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s0 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_sindex_large_offset_foo: ; GFX9-PAL-LABEL: store_load_sindex_large_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s1, s0, 2
; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15 ; GFX9-PAL-NEXT: s_and_b32 s0, s0, 15
; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX9-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX9-PAL-NEXT: s_add_u32 s1, 0x4004, s1 ; GFX9-PAL-NEXT: s_add_u32 s1, 0x4004, s1
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, s1
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX9-PAL-NEXT: s_add_u32 s0, 0x4004, s0
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 ; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_sindex_large_offset_foo: ; GFX10-PAL-LABEL: store_load_sindex_large_offset_foo:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX10-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1 ; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1
; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 ; GFX10-PAL-NEXT: scratch_load_dword v0, off, off offset:4 glc dlc
; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s1, s0, 15
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s0, s0, 2
; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2 ; GFX10-PAL-NEXT: s_lshl_b32 s1, s1, 2
; GFX10-PAL-NEXT: s_add_u32 s0, 0x4004, s0 ; GFX10-PAL-NEXT: s_add_u32 s0, 0x4004, s0
; GFX10-PAL-NEXT: s_add_u32 s1, 0x4004, s1 ; GFX10-PAL-NEXT: s_add_u32 s1, 0x4004, s1
; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0 ; GFX10-PAL-NEXT: scratch_store_dword off, v0, s0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s1 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%padding = alloca [4096 x i32], align 4, addrspace(5) %padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = and i32 %idx, 15 %i9 = and i32 %idx, 15
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define amdgpu_kernel void @store_load_vindex_large_offset_kernel() { define amdgpu_kernel void @store_load_vindex_large_offset_kernel() {
; GFX9-LABEL: store_load_vindex_large_offset_kernel: ; GFX9-LABEL: store_load_vindex_large_offset_kernel:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 ; GFX9-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0x4004 ; GFX9-NEXT: v_mov_b32_e32 v1, 0x4004
; GFX9-NEXT: v_add_u32_e32 v2, v1, v0 ; GFX9-NEXT: v_add_u32_e32 v2, v1, v0
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: scratch_store_dword v2, v3, off ; GFX9-NEXT: scratch_store_dword v2, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0 ; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX9-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_vindex_large_offset_kernel: ; GFX10-LABEL: store_load_vindex_large_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_mov_b32_e32 v1, 0x4004 ; GFX10-NEXT: v_mov_b32_e32 v1, 0x4004
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-NEXT: v_mov_b32_e32 v3, 15
; GFX10-NEXT: v_add_nc_u32_e32 v2, v1, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-NEXT: v_sub_nc_u32_e32 v0, v1, v0 ; GFX10-NEXT: v_sub_nc_u32_e32 v0, v1, v0
; GFX10-NEXT: scratch_load_dword v1, off, off offset:4 ; GFX10-NEXT: scratch_load_dword v1, off, off offset:4 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: scratch_store_dword v2, v3, off ; GFX10-NEXT: scratch_store_dword v2, v3, off
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_vindex_large_offset_kernel: ; GFX9-PAL-LABEL: store_load_vindex_large_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 ; GFX9-PAL-NEXT: scratch_load_dword v1, off, vcc_hi offset:4 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 0x4004 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 0x4004
; GFX9-PAL-NEXT: v_add_u32_e32 v2, v1, v0 ; GFX9-PAL-NEXT: v_add_u32_e32 v2, v1, v0
; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off ; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_sub_u32_e32 v0, v1, v0 ; GFX9-PAL-NEXT: v_sub_u32_e32 v0, v1, v0
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_vindex_large_offset_kernel: ; GFX10-PAL-LABEL: store_load_vindex_large_offset_kernel:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX10-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1 ; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1
; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 0x4004 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 0x4004
; GFX10-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-PAL-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 15
; GFX10-PAL-NEXT: v_add_nc_u32_e32 v2, v1, v0 ; GFX10-PAL-NEXT: v_add_nc_u32_e32 v2, v1, v0
; GFX10-PAL-NEXT: v_sub_nc_u32_e32 v0, v1, v0 ; GFX10-PAL-NEXT: v_sub_nc_u32_e32 v0, v1, v0
; GFX10-PAL-NEXT: scratch_load_dword v1, off, off offset:4 ; GFX10-PAL-NEXT: scratch_load_dword v1, off, off offset:4 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: scratch_store_dword v2, v3, off ; GFX10-PAL-NEXT: scratch_store_dword v2, v3, off
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:124 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%padding = alloca [4096 x i32], align 4, addrspace(5) %padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i2 = tail call i32 @llvm.amdgcn.workitem.id.x() %i2 = tail call i32 @llvm.amdgcn.workitem.id.x()
%i3 = zext i32 %i2 to i64 %i3 = zext i32 %i2 to i64
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2 %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i2
%i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)* %i8 = bitcast float addrspace(5)* %i7 to i32 addrspace(5)*
store volatile i32 15, i32 addrspace(5)* %i8, align 4 store volatile i32 15, i32 addrspace(5)* %i8, align 4
%i9 = sub nsw i32 31, %i2 %i9 = sub nsw i32 31, %i2
%i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9 %i10 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %i9
%i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)* %i11 = bitcast float addrspace(5)* %i10 to i32 addrspace(5)*
%i12 = load volatile i32, i32 addrspace(5)* %i11, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i11, align 4
ret void ret void
} }
define void @store_load_vindex_large_offset_foo(i32 %idx) { define void @store_load_vindex_large_offset_foo(i32 %idx) {
; GFX9-LABEL: store_load_vindex_large_offset_foo: ; GFX9-LABEL: store_load_vindex_large_offset_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: scratch_load_dword v1, off, s32 ; GFX9-NEXT: scratch_load_dword v1, off, s32 glc
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-NEXT: v_mov_b32_e32 v1, vcc_hi ; GFX9-NEXT: v_mov_b32_e32 v1, vcc_hi
; GFX9-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-NEXT: v_mov_b32_e32 v3, 15
; GFX9-NEXT: v_lshl_add_u32 v2, v0, 2, v1 ; GFX9-NEXT: v_lshl_add_u32 v2, v0, 2, v1
; GFX9-NEXT: v_and_b32_e32 v0, v0, v3 ; GFX9-NEXT: v_and_b32_e32 v0, v0, v3
; GFX9-NEXT: scratch_store_dword v2, v3, off ; GFX9-NEXT: scratch_store_dword v2, v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX9-NEXT: scratch_load_dword v0, v0, off ; GFX9-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_vindex_large_offset_foo: ; GFX10-LABEL: store_load_vindex_large_offset_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-NEXT: s_add_u32 vcc_lo, s32, 0x4000
; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo ; GFX10-NEXT: v_mov_b32_e32 v2, vcc_lo
; GFX10-NEXT: v_and_b32_e32 v3, v0, v1 ; GFX10-NEXT: v_and_b32_e32 v3, v0, v1
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, v2 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, v2
; GFX10-NEXT: v_lshl_add_u32 v2, v3, 2, v2 ; GFX10-NEXT: v_lshl_add_u32 v2, v3, 2, v2
; GFX10-NEXT: scratch_load_dword v3, off, s32 ; GFX10-NEXT: scratch_load_dword v3, off, s32 glc dlc
; GFX10-NEXT: scratch_store_dword v0, v1, off
; GFX10-NEXT: scratch_load_dword v0, v2, off
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: scratch_store_dword v0, v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v2, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: store_load_vindex_large_offset_foo: ; GFX9-PAL-LABEL: store_load_vindex_large_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dword v1, off, s32 ; GFX9-PAL-NEXT: scratch_load_dword v1, off, s32 glc
; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 vcc_hi, s32, 0x4000
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, vcc_hi ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, vcc_hi
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 15
; GFX9-PAL-NEXT: v_lshl_add_u32 v2, v0, 2, v1 ; GFX9-PAL-NEXT: v_lshl_add_u32 v2, v0, 2, v1
; GFX9-PAL-NEXT: v_and_b32_e32 v0, v0, v3 ; GFX9-PAL-NEXT: v_and_b32_e32 v0, v0, v3
; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off ; GFX9-PAL-NEXT: scratch_store_dword v2, v3, off
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v1 ; GFX9-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off ; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: store_load_vindex_large_offset_foo: ; GFX10-PAL-LABEL: store_load_vindex_large_offset_foo:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x4000 ; GFX10-PAL-NEXT: s_add_u32 vcc_lo, s32, 0x4000
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, vcc_lo ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, vcc_lo
; GFX10-PAL-NEXT: v_and_b32_e32 v3, v0, v1 ; GFX10-PAL-NEXT: v_and_b32_e32 v3, v0, v1
; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v2 ; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v2
; GFX10-PAL-NEXT: v_lshl_add_u32 v2, v3, 2, v2 ; GFX10-PAL-NEXT: v_lshl_add_u32 v2, v3, 2, v2
; GFX10-PAL-NEXT: scratch_load_dword v3, off, s32 ; GFX10-PAL-NEXT: scratch_load_dword v3, off, s32 glc dlc
; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off
; GFX10-PAL-NEXT: scratch_load_dword v0, v2, off
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, v2, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%padding = alloca [4096 x i32], align 4, addrspace(5) %padding = alloca [4096 x i32], align 4, addrspace(5)
%i = alloca [32 x float], align 4, addrspace(5) %i = alloca [32 x float], align 4, addrspace(5)
%pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef %pad_gep = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %padding, i32 0, i32 undef
%pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4 %pad_load = load volatile i32, i32 addrspace(5)* %pad_gep, align 4
%i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)* %i1 = bitcast [32 x float] addrspace(5)* %i to i8 addrspace(5)*
%i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx %i7 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %i, i32 0, i32 %idx
Show All 10 Lines
; GFX9-LABEL: store_load_large_imm_offset_kernel: ; GFX9-LABEL: store_load_large_imm_offset_kernel:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s0, s3
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s1, 0
; GFX9-NEXT: s_movk_i32 s0, 0x3000 ; GFX9-NEXT: s_movk_i32 s0, 0x3000
; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: v_mov_b32_e32 v0, 13
; GFX9-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-NEXT: scratch_store_dword off, v0, vcc_hi offset:4 ; GFX9-NEXT: scratch_store_dword off, v0, vcc_hi offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, 4, s0 ; GFX9-NEXT: s_add_u32 s0, 4, s0
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: scratch_store_dword off, v0, s0 offset:3712 ; GFX9-NEXT: scratch_store_dword off, v0, s0 offset:3712
; GFX9-NEXT: scratch_load_dword v0, off, s0 offset:3712 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dword v0, off, s0 offset:3712 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_large_imm_offset_kernel: ; GFX10-LABEL: store_load_large_imm_offset_kernel:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s0, s0, s3 ; GFX10-NEXT: s_add_u32 s0, s0, s3
; GFX10-NEXT: s_addc_u32 s1, s1, 0 ; GFX10-NEXT: s_addc_u32 s1, s1, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s1
; GFX10-NEXT: v_mov_b32_e32 v0, 13 ; GFX10-NEXT: v_mov_b32_e32 v0, 13
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: s_movk_i32 s0, 0x3800 ; GFX10-NEXT: s_movk_i32 s0, 0x3800
; GFX10-NEXT: s_add_u32 s0, 4, s0 ; GFX10-NEXT: s_add_u32 s0, 4, s0
; GFX10-NEXT: scratch_store_dword off, v0, off offset:4 ; GFX10-NEXT: scratch_store_dword off, v0, off offset:4
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_store_dword off, v1, s0 offset:1664 ; GFX10-NEXT: scratch_store_dword off, v1, s0 offset:1664
; GFX10-NEXT: scratch_load_dword v0, off, s0 offset:1664 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s0 offset:1664 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_large_imm_offset_kernel: ; GFX9-PAL-LABEL: store_load_large_imm_offset_kernel:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX9-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX9-PAL-NEXT: s_mov_b32 s2, s0 ; GFX9-PAL-NEXT: s_mov_b32 s2, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 13
; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0 ; GFX9-PAL-NEXT: s_mov_b32 vcc_hi, 0
; GFX9-PAL-NEXT: s_movk_i32 s0, 0x3000 ; GFX9-PAL-NEXT: s_movk_i32 s0, 0x3000
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s2, s1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-PAL-NEXT: scratch_store_dword off, v0, vcc_hi offset:4 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, vcc_hi offset:4
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 s0, 4, s0 ; GFX9-PAL-NEXT: s_add_u32 s0, 4, s0
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX9-PAL-NEXT: scratch_store_dword off, v0, s0 offset:3712 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, s0 offset:3712
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 offset:3712 ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 offset:3712 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_large_imm_offset_kernel: ; GFX10-PAL-LABEL: store_load_large_imm_offset_kernel:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[2:3] ; GFX10-PAL-NEXT: s_getpc_b64 s[2:3]
; GFX10-PAL-NEXT: s_mov_b32 s2, s0 ; GFX10-PAL-NEXT: s_mov_b32 s2, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s3, s3, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1 ; GFX10-PAL-NEXT: s_add_u32 s2, s2, s1
; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-PAL-NEXT: s_addc_u32 s3, s3, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 13 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 13
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX10-PAL-NEXT: s_movk_i32 s0, 0x3800 ; GFX10-PAL-NEXT: s_movk_i32 s0, 0x3800
; GFX10-PAL-NEXT: s_add_u32 s0, 4, s0 ; GFX10-PAL-NEXT: s_add_u32 s0, 4, s0
; GFX10-PAL-NEXT: scratch_store_dword off, v0, off offset:4 ; GFX10-PAL-NEXT: scratch_store_dword off, v0, off offset:4
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_store_dword off, v1, s0 offset:1664 ; GFX10-PAL-NEXT: scratch_store_dword off, v1, s0 offset:1664
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s0 offset:1664 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s0 offset:1664 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%i = alloca [4096 x i32], align 4, addrspace(5) %i = alloca [4096 x i32], align 4, addrspace(5)
%i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef %i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef
store volatile i32 13, i32 addrspace(5)* %i1, align 4 store volatile i32 13, i32 addrspace(5)* %i1, align 4
%i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 %i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
store volatile i32 15, i32 addrspace(5)* %i7, align 4 store volatile i32 15, i32 addrspace(5)* %i7, align 4
%i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 %i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
%i12 = load volatile i32, i32 addrspace(5)* %i10, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i10, align 4
ret void ret void
} }
define void @store_load_large_imm_offset_foo() { define void @store_load_large_imm_offset_foo() {
; GFX9-LABEL: store_load_large_imm_offset_foo: ; GFX9-LABEL: store_load_large_imm_offset_foo:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_movk_i32 s0, 0x3000 ; GFX9-NEXT: s_movk_i32 s0, 0x3000
; GFX9-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-NEXT: v_mov_b32_e32 v0, 13
; GFX9-NEXT: scratch_store_dword off, v0, s32 ; GFX9-NEXT: scratch_store_dword off, v0, s32
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_add_u32 s0, s32, s0 ; GFX9-NEXT: s_add_u32 s0, s32, s0
; GFX9-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-NEXT: v_mov_b32_e32 v0, 15
; GFX9-NEXT: scratch_store_dword off, v0, s0 offset:3712 ; GFX9-NEXT: scratch_store_dword off, v0, s0 offset:3712
; GFX9-NEXT: scratch_load_dword v0, off, s0 offset:3712 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dword v0, off, s0 offset:3712 glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_large_imm_offset_foo: ; GFX10-LABEL: store_load_large_imm_offset_foo:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v0, 13 ; GFX10-NEXT: v_mov_b32_e32 v0, 13
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: s_movk_i32 s0, 0x3800 ; GFX10-NEXT: s_movk_i32 s0, 0x3800
; GFX10-NEXT: s_add_u32 s0, s32, s0 ; GFX10-NEXT: s_add_u32 s0, s32, s0
; GFX10-NEXT: scratch_store_dword off, v0, s32 ; GFX10-NEXT: scratch_store_dword off, v0, s32
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_store_dword off, v1, s0 offset:1664 ; GFX10-NEXT: scratch_store_dword off, v1, s0 offset:1664
; GFX10-NEXT: scratch_load_dword v0, off, s0 offset:1664
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, off, s0 offset:1664 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: store_load_large_imm_offset_foo: ; GFX9-PAL-LABEL: store_load_large_imm_offset_foo:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: s_movk_i32 s0, 0x3000 ; GFX9-PAL-NEXT: s_movk_i32 s0, 0x3000
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 13 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 13
; GFX9-PAL-NEXT: scratch_store_dword off, v0, s32 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, s32
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_add_u32 s0, s32, s0 ; GFX9-PAL-NEXT: s_add_u32 s0, s32, s0
; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v0, 15
; GFX9-PAL-NEXT: scratch_store_dword off, v0, s0 offset:3712 ; GFX9-PAL-NEXT: scratch_store_dword off, v0, s0 offset:3712
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 offset:3712 ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dword v0, off, s0 offset:3712 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: store_load_large_imm_offset_foo: ; GFX10-PAL-LABEL: store_load_large_imm_offset_foo:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 13 ; GFX10-PAL-NEXT: v_mov_b32_e32 v0, 13
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX10-PAL-NEXT: s_movk_i32 s0, 0x3800 ; GFX10-PAL-NEXT: s_movk_i32 s0, 0x3800
; GFX10-PAL-NEXT: s_add_u32 s0, s32, s0 ; GFX10-PAL-NEXT: s_add_u32 s0, s32, s0
; GFX10-PAL-NEXT: scratch_store_dword off, v0, s32 ; GFX10-PAL-NEXT: scratch_store_dword off, v0, s32
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_store_dword off, v1, s0 offset:1664 ; GFX10-PAL-NEXT: scratch_store_dword off, v1, s0 offset:1664
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s0 offset:1664
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, off, s0 offset:1664 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
bb: bb:
%i = alloca [4096 x i32], align 4, addrspace(5) %i = alloca [4096 x i32], align 4, addrspace(5)
%i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef %i1 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 undef
store volatile i32 13, i32 addrspace(5)* %i1, align 4 store volatile i32 13, i32 addrspace(5)* %i1, align 4
%i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 %i7 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
store volatile i32 15, i32 addrspace(5)* %i7, align 4 store volatile i32 15, i32 addrspace(5)* %i7, align 4
%i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000 %i10 = getelementptr inbounds [4096 x i32], [4096 x i32] addrspace(5)* %i, i32 0, i32 4000
%i12 = load volatile i32, i32 addrspace(5)* %i10, align 4 %i12 = load volatile i32, i32 addrspace(5)* %i10, align 4
ret void ret void
} }
define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) { define amdgpu_kernel void @store_load_vidx_sidx_offset(i32 %sidx) {
; GFX9-LABEL: store_load_vidx_sidx_offset: ; GFX9-LABEL: store_load_vidx_sidx_offset:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; GFX9-NEXT: v_mov_b32_e32 v1, 4 ; GFX9-NEXT: v_mov_b32_e32 v1, 4
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, s0, v0 ; GFX9-NEXT: v_add_u32_e32 v0, s0, v0
; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1 ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX9-NEXT: v_mov_b32_e32 v1, 15 ; GFX9-NEXT: v_mov_b32_e32 v1, 15
; GFX9-NEXT: scratch_store_dword v0, v1, off offset:1024 ; GFX9-NEXT: scratch_store_dword v0, v1, off offset:1024
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:1024 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dword v0, v0, off offset:1024 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: store_load_vidx_sidx_offset: ; GFX10-LABEL: store_load_vidx_sidx_offset:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_add_u32 s2, s2, s5 ; GFX10-NEXT: s_add_u32 s2, s2, s5
; GFX10-NEXT: s_addc_u32 s3, s3, 0 ; GFX10-NEXT: s_addc_u32 s3, s3, 0
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s2
; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3 ; GFX10-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s3
; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0 ; GFX10-NEXT: v_add_nc_u32_e32 v0, s0, v0
; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, 4 ; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, 4
; GFX10-NEXT: scratch_store_dword v0, v1, off offset:1024 ; GFX10-NEXT: scratch_store_dword v0, v1, off offset:1024
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:1024 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dword v0, v0, off offset:1024 glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX9-PAL-LABEL: store_load_vidx_sidx_offset: ; GFX9-PAL-LABEL: store_load_vidx_sidx_offset:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_getpc_b64 s[4:5] ; GFX9-PAL-NEXT: s_getpc_b64 s[4:5]
; GFX9-PAL-NEXT: s_mov_b32 s4, s0 ; GFX9-PAL-NEXT: s_mov_b32 s4, s0
; GFX9-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX9-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX9-PAL-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX9-PAL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 4 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 4
; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-PAL-NEXT: s_and_b32 s5, s5, 0xffff ; GFX9-PAL-NEXT: s_and_b32 s5, s5, 0xffff
; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s4, s3 ; GFX9-PAL-NEXT: s_add_u32 flat_scratch_lo, s4, s3
; GFX9-PAL-NEXT: v_add_u32_e32 v0, s0, v0 ; GFX9-PAL-NEXT: v_add_u32_e32 v0, s0, v0
; GFX9-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v1 ; GFX9-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, v1
; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX9-PAL-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX9-PAL-NEXT: scratch_store_dword v0, v1, off offset:1024 ; GFX9-PAL-NEXT: scratch_store_dword v0, v1, off offset:1024
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:1024 ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dword v0, v0, off offset:1024 glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_endpgm ; GFX9-PAL-NEXT: s_endpgm
; ;
; GFX10-PAL-LABEL: store_load_vidx_sidx_offset: ; GFX10-PAL-LABEL: store_load_vidx_sidx_offset:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_getpc_b64 s[4:5] ; GFX10-PAL-NEXT: s_getpc_b64 s[4:5]
; GFX10-PAL-NEXT: s_mov_b32 s4, s0 ; GFX10-PAL-NEXT: s_mov_b32 s4, s0
; GFX10-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; GFX10-PAL-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: s_and_b32 s5, s5, 0xffff ; GFX10-PAL-NEXT: s_and_b32 s5, s5, 0xffff
; GFX10-PAL-NEXT: s_add_u32 s4, s4, s3 ; GFX10-PAL-NEXT: s_add_u32 s4, s4, s3
; GFX10-PAL-NEXT: s_addc_u32 s5, s5, 0 ; GFX10-PAL-NEXT: s_addc_u32 s5, s5, 0
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s4
; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5 ; GFX10-PAL-NEXT: s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s5
; GFX10-PAL-NEXT: s_load_dword s0, s[0:1], 0x24 ; GFX10-PAL-NEXT: s_load_dword s0, s[0:1], 0x24
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-PAL-NEXT: v_add_nc_u32_e32 v0, s0, v0 ; GFX10-PAL-NEXT: v_add_nc_u32_e32 v0, s0, v0
; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, 4 ; GFX10-PAL-NEXT: v_lshl_add_u32 v0, v0, 2, 4
; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off offset:1024 ; GFX10-PAL-NEXT: scratch_store_dword v0, v1, off offset:1024
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:1024 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dword v0, v0, off offset:1024 glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_endpgm ; GFX10-PAL-NEXT: s_endpgm
bb: bb:
%alloca = alloca [32 x i32], align 4, addrspace(5) %alloca = alloca [32 x i32], align 4, addrspace(5)
%vidx = tail call i32 @llvm.amdgcn.workitem.id.x() %vidx = tail call i32 @llvm.amdgcn.workitem.id.x()
%add1 = add nsw i32 %sidx, %vidx %add1 = add nsw i32 %sidx, %vidx
%add2 = add nsw i32 %add1, 256 %add2 = add nsw i32 %add1, 256
%gep = getelementptr inbounds [32 x i32], [32 x i32] addrspace(5)* %alloca, i32 0, i32 %add2 %gep = getelementptr inbounds [32 x i32], [32 x i32] addrspace(5)* %alloca, i32 0, i32 %add2
store volatile i32 15, i32 addrspace(5)* %gep, align 4 store volatile i32 15, i32 addrspace(5)* %gep, align 4
%load = load volatile i32, i32 addrspace(5)* %gep, align 4 %load = load volatile i32, i32 addrspace(5)* %gep, align 4
ret void ret void
} }
define void @store_load_i64_aligned(i64 addrspace(5)* nocapture %arg) { define void @store_load_i64_aligned(i64 addrspace(5)* nocapture %arg) {
; GFX9-LABEL: store_load_i64_aligned: ; GFX9-LABEL: store_load_i64_aligned:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, 15 ; GFX9-NEXT: v_mov_b32_e32 v1, 15
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_i64_aligned: ; GFX10-LABEL: store_load_i64_aligned:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: store_load_i64_aligned: ; GFX9-PAL-LABEL: store_load_i64_aligned:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 0
; GFX9-PAL-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX9-PAL-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX9-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: store_load_i64_aligned: ; GFX10-PAL-LABEL: store_load_i64_aligned:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 0
; GFX10-PAL-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX10-PAL-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX10-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
bb: bb:
store volatile i64 15, i64 addrspace(5)* %arg, align 8 store volatile i64 15, i64 addrspace(5)* %arg, align 8
%load = load volatile i64, i64 addrspace(5)* %arg, align 8 %load = load volatile i64, i64 addrspace(5)* %arg, align 8
ret void ret void
} }
define void @store_load_i64_unaligned(i64 addrspace(5)* nocapture %arg) { define void @store_load_i64_unaligned(i64 addrspace(5)* nocapture %arg) {
; GFX9-LABEL: store_load_i64_unaligned: ; GFX9-LABEL: store_load_i64_unaligned:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, 15 ; GFX9-NEXT: v_mov_b32_e32 v1, 15
; GFX9-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX9-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_i64_unaligned: ; GFX10-LABEL: store_load_i64_unaligned:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-NEXT: v_mov_b32_e32 v1, 15
; GFX10-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX10-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: store_load_i64_unaligned: ; GFX9-PAL-LABEL: store_load_i64_unaligned:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 0 ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 0
; GFX9-PAL-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX9-PAL-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX9-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: store_load_i64_unaligned: ; GFX10-PAL-LABEL: store_load_i64_unaligned:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 15
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 0 ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 0
; GFX10-PAL-NEXT: scratch_store_dwordx2 v0, v[1:2], off ; GFX10-PAL-NEXT: scratch_store_dwordx2 v0, v[1:2], off
; GFX10-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dwordx2 v[0:1], v0, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
bb: bb:
store volatile i64 15, i64 addrspace(5)* %arg, align 1 store volatile i64 15, i64 addrspace(5)* %arg, align 1
%load = load volatile i64, i64 addrspace(5)* %arg, align 1 %load = load volatile i64, i64 addrspace(5)* %arg, align 1
ret void ret void
} }
define void @store_load_v3i32_unaligned(<3 x i32> addrspace(5)* nocapture %arg) { define void @store_load_v3i32_unaligned(<3 x i32> addrspace(5)* nocapture %arg) {
; GFX9-LABEL: store_load_v3i32_unaligned: ; GFX9-LABEL: store_load_v3i32_unaligned:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: v_mov_b32_e32 v2, 2 ; GFX9-NEXT: v_mov_b32_e32 v2, 2
; GFX9-NEXT: v_mov_b32_e32 v3, 3 ; GFX9-NEXT: v_mov_b32_e32 v3, 3
; GFX9-NEXT: scratch_store_dwordx3 v0, v[1:3], off ; GFX9-NEXT: scratch_store_dwordx3 v0, v[1:3], off
; GFX9-NEXT: scratch_load_dwordx3 v[0:2], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dwordx3 v[0:2], v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_v3i32_unaligned: ; GFX10-LABEL: store_load_v3i32_unaligned:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v1, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 1
; GFX10-NEXT: v_mov_b32_e32 v2, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 2
; GFX10-NEXT: v_mov_b32_e32 v3, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 3
; GFX10-NEXT: scratch_store_dwordx3 v0, v[1:3], off ; GFX10-NEXT: scratch_store_dwordx3 v0, v[1:3], off
; GFX10-NEXT: scratch_load_dwordx3 v[0:2], v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dwordx3 v[0:2], v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: store_load_v3i32_unaligned: ; GFX9-PAL-LABEL: store_load_v3i32_unaligned:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 1
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 2 ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 2
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 3 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 3
; GFX9-PAL-NEXT: scratch_store_dwordx3 v0, v[1:3], off ; GFX9-PAL-NEXT: scratch_store_dwordx3 v0, v[1:3], off
; GFX9-PAL-NEXT: scratch_load_dwordx3 v[0:2], v0, off ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dwordx3 v[0:2], v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: store_load_v3i32_unaligned: ; GFX10-PAL-LABEL: store_load_v3i32_unaligned:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 1 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 1
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 2 ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 2
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 3 ; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 3
; GFX10-PAL-NEXT: scratch_store_dwordx3 v0, v[1:3], off ; GFX10-PAL-NEXT: scratch_store_dwordx3 v0, v[1:3], off
; GFX10-PAL-NEXT: scratch_load_dwordx3 v[0:2], v0, off
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dwordx3 v[0:2], v0, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
bb: bb:
store volatile <3 x i32> <i32 1, i32 2, i32 3>, <3 x i32> addrspace(5)* %arg, align 1 store volatile <3 x i32> <i32 1, i32 2, i32 3>, <3 x i32> addrspace(5)* %arg, align 1
%load = load volatile <3 x i32>, <3 x i32> addrspace(5)* %arg, align 1 %load = load volatile <3 x i32>, <3 x i32> addrspace(5)* %arg, align 1
ret void ret void
} }
define void @store_load_v4i32_unaligned(<4 x i32> addrspace(5)* nocapture %arg) { define void @store_load_v4i32_unaligned(<4 x i32> addrspace(5)* nocapture %arg) {
; GFX9-LABEL: store_load_v4i32_unaligned: ; GFX9-LABEL: store_load_v4i32_unaligned:
; GFX9: ; %bb.0: ; %bb ; GFX9: ; %bb.0: ; %bb
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-NEXT: v_mov_b32_e32 v1, 1
; GFX9-NEXT: v_mov_b32_e32 v2, 2 ; GFX9-NEXT: v_mov_b32_e32 v2, 2
; GFX9-NEXT: v_mov_b32_e32 v3, 3 ; GFX9-NEXT: v_mov_b32_e32 v3, 3
; GFX9-NEXT: v_mov_b32_e32 v4, 4 ; GFX9-NEXT: v_mov_b32_e32 v4, 4
; GFX9-NEXT: scratch_store_dwordx4 v0, v[1:4], off ; GFX9-NEXT: scratch_store_dwordx4 v0, v[1:4], off
; GFX9-NEXT: scratch_load_dwordx4 v[0:3], v0, off ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: scratch_load_dwordx4 v[0:3], v0, off glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: store_load_v4i32_unaligned: ; GFX10-LABEL: store_load_v4i32_unaligned:
; GFX10: ; %bb.0: ; %bb ; GFX10: ; %bb.0: ; %bb
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v1, 1 ; GFX10-NEXT: v_mov_b32_e32 v1, 1
; GFX10-NEXT: v_mov_b32_e32 v2, 2 ; GFX10-NEXT: v_mov_b32_e32 v2, 2
; GFX10-NEXT: v_mov_b32_e32 v3, 3 ; GFX10-NEXT: v_mov_b32_e32 v3, 3
; GFX10-NEXT: v_mov_b32_e32 v4, 4 ; GFX10-NEXT: v_mov_b32_e32 v4, 4
; GFX10-NEXT: scratch_store_dwordx4 v0, v[1:4], off ; GFX10-NEXT: scratch_store_dwordx4 v0, v[1:4], off
; GFX10-NEXT: scratch_load_dwordx4 v[0:3], v0, off
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: scratch_load_dwordx4 v[0:3], v0, off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-PAL-LABEL: store_load_v4i32_unaligned: ; GFX9-PAL-LABEL: store_load_v4i32_unaligned:
; GFX9-PAL: ; %bb.0: ; %bb ; GFX9-PAL: ; %bb.0: ; %bb
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 1 ; GFX9-PAL-NEXT: v_mov_b32_e32 v1, 1
; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 2 ; GFX9-PAL-NEXT: v_mov_b32_e32 v2, 2
; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 3 ; GFX9-PAL-NEXT: v_mov_b32_e32 v3, 3
; GFX9-PAL-NEXT: v_mov_b32_e32 v4, 4 ; GFX9-PAL-NEXT: v_mov_b32_e32 v4, 4
; GFX9-PAL-NEXT: scratch_store_dwordx4 v0, v[1:4], off ; GFX9-PAL-NEXT: scratch_store_dwordx4 v0, v[1:4], off
; GFX9-PAL-NEXT: scratch_load_dwordx4 v[0:3], v0, off ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: scratch_load_dwordx4 v[0:3], v0, off glc
; GFX9-PAL-NEXT: s_waitcnt vmcnt(0) ; GFX9-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX9-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX9-PAL-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-PAL-LABEL: store_load_v4i32_unaligned: ; GFX10-PAL-LABEL: store_load_v4i32_unaligned:
; GFX10-PAL: ; %bb.0: ; %bb ; GFX10-PAL: ; %bb.0: ; %bb
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-PAL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 1 ; GFX10-PAL-NEXT: v_mov_b32_e32 v1, 1
; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 2 ; GFX10-PAL-NEXT: v_mov_b32_e32 v2, 2
; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 3 ; GFX10-PAL-NEXT: v_mov_b32_e32 v3, 3
; GFX10-PAL-NEXT: v_mov_b32_e32 v4, 4 ; GFX10-PAL-NEXT: v_mov_b32_e32 v4, 4
; GFX10-PAL-NEXT: scratch_store_dwordx4 v0, v[1:4], off ; GFX10-PAL-NEXT: scratch_store_dwordx4 v0, v[1:4], off
; GFX10-PAL-NEXT: scratch_load_dwordx4 v[0:3], v0, off
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-PAL-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-PAL-NEXT: scratch_load_dwordx4 v[0:3], v0, off glc dlc
; GFX10-PAL-NEXT: s_waitcnt vmcnt(0)
; GFX10-PAL-NEXT: s_setpc_b64 s[30:31] ; GFX10-PAL-NEXT: s_setpc_b64 s[30:31]
bb: bb:
store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %arg, align 1 store volatile <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %arg, align 1
%load = load volatile <4 x i32>, <4 x i32> addrspace(5)* %arg, align 1 %load = load volatile <4 x i32>, <4 x i32> addrspace(5)* %arg, align 1
ret void ret void
} }
declare void @llvm.memset.p5i8.i64(i8 addrspace(5)* nocapture writeonly, i8, i64, i1 immarg) declare void @llvm.memset.p5i8.i64(i8 addrspace(5)* nocapture writeonly, i8, i64, i1 immarg)
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()

llvm/test/CodeGen/AMDGPU/fma-combine.ll

Show All 10 Lines
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare double @llvm.fabs.f64(double) #0 declare double @llvm.fabs.f64(double) #0
declare double @llvm.fma.f64(double, double, double) #0 declare double @llvm.fma.f64(double, double, double) #0
declare float @llvm.fma.f32(float, float, float) #0 declare float @llvm.fma.f32(float, float, float) #0
declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #0 declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #0
; (fadd (fmul x, y), z) -> (fma x, y, z) ; (fadd (fmul x, y), z) -> (fma x, y, z)
; FUNC-LABEL: {{^}}combine_to_fma_f64_0: ; FUNC-LABEL: {{^}}combine_to_fma_f64_0:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]] ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
; SI: buffer_store_dwordx2 [[RESULT]] ; SI: buffer_store_dwordx2 [[RESULT]]
define amdgpu_kernel void @combine_to_fma_f64_0(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_f64_0(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
%gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
%a = load volatile double, double addrspace(1)* %gep.0 %a = load volatile double, double addrspace(1)* %gep.0
%b = load volatile double, double addrspace(1)* %gep.1 %b = load volatile double, double addrspace(1)* %gep.1
%c = load volatile double, double addrspace(1)* %gep.2 %c = load volatile double, double addrspace(1)* %gep.2
%mul = fmul double %a, %b %mul = fmul double %a, %b
%fma = fadd double %mul, %c %fma = fadd double %mul, %c
store double %fma, double addrspace(1)* %gep.out store double %fma, double addrspace(1)* %gep.out
ret void ret void
} }
; (fadd (fmul x, y), z) -> (fma x, y, z) ; (fadd (fmul x, y), z) -> (fma x, y, z)
; FUNC-LABEL: {{^}}combine_to_fma_f64_0_2use: ; FUNC-LABEL: {{^}}combine_to_fma_f64_0_2use:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}} ; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24 glc{{$}}
; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]] ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[D]] ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[D]]
; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @combine_to_fma_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
Show All 13 Linesdefine amdgpu_kernel void @combine_to_fma_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%fma1 = fadd double %mul, %d %fma1 = fadd double %mul, %d
store volatile double %fma0, double addrspace(1)* %gep.out.0 store volatile double %fma0, double addrspace(1)* %gep.out.0
store volatile double %fma1, double addrspace(1)* %gep.out.1 store volatile double %fma1, double addrspace(1)* %gep.out.1
ret void ret void
} }
; (fadd x, (fmul y, z)) -> (fma y, z, x) ; (fadd x, (fmul y, z)) -> (fma y, z, x)
; FUNC-LABEL: {{^}}combine_to_fma_f64_1: ; FUNC-LABEL: {{^}}combine_to_fma_f64_1:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]] ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], [[C]]
; SI: buffer_store_dwordx2 [[RESULT]] ; SI: buffer_store_dwordx2 [[RESULT]]
define amdgpu_kernel void @combine_to_fma_f64_1(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_f64_1(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
%gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
%a = load volatile double, double addrspace(1)* %gep.0 %a = load volatile double, double addrspace(1)* %gep.0
%b = load volatile double, double addrspace(1)* %gep.1 %b = load volatile double, double addrspace(1)* %gep.1
%c = load volatile double, double addrspace(1)* %gep.2 %c = load volatile double, double addrspace(1)* %gep.2
%mul = fmul double %a, %b %mul = fmul double %a, %b
%fma = fadd double %c, %mul %fma = fadd double %c, %mul
store double %fma, double addrspace(1)* %gep.out store double %fma, double addrspace(1)* %gep.out
ret void ret void
} }
; (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) ; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_fma_fsub_0_f64: ; FUNC-LABEL: {{^}}combine_to_fma_fsub_0_f64:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]] ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]]
; SI: buffer_store_dwordx2 [[RESULT]] ; SI: buffer_store_dwordx2 [[RESULT]]
define amdgpu_kernel void @combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
%gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
%a = load volatile double, double addrspace(1)* %gep.0 %a = load volatile double, double addrspace(1)* %gep.0
%b = load volatile double, double addrspace(1)* %gep.1 %b = load volatile double, double addrspace(1)* %gep.1
%c = load volatile double, double addrspace(1)* %gep.2 %c = load volatile double, double addrspace(1)* %gep.2
%mul = fmul double %a, %b %mul = fmul double %a, %b
%fma = fsub double %mul, %c %fma = fsub double %mul, %c
store double %fma, double addrspace(1)* %gep.out store double %fma, double addrspace(1)* %gep.out
ret void ret void
} }
; (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) ; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_fma_fsub_f64_0_2use: ; FUNC-LABEL: {{^}}combine_to_fma_fsub_f64_0_2use:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}} ; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24 glc{{$}}
; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]] ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[C]]
; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]] ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]]
; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @combine_to_fma_fsub_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_fsub_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
Show All 13 Linesdefine amdgpu_kernel void @combine_to_fma_fsub_f64_0_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%fma1 = fsub double %mul, %d %fma1 = fsub double %mul, %d
store volatile double %fma0, double addrspace(1)* %gep.out.0 store volatile double %fma0, double addrspace(1)* %gep.out.0
store volatile double %fma1, double addrspace(1)* %gep.out.1 store volatile double %fma1, double addrspace(1)* %gep.out.1
ret void ret void
} }
; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) ; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64: ; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]] ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]]
; SI: buffer_store_dwordx2 [[RESULT]] ; SI: buffer_store_dwordx2 [[RESULT]]
define amdgpu_kernel void @combine_to_fma_fsub_1_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_fsub_1_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
%gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
%a = load volatile double, double addrspace(1)* %gep.0 %a = load volatile double, double addrspace(1)* %gep.0
%b = load volatile double, double addrspace(1)* %gep.1 %b = load volatile double, double addrspace(1)* %gep.1
%c = load volatile double, double addrspace(1)* %gep.2 %c = load volatile double, double addrspace(1)* %gep.2
%mul = fmul double %a, %b %mul = fmul double %a, %b
%fma = fsub double %c, %mul %fma = fsub double %c, %mul
store double %fma, double addrspace(1)* %gep.out store double %fma, double addrspace(1)* %gep.out
ret void ret void
} }
; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) ; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64_2use: ; FUNC-LABEL: {{^}}combine_to_fma_fsub_1_f64_2use:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}} ; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24 glc{{$}}
; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]] ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[C]]
; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[D]] ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], [[D]]
; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @combine_to_fma_fsub_1_f64_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_fsub_1_f64_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
Show All 13 Linesdefine amdgpu_kernel void @combine_to_fma_fsub_1_f64_2use(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%fma1 = fsub double %d, %mul %fma1 = fsub double %d, %mul
store volatile double %fma0, double addrspace(1)* %gep.out.0 store volatile double %fma0, double addrspace(1)* %gep.out.0
store volatile double %fma1, double addrspace(1)* %gep.out.1 store volatile double %fma1, double addrspace(1)* %gep.out.1
ret void ret void
} }
; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z)) ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64: ; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]] ; SI: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
; SI: buffer_store_dwordx2 [[RESULT]] ; SI: buffer_store_dwordx2 [[RESULT]]
define amdgpu_kernel void @combine_to_fma_fsub_2_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_fsub_2_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr double, double addrspace(1)* %gep.0, i32 1
%gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2 %gep.2 = getelementptr double, double addrspace(1)* %gep.0, i32 2
%gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid %gep.out = getelementptr double, double addrspace(1)* %out, i32 %tid
%a = load volatile double, double addrspace(1)* %gep.0 %a = load volatile double, double addrspace(1)* %gep.0
%b = load volatile double, double addrspace(1)* %gep.1 %b = load volatile double, double addrspace(1)* %gep.1
%c = load volatile double, double addrspace(1)* %gep.2 %c = load volatile double, double addrspace(1)* %gep.2
%mul = fmul double %a, %b %mul = fmul double %a, %b
%mul.neg = fsub double -0.0, %mul %mul.neg = fsub double -0.0, %mul
%fma = fsub double %mul.neg, %c %fma = fsub double %mul.neg, %c
store double %fma, double addrspace(1)* %gep.out store double %fma, double addrspace(1)* %gep.out
ret void ret void
} }
; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z)) ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_neg: ; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_neg:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}} ; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24 glc{{$}}
; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]] ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[D]] ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[D]]
; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @combine_to_fma_fsub_2_f64_2uses_neg(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_fsub_2_f64_2uses_neg(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
Show All 15 Linesdefine amdgpu_kernel void @combine_to_fma_fsub_2_f64_2uses_neg(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
store volatile double %fma0, double addrspace(1)* %gep.out.0 store volatile double %fma0, double addrspace(1)* %gep.out.0
store volatile double %fma1, double addrspace(1)* %gep.out.1 store volatile double %fma1, double addrspace(1)* %gep.out.1
ret void ret void
} }
; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z)) ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_mul: ; FUNC-LABEL: {{^}}combine_to_fma_fsub_2_f64_2uses_mul:
; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}} ; SI-DAG: buffer_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24 glc{{$}}
; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]] ; SI-DAG: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], -[[A]], [[B]], -[[C]]
; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]] ; SI-DAG: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], -[[D]]
; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT0]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_store_dwordx2 [[RESULT1]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @combine_to_fma_fsub_2_f64_2uses_mul(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 { define amdgpu_kernel void @combine_to_fma_fsub_2_f64_2uses_mul(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tid = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid %gep.0 = getelementptr double, double addrspace(1)* %in, i32 %tid
Show All 16 Linesdefine amdgpu_kernel void @combine_to_fma_fsub_2_f64_2uses_mul(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
store volatile double %fma0, double addrspace(1)* %gep.out.0 store volatile double %fma0, double addrspace(1)* %gep.out.0
store volatile double %fma1, double addrspace(1)* %gep.out.1 store volatile double %fma1, double addrspace(1)* %gep.out.1
ret void ret void
} }
; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z))) ; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_0_f64: ; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_0_f64:
; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}} ; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:32{{$}} ; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:32 glc{{$}}
; SI-SAFE: v_mul_f64 [[TMP0:v\[[0-9]+:[0-9]+\]]], [[U]], [[V]] ; SI-SAFE: v_mul_f64 [[TMP0:v\[[0-9]+:[0-9]+\]]], [[U]], [[V]]
; SI-SAFE: v_fma_f64 [[TMP1:v\[[0-9]+:[0-9]+\]]], [[X]], [[Y]], [[TMP0]] ; SI-SAFE: v_fma_f64 [[TMP1:v\[[0-9]+:[0-9]+\]]], [[X]], [[Y]], [[TMP0]]
; SI-SAFE: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[TMP1]], -[[Z]] ; SI-SAFE: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[TMP1]], -[[Z]]
; SI-UNSAFE: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], [[U]], [[V]], -[[Z]] ; SI-UNSAFE: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], [[U]], [[V]], -[[Z]]
; SI-UNSAFE: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[X]], [[Y]], [[FMA0]] ; SI-UNSAFE: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[X]], [[Y]], [[FMA0]]
Show All 20 Linesdefine amdgpu_kernel void @aggressive_combine_to_fma_fsub_0_f64(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in) #1 {
store double %tmp2, double addrspace(1)* %gep.out store double %tmp2, double addrspace(1)* %gep.out
ret void ret void
} }
; fold (fsub x, (fma y, z, (fmul u, v))) ; fold (fsub x, (fma y, z, (fmul u, v)))
; -> (fma (fneg y), z, (fma (fneg u), v, x)) ; -> (fma (fneg y), z, (fma (fneg u), v, x))
; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_1_f64: ; FUNC-LABEL: {{^}}aggressive_combine_to_fma_fsub_1_f64:
; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dwordx2 [[X:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dwordx2 [[Y:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dwordx2 [[Z:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24{{$}} ; SI-DAG: buffer_load_dwordx2 [[U:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:24 glc{{$}}
; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:32{{$}} ; SI-DAG: buffer_load_dwordx2 [[V:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:32 glc{{$}}
; SI-SAFE: v_mul_f64 [[TMP0:v\[[0-9]+:[0-9]+\]]], [[U]], [[V]] ; SI-SAFE: v_mul_f64 [[TMP0:v\[[0-9]+:[0-9]+\]]], [[U]], [[V]]
; SI-SAFE: v_fma_f64 [[TMP1:v\[[0-9]+:[0-9]+\]]], [[Y]], [[Z]], [[TMP0]] ; SI-SAFE: v_fma_f64 [[TMP1:v\[[0-9]+:[0-9]+\]]], [[Y]], [[Z]], [[TMP0]]
; SI-SAFE: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[X]], -[[TMP1]] ; SI-SAFE: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[X]], -[[TMP1]]
; SI-UNSAFE: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], -[[U]], [[V]], [[X]] ; SI-UNSAFE: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], -[[U]], [[V]], [[X]]
; SI-UNSAFE: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[Y]], [[Z]], [[FMA0]] ; SI-UNSAFE: v_fma_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], -[[Y]], [[Z]], [[FMA0]]
▲ Show 20 Lines • Show All 341 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/fmax3.f64.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
declare double @llvm.maxnum.f64(double, double) nounwind readnone declare double @llvm.maxnum.f64(double, double) nounwind readnone
; SI-LABEL: {{^}}test_fmax3_f64: ; SI-LABEL: {{^}}test_fmax3_f64:
; SI: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}} ; SI: buffer_load_dwordx2 [[REGA:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 glc{{$}}
; SI: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8 ; SI: buffer_load_dwordx2 [[REGB:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8
; SI: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:16 ; SI: buffer_load_dwordx2 [[REGC:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:16
; SI: v_max_f64 [[QUIET_A:v\[[0-9]+:[0-9]+\]]], [[REGA]], [[REGA]] ; SI: v_max_f64 [[QUIET_A:v\[[0-9]+:[0-9]+\]]], [[REGA]], [[REGA]]
; SI: v_max_f64 [[QUIET_B:v\[[0-9]+:[0-9]+\]]], [[REGB]], [[REGB]] ; SI: v_max_f64 [[QUIET_B:v\[[0-9]+:[0-9]+\]]], [[REGB]], [[REGB]]
; SI: v_max_f64 [[MAX0:v\[[0-9]+:[0-9]+\]]], [[QUIET_A]], [[QUIET_B]] ; SI: v_max_f64 [[MAX0:v\[[0-9]+:[0-9]+\]]], [[QUIET_A]], [[QUIET_B]]
; SI: v_max_f64 [[QUIET_C:v\[[0-9]+:[0-9]+\]]], [[REGC]], [[REGC]] ; SI: v_max_f64 [[QUIET_C:v\[[0-9]+:[0-9]+\]]], [[REGC]], [[REGC]]
; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[MAX0]], [[QUIET_C]] ; SI: v_max_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[MAX0]], [[QUIET_C]]
; SI: buffer_store_dwordx2 [[RESULT]], ; SI: buffer_store_dwordx2 [[RESULT]],
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/fneg-combines.ll

Show All 31 Lines
} }
; GCN-LABEL: {{^}}v_fneg_add_store_use_add_f32: ; GCN-LABEL: {{^}}v_fneg_add_store_use_add_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN-DAG: v_add_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]] ; GCN-DAG: v_add_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
; GCN-DAG: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], 0x80000000, [[ADD]] ; GCN-DAG: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], 0x80000000, [[ADD]]
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ADD]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ADD]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_add_store_use_add_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 { define amdgpu_kernel void @v_fneg_add_store_use_add_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%b = load volatile float, float addrspace(1)* %b.gep %b = load volatile float, float addrspace(1)* %b.gep
Show All 11 Lines
; GCN-SAFE: v_add_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]] ; GCN-SAFE: v_add_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
; GCN-SAFE: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], 0x80000000, [[ADD]] ; GCN-SAFE: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], 0x80000000, [[ADD]]
; GCN-SAFE: v_mul_f32_e32 [[MUL:v[0-9]+]], 4.0, [[ADD]] ; GCN-SAFE: v_mul_f32_e32 [[MUL:v[0-9]+]], 4.0, [[ADD]]
; GCN-NSZ: v_sub_f32_e64 [[NEG_ADD:v[0-9]+]], -[[A]], [[B]] ; GCN-NSZ: v_sub_f32_e64 [[NEG_ADD:v[0-9]+]], -[[A]], [[B]]
; GCN-NSZ-NEXT: v_mul_f32_e32 [[MUL:v[0-9]+]], -4.0, [[NEG_ADD]] ; GCN-NSZ-NEXT: v_mul_f32_e32 [[MUL:v[0-9]+]], -4.0, [[NEG_ADD]]
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_add_multi_use_add_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 { define amdgpu_kernel void @v_fneg_add_multi_use_add_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%b = load volatile float, float addrspace(1)* %b.gep %b = load volatile float, float addrspace(1)* %b.gep
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lines
; GCN-SAFE: v_xor_b32_e32 [[NEG_A:v[0-9]+]], [[SIGNBIT]], [[A]] ; GCN-SAFE: v_xor_b32_e32 [[NEG_A:v[0-9]+]], [[SIGNBIT]], [[A]]
; GCN-SAFE: v_sub_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]] ; GCN-SAFE: v_sub_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
; GCN-SAFE: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], [[SIGNBIT]], [[ADD]] ; GCN-SAFE: v_xor_b32_e32 [[NEG_ADD:v[0-9]+]], [[SIGNBIT]], [[ADD]]
; GCN-NSZ-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]] ; GCN-NSZ-DAG: v_xor_b32_e32 [[NEG_A:v[0-9]+]], 0x80000000, [[A]]
; GCN-NSZ-DAG: v_sub_f32_e32 [[NEG_ADD:v[0-9]+]], [[A]], [[B]] ; GCN-NSZ-DAG: v_sub_f32_e32 [[NEG_ADD:v[0-9]+]], [[A]], [[B]]
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]]
; GCN-NSZ-NEXT: s_waitcnt vmcnt(0)
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_A]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_A]]
; GCN-NSZ-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_add_store_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 { define amdgpu_kernel void @v_fneg_add_store_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%b = load volatile float, float addrspace(1)* %b.gep %b = load volatile float, float addrspace(1)* %b.gep
Show All 11 Lines
; GCN-SAFE-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}} ; GCN-SAFE-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
; GCN-SAFE-DAG: v_sub_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]] ; GCN-SAFE-DAG: v_sub_f32_e32 [[ADD:v[0-9]+]], [[B]], [[A]]
; GCN-SAFE-DAG: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[ADD]] ; GCN-SAFE-DAG: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[ADD]]
; GCN-NSZ-DAG: v_sub_f32_e32 [[NEG_ADD:v[0-9]+]], [[A]], [[B]] ; GCN-NSZ-DAG: v_sub_f32_e32 [[NEG_ADD:v[0-9]+]], [[A]], [[B]]
; GCN-NSZ-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}} ; GCN-NSZ-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_ADD]]
; GCN-NSZ-NEXT: s_waitcnt vmcnt(0)
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
; GCN-NSZ-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_add_multi_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float %c) #0 { define amdgpu_kernel void @v_fneg_add_multi_use_fneg_x_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float %c) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%b = load volatile float, float addrspace(1)* %b.gep %b = load volatile float, float addrspace(1)* %b.gep
▲ Show 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}v_fneg_mul_multi_use_mul_f32: ; GCN-LABEL: {{^}}v_fneg_mul_multi_use_mul_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN: v_mul_f32_e64 [[MUL0:v[0-9]+]], [[A]], -[[B]] ; GCN: v_mul_f32_e64 [[MUL0:v[0-9]+]], [[A]], -[[B]]
; GCN-NEXT: v_mul_f32_e32 [[MUL1:v[0-9]+]], -4.0, [[MUL0]] ; GCN-NEXT: v_mul_f32_e32 [[MUL1:v[0-9]+]], -4.0, [[MUL0]]
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL0]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL0]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_mul_multi_use_mul_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 { define amdgpu_kernel void @v_fneg_mul_multi_use_mul_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%b = load volatile float, float addrspace(1)* %b.gep %b = load volatile float, float addrspace(1)* %b.gep
▲ Show 20 Lines • Show All 481 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}v_fneg_minnum_multi_use_minnum_f32_ieee: ; GCN-LABEL: {{^}}v_fneg_minnum_multi_use_minnum_f32_ieee:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[NEG_QUIET_A:v[0-9]+]], -1.0, [[A]] ; GCN-DAG: v_mul_f32_e32 [[NEG_QUIET_A:v[0-9]+]], -1.0, [[A]]
; GCN-DAG: v_mul_f32_e32 [[NEG_QUIET_B:v[0-9]+]], -1.0, [[B]] ; GCN-DAG: v_mul_f32_e32 [[NEG_QUIET_B:v[0-9]+]], -1.0, [[B]]
; GCN: v_max_f32_e32 [[MAX0:v[0-9]+]], [[NEG_QUIET_A]], [[NEG_QUIET_B]] ; GCN: v_max_f32_e32 [[MAX0:v[0-9]+]], [[NEG_QUIET_A]], [[NEG_QUIET_B]]
; GCN-NEXT: v_mul_f32_e32 [[MUL1:v[0-9]+]], -4.0, [[MAX0]] ; GCN-NEXT: v_mul_f32_e32 [[MUL1:v[0-9]+]], -4.0, [[MAX0]]
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MAX0]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MAX0]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_minnum_multi_use_minnum_f32_ieee(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 { define amdgpu_kernel void @v_fneg_minnum_multi_use_minnum_f32_ieee(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%b = load volatile float, float addrspace(1)* %b.gep %b = load volatile float, float addrspace(1)* %b.gep
▲ Show 20 Lines • Show All 219 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}v_fneg_maxnum_multi_use_maxnum_f32_ieee: ; GCN-LABEL: {{^}}v_fneg_maxnum_multi_use_maxnum_f32_ieee:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN-DAG: v_mul_f32_e32 [[NEG_QUIET_A:v[0-9]+]], -1.0, [[A]] ; GCN-DAG: v_mul_f32_e32 [[NEG_QUIET_A:v[0-9]+]], -1.0, [[A]]
; GCN-DAG: v_mul_f32_e32 [[NEG_QUIET_B:v[0-9]+]], -1.0, [[B]] ; GCN-DAG: v_mul_f32_e32 [[NEG_QUIET_B:v[0-9]+]], -1.0, [[B]]
; GCN: v_min_f32_e32 [[MAX0:v[0-9]+]], [[NEG_QUIET_A]], [[NEG_QUIET_B]] ; GCN: v_min_f32_e32 [[MAX0:v[0-9]+]], [[NEG_QUIET_A]], [[NEG_QUIET_B]]
; GCN-NEXT: v_mul_f32_e32 [[MUL1:v[0-9]+]], -4.0, [[MAX0]] ; GCN-NEXT: v_mul_f32_e32 [[MUL1:v[0-9]+]], -4.0, [[MAX0]]
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MAX0]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MAX0]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_maxnum_multi_use_maxnum_f32_ieee(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 { define amdgpu_kernel void @v_fneg_maxnum_multi_use_maxnum_f32_ieee(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%b = load volatile float, float addrspace(1)* %b.gep %b = load volatile float, float addrspace(1)* %b.gep
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}v_fneg_fma_store_use_fma_f32: ; GCN-LABEL: {{^}}v_fneg_fma_store_use_fma_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
; GCN-DAG: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], [[C]] ; GCN-DAG: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], [[C]]
; GCN-DAG: v_xor_b32_e32 [[NEG_FMA:v[0-9]+]], 0x80000000, [[FMA]] ; GCN-DAG: v_xor_b32_e32 [[NEG_FMA:v[0-9]+]], 0x80000000, [[FMA]]
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_FMA]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_FMA]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FMA]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FMA]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_fma_store_use_fma_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 { define amdgpu_kernel void @v_fneg_fma_store_use_fma_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext %c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
Show All 14 Lines
; GCN-SAFE: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], [[C]] ; GCN-SAFE: v_fma_f32 [[FMA:v[0-9]+]], [[A]], [[B]], [[C]]
; GCN-SAFE: v_xor_b32_e32 [[NEG_FMA:v[0-9]+]], 0x80000000, [[FMA]] ; GCN-SAFE: v_xor_b32_e32 [[NEG_FMA:v[0-9]+]], 0x80000000, [[FMA]]
; GCN-SAFE: v_mul_f32_e32 [[MUL:v[0-9]+]], 4.0, [[FMA]] ; GCN-SAFE: v_mul_f32_e32 [[MUL:v[0-9]+]], 4.0, [[FMA]]
; GCN-NSZ: v_fma_f32 [[NEG_FMA:v[0-9]+]], [[A]], -[[B]], -[[C]] ; GCN-NSZ: v_fma_f32 [[NEG_FMA:v[0-9]+]], [[A]], -[[B]], -[[C]]
; GCN-NSZ-NEXT: v_mul_f32_e32 [[MUL:v[0-9]+]], -4.0, [[NEG_FMA]] ; GCN-NSZ-NEXT: v_mul_f32_e32 [[MUL:v[0-9]+]], -4.0, [[NEG_FMA]]
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_FMA]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_FMA]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_fma_multi_use_fma_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 { define amdgpu_kernel void @v_fneg_fma_multi_use_fma_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext %c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines
; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
; GCN-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}} ; GCN-DAG: v_mul_f32_e64 [[MUL:v[0-9]+]], -[[A]], s{{[0-9]+}}
; GCN-SAFE-DAG: v_fma_f32 [[FMA:v[0-9]+]] ; GCN-SAFE-DAG: v_fma_f32 [[FMA:v[0-9]+]]
; GCN-SAFE-DAG: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[FMA]] ; GCN-SAFE-DAG: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, [[FMA]]
; GCN-NSZ-DAG: v_fma_f32 [[NEG_FMA:v[0-9]+]], [[A]], [[B]], -[[C]] ; GCN-NSZ-DAG: v_fma_f32 [[NEG_FMA:v[0-9]+]], [[A]], [[B]], -[[C]]
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_FMA]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_FMA]]
; GCN-NSZ-NEXT: s_waitcnt vmcnt(0)
; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] ; GCN-NSZ-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
; GCN-NSZ-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_fma_multi_use_fneg_x_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr, float %d) #0 { define amdgpu_kernel void @v_fneg_fma_multi_use_fneg_x_y_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr, float %d) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext %c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; GCN-SAFE: v_mac_f32_e32 [[C]], [[A]], [[B]] ; GCN-SAFE: v_mac_f32_e32 [[C]], [[A]], [[B]]
; GCN-SAFE: v_xor_b32_e32 [[NEG_MAD:v[0-9]+]], 0x80000000, [[C]] ; GCN-SAFE: v_xor_b32_e32 [[NEG_MAD:v[0-9]+]], 0x80000000, [[C]]
; GCN-SAFE-NEXT: v_mul_f32_e32 [[MUL:v[0-9]+]], 4.0, [[C]] ; GCN-SAFE-NEXT: v_mul_f32_e32 [[MUL:v[0-9]+]], 4.0, [[C]]
; GCN-NSZ: v_mad_f32 [[NEG_MAD:v[0-9]+]], [[A]], -[[B]], -[[C]] ; GCN-NSZ: v_mad_f32 [[NEG_MAD:v[0-9]+]], [[A]], -[[B]], -[[C]]
; GCN-NSZ-NEXT: v_mul_f32_e32 [[MUL:v[0-9]+]], -4.0, [[NEG_MAD]] ; GCN-NSZ-NEXT: v_mul_f32_e32 [[MUL:v[0-9]+]], -4.0, [[NEG_MAD]]
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_MAD]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_MAD]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_fmad_multi_use_fmad_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 { define amdgpu_kernel void @v_fneg_fmad_multi_use_fmad_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext %c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
▲ Show 20 Lines • Show All 408 Lines • ▼ Show 20 Lines
} }
; GCN-LABEL: {{^}}v_fneg_mul_legacy_store_use_mul_legacy_f32: ; GCN-LABEL: {{^}}v_fneg_mul_legacy_store_use_mul_legacy_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN-DAG: v_mul_legacy_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]] ; GCN-DAG: v_mul_legacy_f32_e32 [[ADD:v[0-9]+]], [[A]], [[B]]
; GCN-DAG: v_xor_b32_e32 [[NEG_MUL_LEGACY:v[0-9]+]], 0x80000000, [[ADD]] ; GCN-DAG: v_xor_b32_e32 [[NEG_MUL_LEGACY:v[0-9]+]], 0x80000000, [[ADD]]
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_MUL_LEGACY]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[NEG_MUL_LEGACY]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ADD]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ADD]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_mul_legacy_store_use_mul_legacy_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 { define amdgpu_kernel void @v_fneg_mul_legacy_store_use_mul_legacy_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%b = load volatile float, float addrspace(1)* %b.gep %b = load volatile float, float addrspace(1)* %b.gep
%mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b) %mul = call float @llvm.amdgcn.fmul.legacy(float %a, float %b)
%fneg = fneg float %mul %fneg = fneg float %mul
store volatile float %fneg, float addrspace(1)* %out store volatile float %fneg, float addrspace(1)* %out
store volatile float %mul, float addrspace(1)* %out store volatile float %mul, float addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_fneg_mul_legacy_multi_use_mul_legacy_f32: ; GCN-LABEL: {{^}}v_fneg_mul_legacy_multi_use_mul_legacy_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN: v_mul_legacy_f32_e64 [[ADD:v[0-9]+]], [[A]], -[[B]] ; GCN: v_mul_legacy_f32_e64 [[ADD:v[0-9]+]], [[A]], -[[B]]
; GCN-NEXT: v_mul_legacy_f32_e64 [[MUL:v[0-9]+]], -[[ADD]], 4.0 ; GCN-NEXT: v_mul_legacy_f32_e64 [[MUL:v[0-9]+]], -[[ADD]], 4.0
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ADD]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[ADD]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @v_fneg_mul_legacy_multi_use_mul_legacy_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 { define amdgpu_kernel void @v_fneg_mul_legacy_multi_use_mul_legacy_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%b = load volatile float, float addrspace(1)* %b.gep %b = load volatile float, float addrspace(1)* %b.gep
▲ Show 20 Lines • Show All 418 Lines • ▼ Show 20 Lines
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
; GCN: v_fma_f32 [[FMA0:v[0-9]+]], -[[A]], [[B]], [[C]] ; GCN: v_fma_f32 [[FMA0:v[0-9]+]], -[[A]], [[B]], [[C]]
; GCN-NEXT: v_fma_f32 [[FMA1:v[0-9]+]], -[[A]], [[C]], 2.0 ; GCN-NEXT: v_fma_f32 [[FMA1:v[0-9]+]], -[[A]], [[C]], 2.0
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FMA0]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FMA0]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FMA1]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FMA1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @multiuse_fneg_2_vop3_users_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 { define amdgpu_kernel void @multiuse_fneg_2_vop3_users_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext %c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
Show All 15 Lines
; GCN-LABEL: {{^}}multiuse_fneg_2_vop2_users_f32: ; GCN-LABEL: {{^}}multiuse_fneg_2_vop2_users_f32:
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
; GCN: v_mul_f32_e64 [[MUL0:v[0-9]+]], -[[A]], [[B]] ; GCN: v_mul_f32_e64 [[MUL0:v[0-9]+]], -[[A]], [[B]]
; GCN: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[A]], [[C]] ; GCN: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[A]], [[C]]
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL0]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL0]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @multiuse_fneg_2_vop2_users_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 { define amdgpu_kernel void @multiuse_fneg_2_vop2_users_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext %c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
Show All 14 Lines
; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[B:v[0-9]+]]
; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]] ; GCN: {{buffer|flat}}_load_dword [[C:v[0-9]+]]
; GCN: v_fma_f32 [[FMA0:v[0-9]+]], -[[A]], [[B]], 2.0 ; GCN: v_fma_f32 [[FMA0:v[0-9]+]], -[[A]], [[B]], 2.0
; GCN: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[A]], [[C]] ; GCN: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[A]], [[C]]
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FMA0]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FMA0]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @multiuse_fneg_vop2_vop3_users_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 { define amdgpu_kernel void @multiuse_fneg_vop2_vop3_users_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext %c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
Show All 22 Lines
; GCN-SAFE-DAG: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[FMA0]], [[C]] ; GCN-SAFE-DAG: v_mul_f32_e64 [[MUL1:v[0-9]+]], -[[FMA0]], [[C]]
; GCN-SAFE-DAG: v_mul_f32_e64 [[MUL2:v[0-9]+]], -[[FMA0]], [[D]] ; GCN-SAFE-DAG: v_mul_f32_e64 [[MUL2:v[0-9]+]], -[[FMA0]], [[D]]
; GCN-NSZ: v_fma_f32 [[FMA0:v[0-9]+]], [[A]], -[[B]], -2.0 ; GCN-NSZ: v_fma_f32 [[FMA0:v[0-9]+]], [[A]], -[[B]], -2.0
; GCN-NSZ-DAG: v_mul_f32_e32 [[MUL1:v[0-9]+]], [[FMA0]], [[C]] ; GCN-NSZ-DAG: v_mul_f32_e32 [[MUL1:v[0-9]+]], [[FMA0]], [[C]]
; GCN-NSZ-DAG: v_mul_f32_e32 [[MUL2:v[0-9]+]], [[FMA0]], [[D]] ; GCN-NSZ-DAG: v_mul_f32_e32 [[MUL2:v[0-9]+]], [[FMA0]], [[D]]
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL2]] ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MUL2]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @free_fold_src_code_size_cost_use_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr, float addrspace(1)* %d.ptr) #0 { define amdgpu_kernel void @free_fold_src_code_size_cost_use_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr, float addrspace(1)* %b.ptr, float addrspace(1)* %c.ptr, float addrspace(1)* %d.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
%c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext %c.gep = getelementptr inbounds float, float addrspace(1)* %c.ptr, i64 %tid.ext
%d.gep = getelementptr inbounds float, float addrspace(1)* %d.ptr, i64 %tid.ext %d.gep = getelementptr inbounds float, float addrspace(1)* %d.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
Show All 18 Lines
; GCN: {{buffer|flat}}_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]] ; GCN: {{buffer|flat}}_load_dwordx2 [[C:v\[[0-9]+:[0-9]+\]]]
; GCN: {{buffer|flat}}_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]] ; GCN: {{buffer|flat}}_load_dwordx2 [[D:v\[[0-9]+:[0-9]+\]]]
; GCN: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], 2.0 ; GCN: v_fma_f64 [[FMA0:v\[[0-9]+:[0-9]+\]]], [[A]], [[B]], 2.0
; GCN-DAG: v_mul_f64 [[MUL0:v\[[0-9]+:[0-9]+\]]], -[[FMA0]], [[C]] ; GCN-DAG: v_mul_f64 [[MUL0:v\[[0-9]+:[0-9]+\]]], -[[FMA0]], [[C]]
; GCN-DAG: v_mul_f64 [[MUL1:v\[[0-9]+:[0-9]+\]]], -[[FMA0]], [[D]] ; GCN-DAG: v_mul_f64 [[MUL1:v\[[0-9]+:[0-9]+\]]], -[[FMA0]], [[D]]
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[MUL0]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[MUL0]]
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]] ; GCN-NEXT: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[MUL1]]
; GCN-NEXT: s_waitcnt vmcnt(0)
define amdgpu_kernel void @free_fold_src_code_size_cost_use_f64(double addrspace(1)* %out, double addrspace(1)* %a.ptr, double addrspace(1)* %b.ptr, double addrspace(1)* %c.ptr, double addrspace(1)* %d.ptr) #0 { define amdgpu_kernel void @free_fold_src_code_size_cost_use_f64(double addrspace(1)* %out, double addrspace(1)* %a.ptr, double addrspace(1)* %b.ptr, double addrspace(1)* %c.ptr, double addrspace(1)* %d.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds double, double addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds double, double addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds double, double addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds double, double addrspace(1)* %b.ptr, i64 %tid.ext
%c.gep = getelementptr inbounds double, double addrspace(1)* %c.ptr, i64 %tid.ext %c.gep = getelementptr inbounds double, double addrspace(1)* %c.ptr, i64 %tid.ext
%d.gep = getelementptr inbounds double, double addrspace(1)* %d.ptr, i64 %tid.ext %d.gep = getelementptr inbounds double, double addrspace(1)* %d.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds double, double addrspace(1)* %out, i64 %tid.ext
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll

Show First 20 Lines • Show All 101 Lines • ▼ Show 20 Lines
; GFX9-FLATSCR: scratch_store_dword v0, v1, off{{$}} ; GFX9-FLATSCR: scratch_store_dword v0, v1, off{{$}}
define void @func_store_private_arg_i32_ptr(i32 addrspace(5)* %ptr) #0 { define void @func_store_private_arg_i32_ptr(i32 addrspace(5)* %ptr) #0 {
store volatile i32 15, i32 addrspace(5)* %ptr store volatile i32 15, i32 addrspace(5)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}func_load_private_arg_i32_ptr: ; GCN-LABEL: {{^}}func_load_private_arg_i32_ptr:
; GCN: s_waitcnt ; GCN: s_waitcnt
; MUBUF-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen{{$}} ; MUBUF-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen glc{{$}}
; GFX9-FLATSCR-NEXT: scratch_load_dword v0, v0, off{{$}} ; GFX9-FLATSCR-NEXT: scratch_load_dword v0, v0, off glc{{$}}
define void @func_load_private_arg_i32_ptr(i32 addrspace(5)* %ptr) #0 { define void @func_load_private_arg_i32_ptr(i32 addrspace(5)* %ptr) #0 {
%val = load volatile i32, i32 addrspace(5)* %ptr %val = load volatile i32, i32 addrspace(5)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr: ; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr:
; GCN: s_waitcnt ; GCN: s_waitcnt
Show All 37 Lines
; CI: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], s32, 6 ; CI: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], s32, 6
; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32 ; GFX9-MUBUF: v_lshrrev_b32_e64 [[SP:v[0-9]+]], 6, s32
; GFX9-FLATSCR: v_mov_b32_e32 [[SP:v[0-9]+]], s32 ; GFX9-FLATSCR: v_mov_b32_e32 [[SP:v[0-9]+]], s32
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; CI: v_add_i32_e32 [[GEP:v[0-9]+]], vcc, 4, [[SHIFT]] ; CI: v_add_i32_e32 [[GEP:v[0-9]+]], vcc, 4, [[SHIFT]]
; CI: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:4{{$}} ; CI: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:4 glc{{$}}
; GFX9: v_add_u32_e32 [[GEP:v[0-9]+]], 4, [[SP]] ; GFX9: v_add_u32_e32 [[GEP:v[0-9]+]], 4, [[SP]]
; GFX9-MUBUF: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:4{{$}} ; GFX9-MUBUF: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s32 offset:4 glc{{$}}
; GFX9-FLATSCR: scratch_load_dword v{{[0-9]+}}, off, s32 offset:4{{$}} ; GFX9-FLATSCR: scratch_load_dword v{{[0-9]+}}, off, s32 offset:4 glc{{$}}
; GCN: ds_write_b32 v{{[0-9]+}}, [[GEP]] ; GCN: ds_write_b32 v{{[0-9]+}}, [[GEP]]
define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, i32 %arg2) #0 { define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, i32 %arg2) #0 {
%cmp = icmp eq i32 %arg2, 0 %cmp = icmp eq i32 %arg2, 0
br i1 %cmp, label %bb, label %ret br i1 %cmp, label %bb, label %ret
bb: bb:
%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0 %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0
▲ Show 20 Lines • Show All 129 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/function-args.ll

Show First 20 Lines • Show All 531 Lines • ▼ Show 20 Lines
; GCN-DAG: buffer_store_byte v[[ELT0]] ; GCN-DAG: buffer_store_byte v[[ELT0]]
define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 { define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0) #0 {
%arg0.load = load { i8, i32 }, { i8, i32 } addrspace(5)* %arg0 %arg0.load = load { i8, i32 }, { i8, i32 } addrspace(5)* %arg0
store { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef store { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_x2: ; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_x2:
; GCN: buffer_load_ubyte v[[ELT0_0:[0-9]+]], off, s[0:3], s32{{$}} ; GCN: buffer_load_ubyte v[[ELT0_0:[0-9]+]], off, s[0:3], s32 glc{{$}}
; GCN: buffer_load_dword v[[ELT1_0:[0-9]+]], off, s[0:3], s32 offset:4{{$}} ; GCN: buffer_load_dword v[[ELT1_0:[0-9]+]], off, s[0:3], s32 offset:4 glc{{$}}
; GCN: buffer_load_ubyte v[[ELT0_1:[0-9]+]], off, s[0:3], s32 offset:8{{$}} ; GCN: buffer_load_ubyte v[[ELT0_1:[0-9]+]], off, s[0:3], s32 offset:8 glc{{$}}
; GCN: buffer_load_dword v[[ELT1_1:[0-9]+]], off, s[0:3], s32 offset:12{{$}} ; GCN: buffer_load_dword v[[ELT1_1:[0-9]+]], off, s[0:3], s32 offset:12 glc{{$}}
; GCN: ds_write_b32 v0, v0 ; GCN: ds_write_b32 v0, v0
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg1, i32 %arg2) #0 { define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg0, { i8, i32 } addrspace(5)* byval({ i8, i32 }) %arg1, i32 %arg2) #0 {
%arg0.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg0 %arg0.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg0
%arg1.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg1 %arg1.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg1
store volatile { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef store volatile { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef
store volatile { i8, i32 } %arg1.load, { i8, i32 } addrspace(1)* undef store volatile { i8, i32 } %arg1.load, { i8, i32 } addrspace(1)* undef
▲ Show 20 Lines • Show All 262 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 153 Lines • ▼ Show 20 Lines
define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 { define amdgpu_gfx void @test_call_external_void_func_i1_signext(i32) #0 {
; GFX9-LABEL: test_call_external_void_func_i1_signext: ; GFX9-LABEL: test_call_external_void_func_i1_signext:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s33, 2 ; GFX9-NEXT: v_writelane_b32 v40, s33, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s33, s32 ; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_add_u32 s32, s32, 0x400 ; GFX9-NEXT: s_add_u32 s32, s32, 0x400
; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i1_signext@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i1_signext@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i1_signext@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i1_signext@rel32@hi+12
; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: s_sub_u32 s32, s32, 0x400 ; GFX9-NEXT: s_sub_u32 s32, s32, 0x400
; GFX9-NEXT: v_readlane_b32 s33, v40, 2 ; GFX9-NEXT: v_readlane_b32 s33, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[6:7] ; GFX9-NEXT: s_mov_b64 exec, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[4:5] ; GFX9-NEXT: s_setpc_b64 s[4:5]
; ;
; GFX10-LABEL: test_call_external_void_func_i1_signext: ; GFX10-LABEL: test_call_external_void_func_i1_signext:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_or_saveexec_b32 s4, -1 ; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s4 ; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s33, 2 ; GFX10-NEXT: v_writelane_b32 v40, s33, 2
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_add_u32 s32, s32, 0x200 ; GFX10-NEXT: s_add_u32 s32, s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i1_signext@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i1_signext@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i1_signext@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i1_signext@rel32@hi+12
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: s_sub_u32 s32, s32, 0x200 ; GFX10-NEXT: s_sub_u32 s32, s32, 0x200
; GFX10-NEXT: v_readlane_b32 s33, v40, 2 ; GFX10-NEXT: v_readlane_b32 s33, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s6, -1 ; GFX10-NEXT: s_or_saveexec_b32 s6, -1
Show All 9 Lines
define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 { define amdgpu_gfx void @test_call_external_void_func_i1_zeroext(i32) #0 {
; GFX9-LABEL: test_call_external_void_func_i1_zeroext: ; GFX9-LABEL: test_call_external_void_func_i1_zeroext:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s33, 2 ; GFX9-NEXT: v_writelane_b32 v40, s33, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s33, s32 ; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_add_u32 s32, s32, 0x400 ; GFX9-NEXT: s_add_u32 s32, s32, 0x400
; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i1_zeroext@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i1_zeroext@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i1_zeroext@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i1_zeroext@rel32@hi+12
; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX9-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: s_sub_u32 s32, s32, 0x400 ; GFX9-NEXT: s_sub_u32 s32, s32, 0x400
; GFX9-NEXT: v_readlane_b32 s33, v40, 2 ; GFX9-NEXT: v_readlane_b32 s33, v40, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[6:7] ; GFX9-NEXT: s_mov_b64 exec, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[4:5] ; GFX9-NEXT: s_setpc_b64 s[4:5]
; ;
; GFX10-LABEL: test_call_external_void_func_i1_zeroext: ; GFX10-LABEL: test_call_external_void_func_i1_zeroext:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_or_saveexec_b32 s4, -1 ; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s4 ; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s33, 2 ; GFX10-NEXT: v_writelane_b32 v40, s33, 2
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_add_u32 s32, s32, 0x200 ; GFX10-NEXT: s_add_u32 s32, s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i1_zeroext@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i1_zeroext@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i1_zeroext@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i1_zeroext@rel32@hi+12
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32 ; GFX10-NEXT: buffer_store_byte v0, off, s[0:3], s32
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: s_sub_u32 s32, s32, 0x200 ; GFX10-NEXT: s_sub_u32 s32, s32, 0x200
; GFX10-NEXT: v_readlane_b32 s33, v40, 2 ; GFX10-NEXT: v_readlane_b32 s33, v40, 2
; GFX10-NEXT: s_or_saveexec_b32 s6, -1 ; GFX10-NEXT: s_or_saveexec_b32 s6, -1
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 { define amdgpu_gfx void @test_call_external_void_func_i8_signext(i32) #0 {
; GFX9-LABEL: test_call_external_void_func_i8_signext: ; GFX9-LABEL: test_call_external_void_func_i8_signext:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: global_load_sbyte v0, v[0:1], off ; GFX9-NEXT: global_load_sbyte v0, v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s33, 2 ; GFX9-NEXT: v_writelane_b32 v40, s33, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s33, s32 ; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_add_u32 s32, s32, 0x400 ; GFX9-NEXT: s_add_u32 s32, s32, 0x400
; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i8_signext@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i8_signext@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i8_signext@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i8_signext@rel32@hi+12
; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1
Show All 11 Lines
; GFX10-LABEL: test_call_external_void_func_i8_signext: ; GFX10-LABEL: test_call_external_void_func_i8_signext:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_or_saveexec_b32 s4, -1 ; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s4 ; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: global_load_sbyte v0, v[0:1], off ; GFX10-NEXT: global_load_sbyte v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s33, 2 ; GFX10-NEXT: v_writelane_b32 v40, s33, 2
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_add_u32 s32, s32, 0x200 ; GFX10-NEXT: s_add_u32 s32, s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i8_signext@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i8_signext@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i8_signext@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i8_signext@rel32@hi+12
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
Show All 15 Lines
define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 { define amdgpu_gfx void @test_call_external_void_func_i8_zeroext(i32) #0 {
; GFX9-LABEL: test_call_external_void_func_i8_zeroext: ; GFX9-LABEL: test_call_external_void_func_i8_zeroext:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: global_load_ubyte v0, v[0:1], off ; GFX9-NEXT: global_load_ubyte v0, v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s33, 2 ; GFX9-NEXT: v_writelane_b32 v40, s33, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s33, s32 ; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_add_u32 s32, s32, 0x400 ; GFX9-NEXT: s_add_u32 s32, s32, 0x400
; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i8_zeroext@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i8_zeroext@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i8_zeroext@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i8_zeroext@rel32@hi+12
; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1
Show All 11 Lines
; GFX10-LABEL: test_call_external_void_func_i8_zeroext: ; GFX10-LABEL: test_call_external_void_func_i8_zeroext:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_or_saveexec_b32 s4, -1 ; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s4 ; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: global_load_ubyte v0, v[0:1], off ; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s33, 2 ; GFX10-NEXT: v_writelane_b32 v40, s33, 2
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_add_u32 s32, s32, 0x200 ; GFX10-NEXT: s_add_u32 s32, s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i8_zeroext@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i8_zeroext@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i8_zeroext@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i8_zeroext@rel32@hi+12
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
▲ Show 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 { define amdgpu_gfx void @test_call_external_void_func_i16_signext(i32) #0 {
; GFX9-LABEL: test_call_external_void_func_i16_signext: ; GFX9-LABEL: test_call_external_void_func_i16_signext:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s33, 2 ; GFX9-NEXT: v_writelane_b32 v40, s33, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s33, s32 ; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_add_u32 s32, s32, 0x400 ; GFX9-NEXT: s_add_u32 s32, s32, 0x400
; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i16_signext@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i16_signext@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i16_signext@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i16_signext@rel32@hi+12
; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1
Show All 11 Lines
; GFX10-LABEL: test_call_external_void_func_i16_signext: ; GFX10-LABEL: test_call_external_void_func_i16_signext:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_or_saveexec_b32 s4, -1 ; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s4 ; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s33, 2 ; GFX10-NEXT: v_writelane_b32 v40, s33, 2
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_add_u32 s32, s32, 0x200 ; GFX10-NEXT: s_add_u32 s32, s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i16_signext@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i16_signext@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i16_signext@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i16_signext@rel32@hi+12
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
Show All 15 Lines
define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 { define amdgpu_gfx void @test_call_external_void_func_i16_zeroext(i32) #0 {
; GFX9-LABEL: test_call_external_void_func_i16_zeroext: ; GFX9-LABEL: test_call_external_void_func_i16_zeroext:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[4:5], -1
; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX9-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-NEXT: s_mov_b64 exec, s[4:5]
; GFX9-NEXT: global_load_ushort v0, v[0:1], off ; GFX9-NEXT: global_load_ushort v0, v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_writelane_b32 v40, s33, 2 ; GFX9-NEXT: v_writelane_b32 v40, s33, 2
; GFX9-NEXT: v_writelane_b32 v40, s30, 0 ; GFX9-NEXT: v_writelane_b32 v40, s30, 0
; GFX9-NEXT: s_mov_b32 s33, s32 ; GFX9-NEXT: s_mov_b32 s33, s32
; GFX9-NEXT: s_add_u32 s32, s32, 0x400 ; GFX9-NEXT: s_add_u32 s32, s32, 0x400
; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i16_zeroext@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s4, s4, external_void_func_i16_zeroext@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i16_zeroext@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s5, s5, external_void_func_i16_zeroext@rel32@hi+12
; GFX9-NEXT: v_writelane_b32 v40, s31, 1 ; GFX9-NEXT: v_writelane_b32 v40, s31, 1
Show All 11 Lines
; GFX10-LABEL: test_call_external_void_func_i16_zeroext: ; GFX10-LABEL: test_call_external_void_func_i16_zeroext:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_or_saveexec_b32 s4, -1 ; GFX10-NEXT: s_or_saveexec_b32 s4, -1
; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX10-NEXT: buffer_store_dword v40, off, s[0:3], s32 ; 4-byte Folded Spill
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s4 ; GFX10-NEXT: s_mov_b32 exec_lo, s4
; GFX10-NEXT: global_load_ushort v0, v[0:1], off ; GFX10-NEXT: global_load_ushort v0, v[0:1], off glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_writelane_b32 v40, s33, 2 ; GFX10-NEXT: v_writelane_b32 v40, s33, 2
; GFX10-NEXT: s_mov_b32 s33, s32 ; GFX10-NEXT: s_mov_b32 s33, s32
; GFX10-NEXT: s_add_u32 s32, s32, 0x200 ; GFX10-NEXT: s_add_u32 s32, s32, 0x200
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i16_zeroext@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, external_void_func_i16_zeroext@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i16_zeroext@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s5, s5, external_void_func_i16_zeroext@rel32@hi+12
; GFX10-NEXT: v_writelane_b32 v40, s30, 0 ; GFX10-NEXT: v_writelane_b32 v40, s30, 0
; GFX10-NEXT: v_writelane_b32 v40, s31, 1 ; GFX10-NEXT: v_writelane_b32 v40, s31, 1
▲ Show 20 Lines • Show All 2,243 Lines • ▼ Show 20 Lines
; GFX9-NEXT: v_mov_b32_e32 v0, 42 ; GFX9-NEXT: v_mov_b32_e32 v0, 42
; GFX9-NEXT: s_getpc_b64 s[4:5] ; GFX9-NEXT: s_getpc_b64 s[4:5]
; GFX9-NEXT: s_add_u32 s4, s4, external_i32_func_i32@rel32@lo+4 ; GFX9-NEXT: s_add_u32 s4, s4, external_i32_func_i32@rel32@lo+4
; GFX9-NEXT: s_addc_u32 s5, s5, external_i32_func_i32@rel32@hi+12 ; GFX9-NEXT: s_addc_u32 s5, s5, external_i32_func_i32@rel32@hi+12
; GFX9-NEXT: v_writelane_b32 v42, s31, 1 ; GFX9-NEXT: v_writelane_b32 v42, s31, 1
; GFX9-NEXT: v_mov_b32_e32 v41, v1 ; GFX9-NEXT: v_mov_b32_e32 v41, v1
; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX9-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX9-NEXT: global_store_dword v[40:41], v0, off ; GFX9-NEXT: global_store_dword v[40:41], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; 4-byte Folded Reload
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; 4-byte Folded Reload
; GFX9-NEXT: v_readlane_b32 s4, v42, 0 ; GFX9-NEXT: v_readlane_b32 s4, v42, 0
; GFX9-NEXT: v_readlane_b32 s5, v42, 1 ; GFX9-NEXT: v_readlane_b32 s5, v42, 1
; GFX9-NEXT: s_sub_u32 s32, s32, 0x400 ; GFX9-NEXT: s_sub_u32 s32, s32, 0x400
; GFX9-NEXT: v_readlane_b32 s33, v42, 2 ; GFX9-NEXT: v_readlane_b32 s33, v42, 2
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
Show All 19 Lines
; GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-NEXT: v_mov_b32_e32 v0, 42
; GFX10-NEXT: s_getpc_b64 s[4:5] ; GFX10-NEXT: s_getpc_b64 s[4:5]
; GFX10-NEXT: s_add_u32 s4, s4, external_i32_func_i32@rel32@lo+4 ; GFX10-NEXT: s_add_u32 s4, s4, external_i32_func_i32@rel32@lo+4
; GFX10-NEXT: s_addc_u32 s5, s5, external_i32_func_i32@rel32@hi+12 ; GFX10-NEXT: s_addc_u32 s5, s5, external_i32_func_i32@rel32@hi+12
; GFX10-NEXT: v_mov_b32_e32 v41, v1 ; GFX10-NEXT: v_mov_b32_e32 v41, v1
; GFX10-NEXT: v_writelane_b32 v42, s31, 1 ; GFX10-NEXT: v_writelane_b32 v42, s31, 1
; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GFX10-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GFX10-NEXT: global_store_dword v[40:41], v0, off ; GFX10-NEXT: global_store_dword v[40:41], v0, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33 ; GFX10-NEXT: buffer_load_dword v41, off, s[0:3], s33
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4 ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s33 offset:4
; GFX10-NEXT: v_readlane_b32 s4, v42, 0 ; GFX10-NEXT: v_readlane_b32 s4, v42, 0
; GFX10-NEXT: v_readlane_b32 s5, v42, 1 ; GFX10-NEXT: v_readlane_b32 s5, v42, 1
; GFX10-NEXT: s_sub_u32 s32, s32, 0x200 ; GFX10-NEXT: s_sub_u32 s32, s32, 0x200
; GFX10-NEXT: v_readlane_b32 s33, v42, 2 ; GFX10-NEXT: v_readlane_b32 s33, v42, 2
; GFX10-NEXT: s_or_saveexec_b32 s6, -1 ; GFX10-NEXT: s_or_saveexec_b32 s6, -1
; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; GFX10-NEXT: buffer_load_dword v42, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s6 ; GFX10-NEXT: s_mov_b32 exec_lo, s6
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[4:5] ; GFX10-NEXT: s_setpc_b64 s[4:5]
%val = call amdgpu_gfx i32 @external_i32_func_i32(i32 42) %val = call amdgpu_gfx i32 @external_i32_func_i32(i32 42)
store volatile i32 %val, i32 addrspace(1)* %out store volatile i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 { define amdgpu_gfx void @test_call_external_void_func_struct_i8_i32() #0 {
; GFX9-LABEL: test_call_external_void_func_struct_i8_i32: ; GFX9-LABEL: test_call_external_void_func_struct_i8_i32:
▲ Show 20 Lines • Show All 164 Lines • ▼ Show 20 Lines
; GFX9-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8 ; GFX9-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8
; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:12 ; GFX9-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:12
; GFX9-NEXT: v_readlane_b32 s4, v40, 0 ; GFX9-NEXT: v_readlane_b32 s4, v40, 0
; GFX9-NEXT: v_readlane_b32 s5, v40, 1 ; GFX9-NEXT: v_readlane_b32 s5, v40, 1
; GFX9-NEXT: s_sub_u32 s32, s32, 0x800 ; GFX9-NEXT: s_sub_u32 s32, s32, 0x800
; GFX9-NEXT: v_readlane_b32 s33, v40, 2 ; GFX9-NEXT: v_readlane_b32 s33, v40, 2
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: global_store_byte v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v1, off ; GFX9-NEXT: global_store_dword v[0:1], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1 ; GFX9-NEXT: s_or_saveexec_b64 s[6:7], -1
; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload ; GFX9-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX9-NEXT: s_mov_b64 exec, s[6:7] ; GFX9-NEXT: s_mov_b64 exec, s[6:7]
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[4:5] ; GFX9-NEXT: s_setpc_b64 s[4:5]
; ;
; GFX10-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32: ; GFX10-LABEL: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
Show All 23 Lines
; GFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8 ; GFX10-NEXT: buffer_load_ubyte v0, off, s[0:3], s33 offset:8
; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:12 ; GFX10-NEXT: buffer_load_dword v1, off, s[0:3], s33 offset:12
; GFX10-NEXT: v_readlane_b32 s4, v40, 0 ; GFX10-NEXT: v_readlane_b32 s4, v40, 0
; GFX10-NEXT: v_readlane_b32 s5, v40, 1 ; GFX10-NEXT: v_readlane_b32 s5, v40, 1
; GFX10-NEXT: s_sub_u32 s32, s32, 0x400 ; GFX10-NEXT: s_sub_u32 s32, s32, 0x400
; GFX10-NEXT: v_readlane_b32 s33, v40, 2 ; GFX10-NEXT: v_readlane_b32 s33, v40, 2
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_byte v[0:1], v0, off ; GFX10-NEXT: global_store_byte v[0:1], v0, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_or_saveexec_b32 s6, -1 ; GFX10-NEXT: s_or_saveexec_b32 s6, -1
; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload ; GFX10-NEXT: buffer_load_dword v40, off, s[0:3], s32 offset:16 ; 4-byte Folded Reload
; GFX10-NEXT: s_waitcnt_depctr 0xffe3 ; GFX10-NEXT: s_waitcnt_depctr 0xffe3
; GFX10-NEXT: s_mov_b32 exec_lo, s6 ; GFX10-NEXT: s_mov_b32 exec_lo, s6
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_setpc_b64 s[4:5] ; GFX10-NEXT: s_setpc_b64 s[4:5]
%in.val = alloca { i8, i32 }, align 4, addrspace(5) %in.val = alloca { i8, i32 }, align 4, addrspace(5)
%out.val = alloca { i8, i32 }, align 4, addrspace(5) %out.val = alloca { i8, i32 }, align 4, addrspace(5)
%in.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 0 %in.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 0
%in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 1 %in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 1
store i8 3, i8 addrspace(5)* %in.gep0 store i8 3, i8 addrspace(5)* %in.gep0
store i32 8, i32 addrspace(5)* %in.gep1 store i32 8, i32 addrspace(5)* %in.gep1
call amdgpu_gfx void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* %in.val) call amdgpu_gfx void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* %in.val)
▲ Show 20 Lines • Show All 3,304 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll

Show All 13 Lines
; GFX9-NEXT: s_mov_b32 s7, s5 ; GFX9-NEXT: s_mov_b32 s7, s5
; GFX9-NEXT: s_mov_b32 s6, s4 ; GFX9-NEXT: s_mov_b32 s6, s4
; GFX9-NEXT: s_mov_b32 s5, s3 ; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: s_mov_b32 s4, s2 ; GFX9-NEXT: s_mov_b32 s4, s2
; GFX9-NEXT: v_mov_b32_e32 v2, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, v1
; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16 ; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_short v[0:1], v1, off ; GFX9-NEXT: global_store_short v[0:1], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_1d_f16_tfe_dmask0: ; GFX10-LABEL: load_1d_f16_tfe_dmask0:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s11, s9 ; GFX10-NEXT: s_mov_b32 s11, s9
; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_short v[0:1], v1, off ; GFX10-NEXT: global_store_short v[0:1], v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask0: ; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask0:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9 ; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8 ; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7 ; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6 ; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5 ; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4 ; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3 ; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2 ; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16 ; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_short v[0:1], v1 ; GFX8-UNPACKED-NEXT: flat_store_short v[0:1], v1
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: s_endpgm ; GFX8-UNPACKED-NEXT: s_endpgm
%v = call { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) %v = call { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.data = extractvalue { half, i32 } %v, 0 %v.data = extractvalue { half, i32 } %v, 0
%v.err = extractvalue { half, i32 } %v, 1 %v.err = extractvalue { half, i32 } %v, 1
store volatile half %v.data, half addrspace(1)* undef store volatile half %v.data, half addrspace(1)* undef
store volatile i32 %v.err, i32 addrspace(1)* undef store volatile i32 %v.err, i32 addrspace(1)* undef
ret void ret void
} }
Show All 9 Lines
; GFX9-NEXT: s_mov_b32 s7, s5 ; GFX9-NEXT: s_mov_b32 s7, s5
; GFX9-NEXT: s_mov_b32 s6, s4 ; GFX9-NEXT: s_mov_b32 s6, s4
; GFX9-NEXT: s_mov_b32 s5, s3 ; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: s_mov_b32 s4, s2 ; GFX9-NEXT: s_mov_b32 s4, s2
; GFX9-NEXT: v_mov_b32_e32 v2, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, v1
; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16 ; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_short v[0:1], v1, off ; GFX9-NEXT: global_store_short v[0:1], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_1d_f16_tfe_dmask1: ; GFX10-LABEL: load_1d_f16_tfe_dmask1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s11, s9 ; GFX10-NEXT: s_mov_b32 s11, s9
; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_short v[0:1], v1, off ; GFX10-NEXT: global_store_short v[0:1], v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask1: ; GFX8-UNPACKED-LABEL: load_1d_f16_tfe_dmask1:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9 ; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8 ; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7 ; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6 ; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5 ; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4 ; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3 ; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2 ; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16 ; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_short v[0:1], v1 ; GFX8-UNPACKED-NEXT: flat_store_short v[0:1], v1
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: s_endpgm ; GFX8-UNPACKED-NEXT: s_endpgm
%v = call { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) %v = call { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.data = extractvalue { half, i32 } %v, 0 %v.data = extractvalue { half, i32 } %v, 0
%v.err = extractvalue { half, i32 } %v, 1 %v.err = extractvalue { half, i32 } %v, 1
store volatile half %v.data, half addrspace(1)* undef store volatile half %v.data, half addrspace(1)* undef
store volatile i32 %v.err, i32 addrspace(1)* undef store volatile i32 %v.err, i32 addrspace(1)* undef
ret void ret void
} }
Show All 9 Lines
; GFX9-NEXT: s_mov_b32 s7, s5 ; GFX9-NEXT: s_mov_b32 s7, s5
; GFX9-NEXT: s_mov_b32 s6, s4 ; GFX9-NEXT: s_mov_b32 s6, s4
; GFX9-NEXT: s_mov_b32 s5, s3 ; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: s_mov_b32 s4, s2 ; GFX9-NEXT: s_mov_b32 s4, s2
; GFX9-NEXT: v_mov_b32_e32 v2, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, v1
; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16 ; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v1, off ; GFX9-NEXT: global_store_dword v[0:1], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_1d_v2f16_tfe_dmask0: ; GFX10-LABEL: load_1d_v2f16_tfe_dmask0:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s11, s9 ; GFX10-NEXT: s_mov_b32 s11, s9
; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask0: ; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask0:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9 ; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8 ; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7 ; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6 ; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5 ; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4 ; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3 ; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2 ; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16 ; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v1 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v1
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: s_endpgm ; GFX8-UNPACKED-NEXT: s_endpgm
%v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.data = extractvalue { <2 x half>, i32 } %v, 0 %v.data = extractvalue { <2 x half>, i32 } %v, 0
%v.err = extractvalue { <2 x half>, i32 } %v, 1 %v.err = extractvalue { <2 x half>, i32 } %v, 1
store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef
store volatile i32 %v.err, i32 addrspace(1)* undef store volatile i32 %v.err, i32 addrspace(1)* undef
ret void ret void
} }
Show All 9 Lines
; GFX9-NEXT: s_mov_b32 s7, s5 ; GFX9-NEXT: s_mov_b32 s7, s5
; GFX9-NEXT: s_mov_b32 s6, s4 ; GFX9-NEXT: s_mov_b32 s6, s4
; GFX9-NEXT: s_mov_b32 s5, s3 ; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: s_mov_b32 s4, s2 ; GFX9-NEXT: s_mov_b32 s4, s2
; GFX9-NEXT: v_mov_b32_e32 v2, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, v1
; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16 ; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v1, off ; GFX9-NEXT: global_store_dword v[0:1], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_1d_v2f16_tfe_dmask1: ; GFX10-LABEL: load_1d_v2f16_tfe_dmask1:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s11, s9 ; GFX10-NEXT: s_mov_b32 s11, s9
; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask1: ; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask1:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9 ; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8 ; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7 ; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6 ; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5 ; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4 ; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3 ; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2 ; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16 ; GFX8-UNPACKED-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 unorm tfe d16
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v1 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v1
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v2
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: s_endpgm ; GFX8-UNPACKED-NEXT: s_endpgm
%v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.data = extractvalue { <2 x half>, i32 } %v, 0 %v.data = extractvalue { <2 x half>, i32 } %v, 0
%v.err = extractvalue { <2 x half>, i32 } %v, 1 %v.err = extractvalue { <2 x half>, i32 } %v, 1
store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef
store volatile i32 %v.err, i32 addrspace(1)* undef store volatile i32 %v.err, i32 addrspace(1)* undef
ret void ret void
} }
Show All 9 Lines
; GFX9-NEXT: s_mov_b32 s7, s5 ; GFX9-NEXT: s_mov_b32 s7, s5
; GFX9-NEXT: s_mov_b32 s6, s4 ; GFX9-NEXT: s_mov_b32 s6, s4
; GFX9-NEXT: s_mov_b32 s5, s3 ; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: s_mov_b32 s4, s2 ; GFX9-NEXT: s_mov_b32 s4, s2
; GFX9-NEXT: v_mov_b32_e32 v2, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, v1
; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 unorm tfe d16 ; GFX9-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 unorm tfe d16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v1, off ; GFX9-NEXT: global_store_dword v[0:1], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v2, off ; GFX9-NEXT: global_store_dword v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_1d_v2f16_tfe_dmask3: ; GFX10-LABEL: load_1d_v2f16_tfe_dmask3:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s11, s9 ; GFX10-NEXT: s_mov_b32 s11, s9
; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v[0:1], v2, off ; GFX10-NEXT: global_store_dword v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask3: ; GFX8-UNPACKED-LABEL: load_1d_v2f16_tfe_dmask3:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9 ; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8 ; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7 ; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6 ; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5 ; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4 ; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3 ; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2 ; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v3, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v3, v1
; GFX8-UNPACKED-NEXT: image_load v[1:3], v0, s[4:11] dmask:0x3 unorm tfe d16 ; GFX8-UNPACKED-NEXT: image_load v[1:3], v0, s[4:11] dmask:0x3 unorm tfe d16
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v0 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v0
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v3 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v3
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: s_endpgm ; GFX8-UNPACKED-NEXT: s_endpgm
%v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 3, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 3, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.data = extractvalue { <2 x half>, i32 } %v, 0 %v.data = extractvalue { <2 x half>, i32 } %v, 0
%v.err = extractvalue { <2 x half>, i32 } %v, 1 %v.err = extractvalue { <2 x half>, i32 } %v, 1
store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef store volatile <2 x half> %v.data, <2 x half> addrspace(1)* undef
store volatile i32 %v.err, i32 addrspace(1)* undef store volatile i32 %v.err, i32 addrspace(1)* undef
ret void ret void
} }
Show All 10 Lines
; GFX9-NEXT: s_mov_b32 s6, s4 ; GFX9-NEXT: s_mov_b32 s6, s4
; GFX9-NEXT: s_mov_b32 s5, s3 ; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: s_mov_b32 s4, s2 ; GFX9-NEXT: s_mov_b32 s4, s2
; GFX9-NEXT: v_mov_b32_e32 v2, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, v1
; GFX9-NEXT: v_mov_b32_e32 v3, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: image_load v[1:3], v0, s[4:11] dmask:0x7 unorm tfe d16 ; GFX9-NEXT: image_load v[1:3], v0, s[4:11] dmask:0x7 unorm tfe d16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_short v[0:1], v2, off ; GFX9-NEXT: global_store_short v[0:1], v2, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v1, off ; GFX9-NEXT: global_store_dword v[0:1], v1, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v3, off ; GFX9-NEXT: global_store_dword v[0:1], v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_1d_v3f16_tfe_dmask7: ; GFX10-LABEL: load_1d_v3f16_tfe_dmask7:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s11, s9 ; GFX10-NEXT: s_mov_b32 s11, s9
; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: v_mov_b32_e32 v3, v1 ; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: image_load v[1:3], v0, s[4:11] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:3], v0, s[4:11] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_short v[0:1], v2, off ; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v[0:1], v1, off ; GFX10-NEXT: global_store_dword v[0:1], v1, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v[0:1], v3, off ; GFX10-NEXT: global_store_dword v[0:1], v3, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_v3f16_tfe_dmask7: ; GFX8-UNPACKED-LABEL: load_1d_v3f16_tfe_dmask7:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9 ; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8 ; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7 ; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6 ; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5 ; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4 ; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3 ; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2 ; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v3, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v3, v1
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v4, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v4, v1
; GFX8-UNPACKED-NEXT: image_load v[1:4], v0, s[4:11] dmask:0x7 unorm tfe d16 ; GFX8-UNPACKED-NEXT: image_load v[1:4], v0, s[4:11] dmask:0x7 unorm tfe d16
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v0, 16, v2 ; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v0, 16, v2
; GFX8-UNPACKED-NEXT: flat_store_short v[0:1], v3 ; GFX8-UNPACKED-NEXT: flat_store_short v[0:1], v3
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v0 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v0
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v4 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v4
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: s_endpgm ; GFX8-UNPACKED-NEXT: s_endpgm
%v = call { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.data = extractvalue { <3 x half>, i32 } %v, 0 %v.data = extractvalue { <3 x half>, i32 } %v, 0
%v.err = extractvalue { <3 x half>, i32 } %v, 1 %v.err = extractvalue { <3 x half>, i32 } %v, 1
store volatile <3 x half> %v.data, <3 x half> addrspace(1)* undef store volatile <3 x half> %v.data, <3 x half> addrspace(1)* undef
store volatile i32 %v.err, i32 addrspace(1)* undef store volatile i32 %v.err, i32 addrspace(1)* undef
ret void ret void
} }
Show All 10 Lines
; GFX9-NEXT: s_mov_b32 s6, s4 ; GFX9-NEXT: s_mov_b32 s6, s4
; GFX9-NEXT: s_mov_b32 s5, s3 ; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: s_mov_b32 s4, s2 ; GFX9-NEXT: s_mov_b32 s4, s2
; GFX9-NEXT: v_mov_b32_e32 v2, v1 ; GFX9-NEXT: v_mov_b32_e32 v2, v1
; GFX9-NEXT: v_mov_b32_e32 v3, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf unorm tfe d16 ; GFX9-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf unorm tfe d16
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dwordx2 v[0:1], v[1:2], off ; GFX9-NEXT: global_store_dwordx2 v[0:1], v[1:2], off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v[0:1], v3, off ; GFX9-NEXT: global_store_dword v[0:1], v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: load_1d_v4f16_tfe_dmask15: ; GFX10-LABEL: load_1d_v4f16_tfe_dmask15:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_mov_b32_e32 v1, 0 ; GFX10-NEXT: v_mov_b32_e32 v1, 0
; GFX10-NEXT: s_mov_b32 s11, s9 ; GFX10-NEXT: s_mov_b32 s11, s9
; GFX10-NEXT: s_mov_b32 s10, s8 ; GFX10-NEXT: s_mov_b32 s10, s8
; GFX10-NEXT: s_mov_b32 s9, s7 ; GFX10-NEXT: s_mov_b32 s9, s7
; GFX10-NEXT: s_mov_b32 s8, s6 ; GFX10-NEXT: s_mov_b32 s8, s6
; GFX10-NEXT: s_mov_b32 s7, s5 ; GFX10-NEXT: s_mov_b32 s7, s5
; GFX10-NEXT: s_mov_b32 s6, s4 ; GFX10-NEXT: s_mov_b32 s6, s4
; GFX10-NEXT: s_mov_b32 s5, s3 ; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_mov_b32 s4, s2 ; GFX10-NEXT: s_mov_b32 s4, s2
; GFX10-NEXT: v_mov_b32_e32 v2, v1 ; GFX10-NEXT: v_mov_b32_e32 v2, v1
; GFX10-NEXT: v_mov_b32_e32 v3, v1 ; GFX10-NEXT: v_mov_b32_e32 v3, v1
; GFX10-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX10-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_store_dwordx2 v[0:1], v[1:2], off ; GFX10-NEXT: global_store_dwordx2 v[0:1], v[1:2], off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v[0:1], v3, off ; GFX10-NEXT: global_store_dword v[0:1], v3, off
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
; ;
; GFX8-UNPACKED-LABEL: load_1d_v4f16_tfe_dmask15: ; GFX8-UNPACKED-LABEL: load_1d_v4f16_tfe_dmask15:
; GFX8-UNPACKED: ; %bb.0: ; GFX8-UNPACKED: ; %bb.0:
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v1, 0
; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9 ; GFX8-UNPACKED-NEXT: s_mov_b32 s11, s9
; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8 ; GFX8-UNPACKED-NEXT: s_mov_b32 s10, s8
; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7 ; GFX8-UNPACKED-NEXT: s_mov_b32 s9, s7
; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6 ; GFX8-UNPACKED-NEXT: s_mov_b32 s8, s6
; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5 ; GFX8-UNPACKED-NEXT: s_mov_b32 s7, s5
; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4 ; GFX8-UNPACKED-NEXT: s_mov_b32 s6, s4
; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3 ; GFX8-UNPACKED-NEXT: s_mov_b32 s5, s3
; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2 ; GFX8-UNPACKED-NEXT: s_mov_b32 s4, s2
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v2, v1
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v3, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v3, v1
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v4, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v4, v1
; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v5, v1 ; GFX8-UNPACKED-NEXT: v_mov_b32_e32 v5, v1
; GFX8-UNPACKED-NEXT: image_load v[1:5], v0, s[4:11] dmask:0xf unorm tfe d16 ; GFX8-UNPACKED-NEXT: image_load v[1:5], v0, s[4:11] dmask:0xf unorm tfe d16
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0) ; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v0, 16, v4 ; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v0, 16, v4
; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v4, 16, v2 ; GFX8-UNPACKED-NEXT: v_lshlrev_b32_e32 v4, 16, v2
; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v2, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v2, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX8-UNPACKED-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX8-UNPACKED-NEXT: flat_store_dwordx2 v[0:1], v[1:2] ; GFX8-UNPACKED-NEXT: flat_store_dwordx2 v[0:1], v[1:2]
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v5 ; GFX8-UNPACKED-NEXT: flat_store_dword v[0:1], v5
; GFX8-UNPACKED-NEXT: s_waitcnt vmcnt(0)
; GFX8-UNPACKED-NEXT: s_endpgm ; GFX8-UNPACKED-NEXT: s_endpgm
%v = call { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) %v = call { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 15, i32 %s, <8 x i32> %rsrc, i32 1, i32 0)
%v.data = extractvalue { <4 x half>, i32 } %v, 0 %v.data = extractvalue { <4 x half>, i32 } %v, 0
%v.err = extractvalue { <4 x half>, i32 } %v, 1 %v.err = extractvalue { <4 x half>, i32 } %v, 1
store volatile <4 x half> %v.data, <4 x half> addrspace(1)* undef store volatile <4 x half> %v.data, <4 x half> addrspace(1)* undef
store volatile i32 %v.err, i32 addrspace(1)* undef store volatile i32 %v.err, i32 addrspace(1)* undef
ret void ret void
} }
declare { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
declare { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0 declare { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 immarg, i32, <8 x i32>, i32 immarg, i32 immarg) #0
attributes #0 = { nounwind readonly } attributes #0 = { nounwind readonly }

llvm/test/CodeGen/AMDGPU/imm16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX10 %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1010 -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX10 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=tonga -mattr=-flat-for-global -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
; FIXME: Merge into imm.ll ; FIXME: Merge into imm.ll
define amdgpu_kernel void @store_inline_imm_neg_0.0_i16(i16 addrspace(1)* %out) { define amdgpu_kernel void @store_inline_imm_neg_0.0_i16(i16 addrspace(1)* %out) {
; GFX10-LABEL: store_inline_imm_neg_0.0_i16: ; GFX10-LABEL: store_inline_imm_neg_0.0_i16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa] ; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x04,0xf4,0x00,0x00,0x00,0xfa]
; GFX10-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] ; GFX10-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff]
; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31] ; GFX10-NEXT: s_mov_b32 s3, 0x31016000 ; encoding: [0xff,0x03,0x83,0xbe,0x00,0x60,0x01,0x31]
; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe] ; GFX10-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x03,0x82,0xbe]
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf] ; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0xc0,0x8c,0xbf]
; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; GFX10-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; encoding: [0x00,0x00,0xfd,0xbb]
; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; GFX10-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
; ;
; VI-LABEL: store_inline_imm_neg_0.0_i16: ; VI-LABEL: store_inline_imm_neg_0.0_i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00] ; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 ; encoding: [0x02,0x00,0x06,0xc0,0x00,0x00,0x00,0x00]
; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11] ; VI-NEXT: s_mov_b32 s3, 0x1100f000 ; encoding: [0xff,0x00,0x83,0xbe,0x00,0xf0,0x00,0x11]
; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe] ; VI-NEXT: s_mov_b32 s2, -1 ; encoding: [0xc1,0x00,0x82,0xbe]
; VI-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff] ; VI-NEXT: v_mov_b32_e32 v0, 0xffff8000 ; encoding: [0xff,0x02,0x00,0x7e,0x00,0x80,0xff,0xff]
; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf] ; VI-NEXT: s_waitcnt lgkmcnt(0) ; encoding: [0x7f,0x00,0x8c,0xbf]
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80] ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; encoding: [0x00,0x00,0x68,0xe0,0x00,0x00,0x00,0x80]
; VI-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x0f,0x8c,0xbf]
; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf] ; VI-NEXT: s_endpgm ; encoding: [0x00,0x00,0x81,0xbf]
; ;
; SI-LABEL: store_inline_imm_neg_0.0_i16: ; SI-LABEL: store_inline_imm_neg_0.0_i16:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 0x8000 ; SI-NEXT: v_mov_b32_e32 v0, 0x8000
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
store volatile i16 -32768, i16 addrspace(1)* %out store volatile i16 -32768, i16 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @store_inline_imm_0.0_f16(half addrspace(1)* %out) { define amdgpu_kernel void @store_inline_imm_0.0_f16(half addrspace(1)* %out) {
; GFX10-LABEL: store_inline_imm_0.0_f16: ; GFX10-LABEL: store_inline_imm_0.0_f16:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
▲ Show 20 Lines • Show All 1,638 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/infinite-loop.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s ; RUN: llc -march=amdgcn -verify-machineinstrs -simplifycfg-require-and-preserve-domtree=1 < %s | FileCheck -check-prefix=SI %s
; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s ; RUN: opt -mtriple=amdgcn-- -S -amdgpu-unify-divergent-exit-nodes -verify -simplifycfg-require-and-preserve-domtree=1 %s | FileCheck -check-prefix=IR %s
define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) { define amdgpu_kernel void @infinite_loop(i32 addrspace(1)* %out) {
; SI-LABEL: infinite_loop: ; SI-LABEL: infinite_loop:
; SI: ; %bb.0: ; %entry ; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
; SI-NEXT: BB0_1: ; %loop ; SI-NEXT: BB0_1: ; %loop
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB0_1 ; SI-NEXT: s_branch BB0_1
; IR-LABEL: @infinite_loop( ; IR-LABEL: @infinite_loop(
; IR-NEXT: entry: ; IR-NEXT: entry:
; IR-NEXT: br label [[LOOP:%.*]] ; IR-NEXT: br label [[LOOP:%.*]]
; IR: loop: ; IR: loop:
; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4 ; IR-NEXT: store volatile i32 999, i32 addrspace(1)* [[OUT:%.*]], align 4
; IR-NEXT: br label [[LOOP]] ; IR-NEXT: br label [[LOOP]]
entry: entry:
Show All 15 Lines
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
; SI-NEXT: s_and_b64 vcc, exec, -1 ; SI-NEXT: s_and_b64 vcc, exec, -1
; SI-NEXT: BB1_2: ; %loop ; SI-NEXT: BB1_2: ; %loop
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccnz BB1_2 ; SI-NEXT: s_cbranch_vccnz BB1_2
; SI-NEXT: BB1_3: ; %UnifiedReturnBlock ; SI-NEXT: BB1_3: ; %UnifiedReturnBlock
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; IR-LABEL: @infinite_loop_ret( ; IR-LABEL: @infinite_loop_ret(
; IR-NEXT: entry: ; IR-NEXT: entry:
; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() ; IR-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()
; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1 ; IR-NEXT: [[COND:%.*]] = icmp eq i32 [[TMP]], 1
Show All 26 Lines
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, 0x378 ; SI-NEXT: v_mov_b32_e32 v0, 0x378
; SI-NEXT: s_and_b64 vcc, exec, -1 ; SI-NEXT: s_and_b64 vcc, exec, -1
; SI-NEXT: BB2_2: ; %loop2 ; SI-NEXT: BB2_2: ; %loop2
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccnz BB2_2 ; SI-NEXT: s_cbranch_vccnz BB2_2
; SI-NEXT: ; %bb.3: ; %Flow ; SI-NEXT: ; %bb.3: ; %Flow
; SI-NEXT: s_mov_b64 s[2:3], 0 ; SI-NEXT: s_mov_b64 s[2:3], 0
; SI-NEXT: BB2_4: ; %Flow2 ; SI-NEXT: BB2_4: ; %Flow2
; SI-NEXT: s_and_b64 vcc, exec, s[2:3] ; SI-NEXT: s_and_b64 vcc, exec, s[2:3]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccz BB2_7 ; SI-NEXT: s_cbranch_vccz BB2_7
; SI-NEXT: ; %bb.5: ; SI-NEXT: ; %bb.5:
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
; SI-NEXT: s_and_b64 vcc, exec, 0 ; SI-NEXT: s_and_b64 vcc, exec, 0
; SI-NEXT: BB2_6: ; %loop1 ; SI-NEXT: BB2_6: ; %loop1
; SI-NEXT: ; =>This Inner Loop Header: Depth=1 ; SI-NEXT: ; =>This Inner Loop Header: Depth=1
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 vcc, vcc ; SI-NEXT: s_mov_b64 vcc, vcc
; SI-NEXT: s_cbranch_vccz BB2_6 ; SI-NEXT: s_cbranch_vccz BB2_6
; SI-NEXT: BB2_7: ; %DummyReturnBlock ; SI-NEXT: BB2_7: ; %DummyReturnBlock
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; IR-LABEL: @infinite_loops( ; IR-LABEL: @infinite_loops(
; IR-NEXT: entry: ; IR-NEXT: entry:
; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]] ; IR-NEXT: br i1 undef, label [[LOOP1:%.*]], label [[LOOP2:%.*]]
; IR: loop1: ; IR: loop1:
Show All 35 Lines
; SI-NEXT: ; Parent Loop BB3_2 Depth=1 ; SI-NEXT: ; Parent Loop BB3_2 Depth=1
; SI-NEXT: ; => This Inner Loop Header: Depth=2 ; SI-NEXT: ; => This Inner Loop Header: Depth=2
; SI-NEXT: s_and_b64 s[8:9], exec, s[0:1] ; SI-NEXT: s_and_b64 s[8:9], exec, s[0:1]
; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3] ; SI-NEXT: s_or_b64 s[2:3], s[8:9], s[2:3]
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, 0x3e7 ; SI-NEXT: v_mov_b32_e32 v0, 0x3e7
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_andn2_b64 exec, exec, s[2:3] ; SI-NEXT: s_andn2_b64 exec, exec, s[2:3]
; SI-NEXT: s_cbranch_execnz BB3_3 ; SI-NEXT: s_cbranch_execnz BB3_3
; SI-NEXT: ; %bb.4: ; %loop.exit.guard ; SI-NEXT: ; %bb.4: ; %loop.exit.guard
; SI-NEXT: ; in Loop: Header=BB3_2 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_2 Depth=1
; SI-NEXT: s_or_b64 exec, exec, s[2:3] ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
; SI-NEXT: s_mov_b64 vcc, 0 ; SI-NEXT: s_mov_b64 vcc, 0
; SI-NEXT: s_branch BB3_2 ; SI-NEXT: s_branch BB3_2
; SI-NEXT: BB3_5: ; %UnifiedReturnBlock ; SI-NEXT: BB3_5: ; %UnifiedReturnBlock
Show All 36 Lines

llvm/test/CodeGen/AMDGPU/inline-asm.ll

Show First 20 Lines • Show All 239 Lines • ▼ Show 20 Linesentry:
%cc = call i1 asm sideeffect "; use $1, def $0 ", "={v1}, {v0}"(i1 %val) %cc = call i1 asm sideeffect "; use $1, def $0 ", "={v1}, {v0}"(i1 %val)
store i1 %cc, i1 addrspace(1)* undef store i1 %cc, i1 addrspace(1)* undef
ret void ret void
} }
; FIXME: Should prodbably be masking high bits of load. ; FIXME: Should prodbably be masking high bits of load.
; CHECK-LABEL: {{^}}i1_input_phys_vgpr_x2: ; CHECK-LABEL: {{^}}i1_input_phys_vgpr_x2:
; CHECK: buffer_load_ubyte v0 ; CHECK: buffer_load_ubyte v0
; CHECK-NEXT: s_waitcnt
; CHECK-NEXT: buffer_load_ubyte v1 ; CHECK-NEXT: buffer_load_ubyte v1
; CHECK-NEXT: s_waitcnt ; CHECK-NEXT: s_waitcnt
; CHECK-NEXT: ASMSTART ; CHECK-NEXT: ASMSTART
define amdgpu_kernel void @i1_input_phys_vgpr_x2() { define amdgpu_kernel void @i1_input_phys_vgpr_x2() {
entry: entry:
%val0 = load volatile i1, i1 addrspace(1)* undef %val0 = load volatile i1, i1 addrspace(1)* undef
%val1 = load volatile i1, i1 addrspace(1)* undef %val1 = load volatile i1, i1 addrspace(1)* undef
call void asm sideeffect "; use $0 $1 ", "{v0}, {v1}"(i1 %val0, i1 %val1) call void asm sideeffect "; use $0 $1 ", "{v0}, {v1}"(i1 %val0, i1 %val1)
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

Show First 20 Lines • Show All 1,571 Lines • ▼ Show 20 Lines; CI-NEXT: s_endpgm
store <4 x i16> %vecins, <4 x i16> addrspace(1)* %out.gep store <4 x i16> %vecins, <4 x i16> addrspace(1)* %out.gep
ret void ret void
} }
; FIXME: Better code on CI? ; FIXME: Better code on CI?
define amdgpu_kernel void @v_insertelement_v4i16_dynamic_vgpr(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in, i32 %val) #0 { define amdgpu_kernel void @v_insertelement_v4i16_dynamic_vgpr(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(1)* %in, i32 %val) #0 {
; GFX9-LABEL: v_insertelement_v4i16_dynamic_vgpr: ; GFX9-LABEL: v_insertelement_v4i16_dynamic_vgpr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: global_load_dword v2, v[0:1], off ; GFX9-NEXT: global_load_dword v2, v[0:1], off glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX9-NEXT: s_load_dword s4, s[4:5], 0x10 ; GFX9-NEXT: s_load_dword s4, s[4:5], 0x10
; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v4, 3, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3] ; GFX9-NEXT: global_load_dwordx2 v[0:1], v4, s[2:3]
; GFX9-NEXT: s_mov_b32 s3, 0 ; GFX9-NEXT: s_mov_b32 s3, 0
; GFX9-NEXT: s_mov_b32 s2, 0xffff ; GFX9-NEXT: s_mov_b32 s2, 0xffff
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 4, v2 ; GFX9-NEXT: v_lshlrev_b32_e32 v2, 4, v2
; GFX9-NEXT: v_lshlrev_b64 v[2:3], v2, s[2:3] ; GFX9-NEXT: v_lshlrev_b64 v[2:3], v2, s[2:3]
; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s4 ; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s4
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_bfi_b32 v1, v3, s2, v1 ; GFX9-NEXT: v_bfi_b32 v1, v3, s2, v1
; GFX9-NEXT: v_bfi_b32 v0, v2, s2, v0 ; GFX9-NEXT: v_bfi_b32 v0, v2, s2, v0
; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1] ; GFX9-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_insertelement_v4i16_dynamic_vgpr: ; VI-LABEL: v_insertelement_v4i16_dynamic_vgpr:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; VI-NEXT: s_load_dword s4, s[4:5], 0x10 ; VI-NEXT: s_load_dword s4, s[4:5], 0x10
; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v4, v[0:1] ; VI-NEXT: flat_load_dword v4, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; VI-NEXT: s_mov_b32 s2, 0xffff ; VI-NEXT: s_mov_b32 s2, 0xffff
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: s_mov_b32 s3, 0 ; VI-NEXT: s_mov_b32 s3, 0
; VI-NEXT: s_and_b32 s1, s4, s2 ; VI-NEXT: s_and_b32 s1, s4, s2
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: s_lshl_b32 s0, s1, 16 ; VI-NEXT: s_lshl_b32 s0, s1, 16
; VI-NEXT: s_or_b32 s0, s1, s0 ; VI-NEXT: s_or_b32 s0, s1, s0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_lshlrev_b32_e32 v4, 4, v4 ; VI-NEXT: v_lshlrev_b32_e32 v4, 4, v4
; VI-NEXT: v_lshlrev_b64 v[4:5], v4, s[2:3] ; VI-NEXT: v_lshlrev_b64 v[4:5], v4, s[2:3]
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_bfi_b32 v1, v5, s0, v1 ; VI-NEXT: v_bfi_b32 v1, v5, s0, v1
; VI-NEXT: v_bfi_b32 v0, v4, s0, v0 ; VI-NEXT: v_bfi_b32 v0, v4, s0, v0
; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; CI-LABEL: v_insertelement_v4i16_dynamic_vgpr: ; CI-LABEL: v_insertelement_v4i16_dynamic_vgpr:
; CI: ; %bb.0: ; CI: ; %bb.0:
; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0 ; CI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; CI-NEXT: s_load_dword s4, s[4:5], 0x4 ; CI-NEXT: s_load_dword s4, s[4:5], 0x4
; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0 ; CI-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: s_waitcnt lgkmcnt(0)
; CI-NEXT: v_mov_b32_e32 v1, s3 ; CI-NEXT: v_mov_b32_e32 v1, s3
; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v2 ; CI-NEXT: v_add_i32_e32 v0, vcc, s2, v2
; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; CI-NEXT: flat_load_dword v4, v[0:1] ; CI-NEXT: flat_load_dword v4, v[0:1] glc
; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1] ; CI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]
; CI-NEXT: s_mov_b32 s3, 0 ; CI-NEXT: s_mov_b32 s3, 0
; CI-NEXT: s_mov_b32 s2, 0xffff ; CI-NEXT: s_mov_b32 s2, 0xffff
; CI-NEXT: v_mov_b32_e32 v3, s1 ; CI-NEXT: v_mov_b32_e32 v3, s1
; CI-NEXT: s_lshl_b32 s1, s4, 16 ; CI-NEXT: s_lshl_b32 s1, s4, 16
; CI-NEXT: s_and_b32 s4, s4, s2 ; CI-NEXT: s_and_b32 s4, s4, s2
; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v2 ; CI-NEXT: v_add_i32_e32 v2, vcc, s0, v2
; CI-NEXT: s_or_b32 s0, s4, s1 ; CI-NEXT: s_or_b32 s0, s4, s1
; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; CI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; CI-NEXT: s_waitcnt vmcnt(1)
; CI-NEXT: v_lshlrev_b32_e32 v4, 4, v4 ; CI-NEXT: v_lshlrev_b32_e32 v4, 4, v4
; CI-NEXT: v_lshl_b64 v[4:5], s[2:3], v4 ; CI-NEXT: v_lshl_b64 v[4:5], s[2:3], v4
; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_waitcnt vmcnt(0)
; CI-NEXT: v_bfi_b32 v1, v5, s0, v1 ; CI-NEXT: v_bfi_b32 v1, v5, s0, v1
; CI-NEXT: v_bfi_b32 v0, v4, s0, v0 ; CI-NEXT: v_bfi_b32 v0, v4, s0, v0
; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1] ; CI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
; CI-NEXT: s_endpgm ; CI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1 %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
▲ Show 20 Lines • Show All 104 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll

Show First 20 Lines • Show All 95 Lines • ▼ Show 20 Lines
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b64 s[6:7], s[2:3] ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[0:1], s[10:11] ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3] ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v2, v2, v3 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v2, v2, v3
; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_cvt_pkrtz_v2f16_f32: ; VI-LABEL: v_cvt_pkrtz_v2f16_f32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, v1
; VI-NEXT: flat_store_dword v[4:5], v0 ; VI-NEXT: flat_store_dword v[4:5], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32: ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] ; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, v1, v2 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, v1, v2
; GFX9-NEXT: global_store_dword v0, v1, s[4:5] ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
Show All 10 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, 0 ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[2:3] ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, v2, 1.0 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, v2, 1.0
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_cvt_pkrtz_v2f16_f32_reg_imm: ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_reg_imm:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, 1.0 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, 1.0
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[2:3], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_reg_imm: ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_reg_imm:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, v1, 1.0 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, v1, 1.0
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
%a = load volatile float, float addrspace(1)* %a.gep %a = load volatile float, float addrspace(1)* %a.gep
%cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float 1.0) %cvt = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %a, float 1.0)
store <2 x half> %cvt, <2 x half> addrspace(1)* %out.gep store <2 x half> %cvt, <2 x half> addrspace(1)* %out.gep
ret void ret void
} }
define amdgpu_kernel void @v_cvt_pkrtz_v2f16_f32_imm_reg(<2 x half> addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 { define amdgpu_kernel void @v_cvt_pkrtz_v2f16_f32_imm_reg(<2 x half> addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
; SI-LABEL: v_cvt_pkrtz_v2f16_f32_imm_reg: ; SI-LABEL: v_cvt_pkrtz_v2f16_f32_imm_reg:
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, 0 ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[2:3] ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v2, 1.0, v2 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e32 v2, 1.0, v2
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_cvt_pkrtz_v2f16_f32_imm_reg: ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_imm_reg:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, 1.0, v0 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, 1.0, v0
; VI-NEXT: flat_store_dword v[2:3], v0 ; VI-NEXT: flat_store_dword v[2:3], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_imm_reg: ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_imm_reg:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, 1.0, v1 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, 1.0, v1
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %out, i64 %tid.ext
Show All 10 Lines
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b64 s[6:7], s[2:3] ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[0:1], s[10:11] ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3] ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, -v2, v3 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, -v2, v3
; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo: ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, -v0, v1 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, -v0, v1
; VI-NEXT: flat_store_dword v[4:5], v0 ; VI-NEXT: flat_store_dword v[4:5], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo: ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] ; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, -v1, v2 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, -v1, v2
; GFX9-NEXT: global_store_dword v0, v1, s[4:5] ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
Show All 13 Lines
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b64 s[6:7], s[2:3] ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[0:1], s[10:11] ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3] ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, v2, -v3 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, v2, -v3
; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_hi: ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_hi:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, -v1 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, v0, -v1
; VI-NEXT: flat_store_dword v[4:5], v0 ; VI-NEXT: flat_store_dword v[4:5], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_hi: ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_hi:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] ; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, v1, -v2 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, v1, -v2
; GFX9-NEXT: global_store_dword v0, v1, s[4:5] ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
Show All 13 Lines
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b64 s[6:7], s[2:3] ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[0:1], s[10:11] ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3] ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, -v2, -v3 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, -v2, -v3
; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo_hi: ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo_hi:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, -v0, -v1 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, -v0, -v1
; VI-NEXT: flat_store_dword v[4:5], v0 ; VI-NEXT: flat_store_dword v[4:5], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo_hi: ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_lo_hi:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] ; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, -v1, -v2 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, -v1, -v2
; GFX9-NEXT: global_store_dword v0, v1, s[4:5] ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
Show All 14 Lines
; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd ; SI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0xd
; SI-NEXT: s_mov_b32 s3, 0xf000 ; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, 0 ; SI-NEXT: s_mov_b32 s2, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_mov_b64 s[6:7], s[2:3] ; SI-NEXT: s_mov_b64 s[6:7], s[2:3]
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[0:1], s[10:11] ; SI-NEXT: s_mov_b64 s[0:1], s[10:11]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[0:3], 0 addr64 glc
; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3] ; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[10:11], s[2:3]
; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, -|v2|, -v3 ; SI-NEXT: v_cvt_pkrtz_f16_f32_e64 v2, -|v2|, -v3
; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[8:11], 0 addr64
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_fabs_lo_fneg_hi: ; VI-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_fabs_lo_fneg_hi:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v4
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v4
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v5, s5 ; VI-NEXT: v_mov_b32_e32 v5, s5
; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4 ; VI-NEXT: v_add_u32_e32 v4, vcc, s4, v4
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, -|v0|, -v1 ; VI-NEXT: v_cvt_pkrtz_f16_f32 v0, -|v0|, -v1
; VI-NEXT: flat_store_dword v[4:5], v0 ; VI-NEXT: flat_store_dword v[4:5], v0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_fabs_lo_fneg_hi: ; GFX9-LABEL: v_cvt_pkrtz_v2f16_f32_fneg_fabs_lo_fneg_hi:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] ; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, -|v1|, -v2 ; GFX9-NEXT: v_cvt_pkrtz_f16_f32 v1, -|v1|, -v2
; GFX9-NEXT: global_store_dword v0, v1, s[4:5] ; GFX9-NEXT: global_store_dword v0, v1, s[4:5]
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext %a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
%b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext %b.gep = getelementptr inbounds float, float addrspace(1)* %b.ptr, i64 %tid.ext
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/llvm.amdgcn.div.fmas.ll

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}} ; GCN: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { define amdgpu_kernel void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
%result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone %result = call float @llvm.amdgcn.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone
store float %result, float addrspace(1)* %out, align 4 store float %result, float addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc: ; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: v_cmp_eq_u32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}} ; SI-DAG: v_cmp_eq_u32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
; SI-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}} ; SI-DAG: v_cmp_ne_u32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], s{{[0-9]+}}, 0{{$}}
; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]] ; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]] ; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]]
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind { define amdgpu_kernel void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind {
%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
▲ Show 20 Lines • Show All 63 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.maxnum.f16.ll

Show All 16 Lines
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s14, s2 ; SI-NEXT: s_mov_b32 s14, s2
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s12, s6 ; SI-NEXT: s_mov_b32 s12, s6
; SI-NEXT: s_mov_b32 s13, s7 ; SI-NEXT: s_mov_b32 s13, s7
; SI-NEXT: s_mov_b32 s15, s3 ; SI-NEXT: s_mov_b32 s15, s3
; SI-NEXT: s_mov_b32 s10, s2 ; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3 ; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0 ; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: v_max_f32_e32 v0, v0, v1 ; SI-NEXT: v_max_f32_e32 v0, v0, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: maxnum_f16: ; VI-LABEL: maxnum_f16:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s14, s2 ; VI-NEXT: s_mov_b32 s14, s2
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s12, s6 ; VI-NEXT: s_mov_b32 s12, s6
; VI-NEXT: s_mov_b32 s13, s7 ; VI-NEXT: s_mov_b32 s13, s7
; VI-NEXT: s_mov_b32 s15, s3 ; VI-NEXT: s_mov_b32 s15, s3
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_max_f16_e32 v0, v0, v0 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_max_f16_e32 v1, v1, v1 ; VI-NEXT: v_max_f16_e32 v1, v1, v1
; VI-NEXT: v_max_f16_e32 v0, v0, v1 ; VI-NEXT: v_max_f16_e32 v0, v0, v1
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: maxnum_f16: ; GFX9-LABEL: maxnum_f16:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_mov_b32 s14, s2 ; GFX9-NEXT: s_mov_b32 s14, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s12, s6 ; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s13, s7 ; GFX9-NEXT: s_mov_b32 s13, s7
; GFX9-NEXT: s_mov_b32 s15, s3 ; GFX9-NEXT: s_mov_b32 s15, s3
; GFX9-NEXT: s_mov_b32 s10, s2 ; GFX9-NEXT: s_mov_b32 s10, s2
; GFX9-NEXT: s_mov_b32 s11, s3 ; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; GFX9-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; GFX9-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_max_f16_e32 v0, v0, v0 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f16_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f16_e32 v1, v1, v1
; GFX9-NEXT: v_max_f16_e32 v0, v0, v1 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v1
; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %b) #0 { half addrspace(1)* %b) #0 {
entry: entry:
▲ Show 20 Lines • Show All 665 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/llvm.minnum.f16.ll

Show All 16 Lines
; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_mov_b32 s14, s2 ; SI-NEXT: s_mov_b32 s14, s2
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s12, s6 ; SI-NEXT: s_mov_b32 s12, s6
; SI-NEXT: s_mov_b32 s13, s7 ; SI-NEXT: s_mov_b32 s13, s7
; SI-NEXT: s_mov_b32 s15, s3 ; SI-NEXT: s_mov_b32 s15, s3
; SI-NEXT: s_mov_b32 s10, s2 ; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3 ; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0 ; SI-NEXT: v_mul_f32_e32 v0, 1.0, v0
; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1 ; SI-NEXT: v_mul_f32_e32 v1, 1.0, v1
; SI-NEXT: v_min_f32_e32 v0, v0, v1 ; SI-NEXT: v_min_f32_e32 v0, v0, v1
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: minnum_f16_ieee: ; VI-LABEL: minnum_f16_ieee:
; VI: ; %bb.0: ; %entry ; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s14, s2 ; VI-NEXT: s_mov_b32 s14, s2
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s12, s6 ; VI-NEXT: s_mov_b32 s12, s6
; VI-NEXT: s_mov_b32 s13, s7 ; VI-NEXT: s_mov_b32 s13, s7
; VI-NEXT: s_mov_b32 s15, s3 ; VI-NEXT: s_mov_b32 s15, s3
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_max_f16_e32 v0, v0, v0 ; VI-NEXT: v_max_f16_e32 v0, v0, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_max_f16_e32 v1, v1, v1 ; VI-NEXT: v_max_f16_e32 v1, v1, v1
; VI-NEXT: v_min_f16_e32 v0, v0, v1 ; VI-NEXT: v_min_f16_e32 v0, v0, v1
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: minnum_f16_ieee: ; GFX9-LABEL: minnum_f16_ieee:
; GFX9: ; %bb.0: ; %entry ; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_mov_b32 s14, s2 ; GFX9-NEXT: s_mov_b32 s14, s2
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s12, s6 ; GFX9-NEXT: s_mov_b32 s12, s6
; GFX9-NEXT: s_mov_b32 s13, s7 ; GFX9-NEXT: s_mov_b32 s13, s7
; GFX9-NEXT: s_mov_b32 s15, s3 ; GFX9-NEXT: s_mov_b32 s15, s3
; GFX9-NEXT: s_mov_b32 s10, s2 ; GFX9-NEXT: s_mov_b32 s10, s2
; GFX9-NEXT: s_mov_b32 s11, s3 ; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; GFX9-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; GFX9-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_max_f16_e32 v0, v0, v0 ; GFX9-NEXT: v_max_f16_e32 v0, v0, v0
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_max_f16_e32 v1, v1, v1 ; GFX9-NEXT: v_max_f16_e32 v1, v1, v1
; GFX9-NEXT: v_min_f16_e32 v0, v0, v1 ; GFX9-NEXT: v_min_f16_e32 v0, v0, v1
; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_short v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %b) #0 { half addrspace(1)* %b) #0 {
entry: entry:
▲ Show 20 Lines • Show All 718 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/load-hi16.ll

Show First 20 Lines • Show All 530 Lines • ▼ Show 20 Linesentry:
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX900-MUBUFF: buffer_load_short_d16_hi v0, off, s[0:3], 0 offset:4094{{$}} ; GFX900-MUBUFF: buffer_load_short_d16_hi v0, off, s[0:3], 0 offset:4094{{$}}
; GFX900-FLATSCR: s_movk_i32 [[SOFF:[^,]+]], 0xffe ; GFX900-FLATSCR: s_movk_i32 [[SOFF:[^,]+]], 0xffe
; GFX900-FLATSCR: scratch_load_short_d16_hi v0, off, [[SOFF]]{{$}} ; GFX900-FLATSCR: scratch_load_short_d16_hi v0, off, [[SOFF]] glc{{$}}
; GFX900: s_waitcnt ; GFX900: s_waitcnt
; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: s_setpc_b64 ; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], 0 offset:4094{{$}} ; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], 0 offset:4094 glc{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval(i16) %in, i16 %reg) #0 {
entry: entry:
%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff: ; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX900-MUBUF-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], 0 offset:4094{{$}} ; GFX900-MUBUF-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], 0 offset:4094 glc{{$}}
; GFX900-FLATSCR-NEXT: s_movk_i32 [[SOFF:[^,]+]], 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 [[SOFF:[^,]+]], 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_short_d16_hi v1, off, [[SOFF]]{{$}} ; GFX900-FLATSCR-NEXT: scratch_load_short_d16_hi v1, off, [[SOFF]] glc{{$}}
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: s_setpc_b64 ; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], 0 offset:4094{{$}} ; NO-D16-HI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], 0 offset:4094 glc{{$}}
define void @load_private_hi_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, half %reg) #0 { define void @load_private_hi_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, half %reg) #0 {
entry: entry:
%load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*) %load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*)
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1 %build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
▲ Show 20 Lines • Show All 81 Lines • ▼ Show 20 Linesentry:
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_zexti8: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], 0 offset:4094{{$}} ; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], 0 offset:4094 glc{{$}}
; GFX900-FLATSCR-NEXT: s_movk_i32 [[SOFF:[^,]+]], 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 [[SOFF:[^,]+]], 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16_hi v1, off, [[SOFF]]{{$}} ; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16_hi v1, off, [[SOFF]] glc{{$}}
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: s_setpc_b64 ; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094{{$}} ; NO-D16-HI: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 glc{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_sexti8: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_sexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16_hi v1, off, s[0:3], 0 offset:4094{{$}} ; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16_hi v1, off, s[0:3], 0 offset:4094 glc{{$}}
; GFX900-FLATSCR-NEXT: s_movk_i32 [[SOFF:[^,]+]], 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 [[SOFF:[^,]+]], 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16_hi v1, off, [[SOFF]]{{$}} ; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16_hi v1, off, [[SOFF]] glc{{$}}
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: s_setpc_b64 ; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_sbyte v0, off, s[0:3], 0 offset:4094{{$}} ; NO-D16-HI: buffer_load_sbyte v0, off, s[0:3], 0 offset:4094 glc{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff_zexti8: ; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], 0 offset:4094{{$}} ; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], 0 offset:4094 glc{{$}}
; GFX900-FLATSCR-NEXT: s_movk_i32 [[SOFF:[^,]+]], 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 [[SOFF:[^,]+]], 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16_hi v1, off, [[SOFF]]{{$}} ; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16_hi v1, off, [[SOFF]] glc{{$}}
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX900-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: s_setpc_b64 ; GFX900-NEXT: s_setpc_b64
; NO-D16-HI: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094{{$}} ; NO-D16-HI: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 glc{{$}}
define void @load_private_hi_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, half %reg) #0 { define void @load_private_hi_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, half %reg) #0 {
entry: entry:
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%bc.ext = bitcast i16 %ext to half %bc.ext = bitcast i16 %ext to half
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bc.ext, i32 1 %build1 = insertelement <2 x half> %build0, half %bc.ext, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
▲ Show 20 Lines • Show All 78 Lines • ▼ Show 20 Linesentry:
ret void ret void
} }
; Local object gives known offset, so requires converting from offen ; Local object gives known offset, so requires converting from offen
; to offset variant. ; to offset variant.
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_to_offset: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_to_offset:
; GFX900-MUBUF: buffer_store_dword ; GFX900-MUBUF: buffer_store_dword
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_short_d16_hi v{{[0-9]+}}, off, s[0:3], s32 offset:4094 ; GFX900-MUBUF-NEXT: buffer_load_short_d16_hi v{{[0-9]+}}, off, s[0:3], s32 offset:4094
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR: scratch_store_dword ; GFX900-FLATSCR: scratch_store_dword
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_load_short_d16_hi v{{[0-9]+}}, off, s32 offset:4094 ; GFX900-FLATSCR-NEXT: scratch_load_short_d16_hi v{{[0-9]+}}, off, s32 offset:4094
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
define void @load_private_hi_v2i16_reglo_vreg_to_offset(i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_to_offset(i16 %reg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i16], align 2, addrspace(5) %obj1 = alloca [4096 x i16], align 2, addrspace(5)
%bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32 addrspace(5)* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2027 %gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2027
%load = load i16, i16 addrspace(5)* %gep %load = load i16, i16 addrspace(5)* %gep
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_sexti8_to_offset: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_sexti8_to_offset:
; GFX900-MUBUF: buffer_store_dword ; GFX900-MUBUF: buffer_store_dword
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16_hi v{{[0-9]+}}, off, s[0:3], s32 offset:4095 ; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16_hi v{{[0-9]+}}, off, s[0:3], s32 offset:4095
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR: scratch_store_dword ; GFX900-FLATSCR: scratch_store_dword
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16_hi v{{[0-9]+}}, off, s32 offset:4095 ; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16_hi v{{[0-9]+}}, off, s32 offset:4095
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
define void @load_private_hi_v2i16_reglo_vreg_sexti8_to_offset(i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_sexti8_to_offset(i16 %reg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5) %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32 addrspace(5)* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055
%load = load i8, i8 addrspace(5)* %gep %load = load i8, i8 addrspace(5)* %gep
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_zexti8_to_offset: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_zexti8_to_offset:
; GFX900-MUBUF: buffer_store_dword ; GFX900-MUBUF: buffer_store_dword
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16_hi v{{[0-9]+}}, off, s[0:3], s32 offset:4095 ; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16_hi v{{[0-9]+}}, off, s[0:3], s32 offset:4095
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR: scratch_store_dword ; GFX900-FLATSCR: scratch_store_dword
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16_hi v{{[0-9]+}}, off, s32 offset:4095 ; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16_hi v{{[0-9]+}}, off, s32 offset:4095
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
define void @load_private_hi_v2i16_reglo_vreg_zexti8_to_offset(i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_zexti8_to_offset(i16 %reg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5) %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32 addrspace(5)* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055
%load = load i8, i8 addrspace(5)* %gep %load = load i8, i8 addrspace(5)* %gep
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Linesentry:
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1 ret <2 x i16> %build1
} }
; FIXME: Remove m0 init and waitcnt between reads ; FIXME: Remove m0 init and waitcnt between reads
; FIXME: Is there a cost to using the extload over not? ; FIXME: Is there a cost to using the extload over not?
; GCN-LABEL: {{^}}load_private_v2i16_split: ; GCN-LABEL: {{^}}load_private_v2i16_split:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX900-MUBUF: buffer_load_ushort v0, off, s[0:3], s32{{$}} ; GFX900-MUBUF: buffer_load_ushort v0, off, s[0:3], s32 glc{{$}}
; GFX900-FLATSCR: scratch_load_ushort v0, off, s32{{$}} ; GFX900-FLATSCR: scratch_load_ushort v0, off, s32 glc{{$}}
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-MUBUF-NEXT: buffer_load_short_d16_hi v0, off, s[0:3], s32 offset:2 ; GFX900-MUBUF-NEXT: buffer_load_short_d16_hi v0, off, s[0:3], s32 offset:2
; GFX900-FLATSCR-NEXT: scratch_load_short_d16_hi v0, off, s32 offset:2 ; GFX900-FLATSCR-NEXT: scratch_load_short_d16_hi v0, off, s32 offset:2
; GFX900-NEXT: s_waitcnt ; GFX900-NEXT: s_waitcnt
; GFX900-NEXT: s_setpc_b64 ; GFX900-NEXT: s_setpc_b64
define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval(i16) %in) #0 { define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval(i16) %in) #0 {
entry: entry:
%gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i32 1 %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i32 1
Show All 28 Lines

llvm/test/CodeGen/AMDGPU/load-lo16.ll

Show First 20 Lines • Show All 1,327 Lines • ▼ Show 20 Linesentry:
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
define void @load_private_lo_v2i16_reglo_vreg_nooff(i16 addrspace(5)* %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_nooff(i16 addrspace(5)* %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_nooff: ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_nooff:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_short_d16 v1, off, s[0:3], 0 offset:4094 ; GFX900-MUBUF-NEXT: buffer_load_short_d16 v1, off, s[0:3], 0 offset:4094 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_nooff: ; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_nooff:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 ; GFX906-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 glc
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1 ; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff: ; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 ; GFX803-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 glc
; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_nooff: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_nooff:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_short_d16 v1, off, s0 ; GFX900-FLATSCR-NEXT: scratch_load_short_d16 v1, off, s0 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
define void @load_private_lo_v2i16_reghi_vreg_nooff(i16 addrspace(5)* %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reghi_vreg_nooff(i16 addrspace(5)* %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reghi_vreg_nooff: ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reghi_vreg_nooff:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_short_d16 v1, off, s[0:3], 0 offset:4094 ; GFX900-MUBUF-NEXT: buffer_load_short_d16 v1, off, s[0:3], 0 offset:4094 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2i16_reghi_vreg_nooff: ; GFX906-LABEL: load_private_lo_v2i16_reghi_vreg_nooff:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 ; GFX906-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 glc
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1 ; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2i16_reghi_vreg_nooff: ; GFX803-LABEL: load_private_lo_v2i16_reghi_vreg_nooff:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 ; GFX803-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 glc
; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reghi_vreg_nooff: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reghi_vreg_nooff:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_short_d16 v1, off, s0 ; GFX900-FLATSCR-NEXT: scratch_load_short_d16 v1, off, s0 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
define void @load_private_lo_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, i32 %reg) #0 { define void @load_private_lo_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg_nooff: ; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg_nooff:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_short_d16 v1, off, s[0:3], 0 offset:4094 ; GFX900-MUBUF-NEXT: buffer_load_short_d16 v1, off, s[0:3], 0 offset:4094 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_nooff: ; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_nooff:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 ; GFX906-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 glc
; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_nooff: ; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_nooff:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 ; GFX803-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:4094 glc
; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: v_or_b32_e32 v0, v0, v1 ; GFX803-NEXT: v_or_b32_e32 v0, v0, v1
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_nooff: ; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_nooff:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_short_d16 v1, off, s0 ; GFX900-FLATSCR-NEXT: scratch_load_short_d16 v1, off, s0 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*) %load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*)
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0 %build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
▲ Show 20 Lines • Show All 101 Lines • ▼ Show 20 Linesentry:
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
define void @load_private_lo_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8: ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], 0 offset:4094 ; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], 0 offset:4094 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8: ; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 ; GFX906-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 glc
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1 ; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8: ; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], 0 offset:4094 ; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], 0 offset:4094 glc
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4 ; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v1, off, s0 ; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v1, off, s0 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
define void @load_private_lo_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8: ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16 v1, off, s[0:3], 0 offset:4094 ; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16 v1, off, s[0:3], 0 offset:4094 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8: ; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: buffer_load_sbyte v0, off, s[0:3], 0 offset:4094 ; GFX906-NEXT: buffer_load_sbyte v0, off, s[0:3], 0 offset:4094 glc
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1 ; GFX906-NEXT: v_bfi_b32 v0, v2, v0, v1
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8: ; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: buffer_load_sbyte v0, off, s[0:3], 0 offset:4094 ; GFX803-NEXT: buffer_load_sbyte v0, off, s[0:3], 0 offset:4094 glc
; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16 v1, off, s0 ; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16 v1, off, s0 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
define void @load_private_lo_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i32 %reg) #0 { define void @load_private_lo_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8: ; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], 0 offset:4094 ; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], 0 offset:4094 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v1, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8: ; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 ; GFX906-NEXT: buffer_load_ubyte v0, off, s[0:3], 0 offset:4094 glc
; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX906-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX906-NEXT: v_lshl_or_b32 v0, v1, 16, v0
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8: ; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v1 ; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v1
; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], 0 offset:4094 ; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], 0 offset:4094 glc
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4 ; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8: ; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe ; GFX900-FLATSCR-NEXT: s_movk_i32 s0, 0xffe
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v1, off, s0 ; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v1, off, s0 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v1, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
▲ Show 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
} }
define void @load_private_lo_v2i16_reglo_vreg_to_offset(i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_to_offset(i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset: ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX900-MUBUF-NEXT: buffer_load_short_d16 v0, off, s[0:3], s32 offset:4094 ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_short_d16 v0, off, s[0:3], s32 offset:4094 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset: ; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX906-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094 glc
; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0 ; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset: ; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094
; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094 glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX803-NEXT: v_or_b32_e32 v0, v1, v0 ; GFX803-NEXT: v_or_b32_e32 v0, v1, v0
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_to_offset:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32 ; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32
; GFX900-FLATSCR-NEXT: scratch_load_short_d16 v0, off, s32 offset:4094 ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_load_short_d16 v0, off, s32 offset:4094 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i16], align 2, addrspace(5) %obj1 = alloca [4096 x i16], align 2, addrspace(5)
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32 addrspace(5)* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2027 %gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2027
%load = load volatile i16, i16 addrspace(5)* %gep %load = load volatile i16, i16 addrspace(5)* %gep
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
define void @load_private_lo_v2i16_reglo_vreg_sexti8_to_offset(i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_sexti8_to_offset(i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset: ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095 ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset: ; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX906-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095 glc
; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0 ; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset: ; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX803-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095 glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX803-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32 ; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32
; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16 v0, off, s32 offset:4095 ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16 v0, off, s32 offset:4095 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5) %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32 addrspace(5)* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055
%load = load volatile i8, i8 addrspace(5)* %gep %load = load volatile i8, i8 addrspace(5)* %gep
%load.ext = sext i8 %load to i16 %load.ext = sext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
define void @load_private_lo_v2i16_reglo_vreg_zexti8_to_offset(i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_zexti8_to_offset(i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset: ; GFX900-MUBUF-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095 ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset: ; GFX906-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX906-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095 glc
; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0 ; GFX906-NEXT: v_bfi_b32 v0, v2, v1, v0
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset: ; GFX803-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095 ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095 glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00 ; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4 ; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset: ; GFX900-FLATSCR-LABEL: load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32 ; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v0, off, s32 offset:4095 ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v0, off, s32 offset:4095 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5) %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32 addrspace(5)* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055
%load = load volatile i8, i8 addrspace(5)* %gep %load = load volatile i8, i8 addrspace(5)* %gep
%load.ext = zext i8 %load to i16 %load.ext = zext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
define void @load_private_lo_v2f16_reglo_vreg_sexti8_to_offset(i32 %reg) #0 { define void @load_private_lo_v2f16_reglo_vreg_sexti8_to_offset(i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset: ; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095 ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s32 offset:4095 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset: ; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX906-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
; GFX906-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095 glc
; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX906-NEXT: v_lshl_or_b32 v0, v0, 16, v1 ; GFX906-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset: ; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX803-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095
; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_load_sbyte v1, off, s[0:3], s32 offset:4095 glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_and_b32_e32 v0, 0xffff0000, v0
; GFX803-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset: ; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_sexti8_to_offset:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32 ; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32
; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16 v0, off, s32 offset:4095 ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_load_sbyte_d16 v0, off, s32 offset:4095 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5) %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
Show All 9 Lines
} }
define void @load_private_lo_v2f16_reglo_vreg_zexti8_to_offset(i32 %reg) #0 { define void @load_private_lo_v2f16_reglo_vreg_zexti8_to_offset(i32 %reg) #0 {
; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset: ; GFX900-MUBUF-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset:
; GFX900-MUBUF: ; %bb.0: ; %entry ; GFX900-MUBUF: ; %bb.0: ; %entry
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-MUBUF-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX900-MUBUF-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095 ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s32 offset:4095 glc
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off ; GFX900-MUBUF-NEXT: global_store_dword v[0:1], v0, off
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0) ; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31] ; GFX900-MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset: ; GFX906-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset:
; GFX906: ; %bb.0: ; %entry ; GFX906: ; %bb.0: ; %entry
; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX906-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX906-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX906-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095
; GFX906-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095 glc
; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX906-NEXT: v_and_b32_e32 v1, 0xffff, v1
; GFX906-NEXT: v_lshl_or_b32 v0, v0, 16, v1 ; GFX906-NEXT: v_lshl_or_b32 v0, v0, 16, v1
; GFX906-NEXT: global_store_dword v[0:1], v0, off ; GFX906-NEXT: global_store_dword v[0:1], v0, off
; GFX906-NEXT: s_waitcnt vmcnt(0) ; GFX906-NEXT: s_waitcnt vmcnt(0)
; GFX906-NEXT: s_setpc_b64 s[30:31] ; GFX906-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset: ; GFX803-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset:
; GFX803: ; %bb.0: ; %entry ; GFX803: ; %bb.0: ; %entry
; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX803-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32 ; GFX803-NEXT: buffer_store_dword v1, off, s[0:3], s32
; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095 ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: buffer_load_ubyte v1, off, s[0:3], s32 offset:4095 glc
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; GFX803-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX803-NEXT: s_mov_b32 s4, 0x5040c00 ; GFX803-NEXT: s_mov_b32 s4, 0x5040c00
; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4 ; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4
; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: flat_store_dword v[0:1], v0
; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_waitcnt vmcnt(0)
; GFX803-NEXT: s_setpc_b64 s[30:31] ; GFX803-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset: ; GFX900-FLATSCR-LABEL: load_private_lo_v2f16_reglo_vreg_zexti8_to_offset:
; GFX900-FLATSCR: ; %bb.0: ; %entry ; GFX900-FLATSCR: ; %bb.0: ; %entry
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b ; GFX900-FLATSCR-NEXT: v_mov_b32_e32 v1, 0x7b
; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32 ; GFX900-FLATSCR-NEXT: scratch_store_dword off, v1, s32
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v0, off, s32 offset:4095 ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_load_ubyte_d16 v0, off, s32 offset:4095 glc
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; GFX900-FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0) ; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31] ; GFX900-FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5) %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
Show All 12 Lines

llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll

Show All 24 Lines
; MUBUF-NEXT: s_add_u32 s0, s0, s9 ; MUBUF-NEXT: s_add_u32 s0, s0, s9
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000
; MUBUF-NEXT: s_addc_u32 s1, s1, 0 ; MUBUF-NEXT: s_addc_u32 s1, s1, 0
; MUBUF-NEXT: v_add_u32_e32 v0, 64, v1 ; MUBUF-NEXT: v_add_u32_e32 v0, 64, v1
; MUBUF-NEXT: v_mov_b32_e32 v2, 0 ; MUBUF-NEXT: v_mov_b32_e32 v2, 0
; MUBUF-NEXT: v_mov_b32_e32 v3, 0x2000 ; MUBUF-NEXT: v_mov_b32_e32 v3, 0x2000
; MUBUF-NEXT: s_mov_b32 s6, 0 ; MUBUF-NEXT: s_mov_b32 s6, 0
; MUBUF-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: BB0_1: ; %loadstoreloop ; MUBUF-NEXT: BB0_1: ; %loadstoreloop
; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1 ; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1
; MUBUF-NEXT: v_add_u32_e32 v3, s6, v1 ; MUBUF-NEXT: v_add_u32_e32 v3, s6, v1
; MUBUF-NEXT: s_add_i32 s6, s6, 1 ; MUBUF-NEXT: s_add_i32 s6, s6, 1
; MUBUF-NEXT: s_cmpk_lt_u32 s6, 0x2120 ; MUBUF-NEXT: s_cmpk_lt_u32 s6, 0x2120
; MUBUF-NEXT: buffer_store_byte v2, v3, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_byte v2, v3, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_cbranch_scc1 BB0_1 ; MUBUF-NEXT: s_cbranch_scc1 BB0_1
; MUBUF-NEXT: ; %bb.2: ; %split ; MUBUF-NEXT: ; %bb.2: ; %split
; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000 ; MUBUF-NEXT: v_mov_b32_e32 v1, 0x3000
; MUBUF-NEXT: v_add_u32_e32 v1, 0x20d0, v1 ; MUBUF-NEXT: v_add_u32_e32 v1, 0x20d0, v1
; MUBUF-NEXT: buffer_load_dword v2, v1, s[0:3], 0 offen ; MUBUF-NEXT: buffer_load_dword v2, v1, s[0:3], 0 offen glc
; MUBUF-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v3, v0, s[0:3], 0 offen ; MUBUF-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen offset:4 glc
; MUBUF-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_waitcnt vmcnt(1) ; MUBUF-NEXT: buffer_load_dword v3, v0, s[0:3], 0 offen glc
; MUBUF-NEXT: v_add_co_u32_e32 v0, vcc, v2, v3 ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v4, v0, s[0:3], 0 offen offset:4 glc
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_co_u32_e32 v0, vcc, v2, v3
; MUBUF-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc ; MUBUF-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v4, vcc
; MUBUF-NEXT: v_mov_b32_e32 v2, 0 ; MUBUF-NEXT: v_mov_b32_e32 v2, 0
; MUBUF-NEXT: s_waitcnt lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5] ; MUBUF-NEXT: global_store_dwordx2 v2, v[0:1], s[4:5]
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_endpgm ; MUBUF-NEXT: s_endpgm
; ;
; FLATSCR-LABEL: local_stack_offset_uses_sp: ; FLATSCR-LABEL: local_stack_offset_uses_sp:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: s_movk_i32 vcc_hi, 0x2000 ; FLATSCR-NEXT: s_movk_i32 vcc_hi, 0x2000
; FLATSCR-NEXT: s_mov_b32 s2, 0 ; FLATSCR-NEXT: s_mov_b32 s2, 0
; FLATSCR-NEXT: scratch_store_dword off, v0, vcc_hi ; FLATSCR-NEXT: scratch_store_dword off, v0, vcc_hi
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: BB0_1: ; %loadstoreloop ; FLATSCR-NEXT: BB0_1: ; %loadstoreloop
; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1
; FLATSCR-NEXT: s_add_u32 s3, 0x3000, s2 ; FLATSCR-NEXT: s_add_u32 s3, 0x3000, s2
; FLATSCR-NEXT: s_add_i32 s2, s2, 1 ; FLATSCR-NEXT: s_add_i32 s2, s2, 1
; FLATSCR-NEXT: s_cmpk_lt_u32 s2, 0x2120 ; FLATSCR-NEXT: s_cmpk_lt_u32 s2, 0x2120
; FLATSCR-NEXT: scratch_store_byte off, v0, s3 ; FLATSCR-NEXT: scratch_store_byte off, v0, s3
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_cbranch_scc1 BB0_1 ; FLATSCR-NEXT: s_cbranch_scc1 BB0_1
; FLATSCR-NEXT: ; %bb.2: ; %split ; FLATSCR-NEXT: ; %bb.2: ; %split
; FLATSCR-NEXT: s_movk_i32 s2, 0x2000 ; FLATSCR-NEXT: s_movk_i32 s2, 0x2000
; FLATSCR-NEXT: s_add_u32 s2, 0x3000, s2 ; FLATSCR-NEXT: s_add_u32 s2, 0x3000, s2
; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s2 offset:208 ; FLATSCR-NEXT: scratch_load_dwordx2 v[0:1], off, s2 offset:208 glc
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_movk_i32 s2, 0x3000 ; FLATSCR-NEXT: s_movk_i32 s2, 0x3000
; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s2 offset:64 ; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s2 offset:64 glc
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 ; FLATSCR-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2
; FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc ; FLATSCR-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc
; FLATSCR-NEXT: v_mov_b32_e32 v2, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; FLATSCR-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1] ; FLATSCR-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_endpgm ; FLATSCR-NEXT: s_endpgm
entry: entry:
%pin.low = alloca i32, align 8192, addrspace(5) %pin.low = alloca i32, align 8192, addrspace(5)
%local.area = alloca [1060 x i64], align 4096, addrspace(5) %local.area = alloca [1060 x i64], align 4096, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %pin.low store volatile i32 0, i32 addrspace(5)* %pin.low
%local.area.cast = bitcast [1060 x i64] addrspace(5)* %local.area to i8 addrspace(5)* %local.area.cast = bitcast [1060 x i64] addrspace(5)* %local.area to i8 addrspace(5)*
call void @llvm.memset.p5i8.i32(i8 addrspace(5)* align 4 %local.area.cast, i8 0, i32 8480, i1 true) call void @llvm.memset.p5i8.i32(i8 addrspace(5)* align 4 %local.area.cast, i8 0, i32 8480, i1 true)
%gep.large.offset = getelementptr inbounds [1060 x i64], [1060 x i64] addrspace(5)* %local.area, i64 0, i64 1050 %gep.large.offset = getelementptr inbounds [1060 x i64], [1060 x i64] addrspace(5)* %local.area, i64 0, i64 1050
Show All 14 Lines
; MUBUF-NEXT: s_and_b32 s33, s4, 0xfff80000 ; MUBUF-NEXT: s_and_b32 s33, s4, 0xfff80000
; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33 ; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33
; MUBUF-NEXT: v_add_u32_e32 v3, 0x1000, v3 ; MUBUF-NEXT: v_add_u32_e32 v3, 0x1000, v3
; MUBUF-NEXT: v_mov_b32_e32 v4, 0 ; MUBUF-NEXT: v_mov_b32_e32 v4, 0
; MUBUF-NEXT: v_add_u32_e32 v2, 64, v3 ; MUBUF-NEXT: v_add_u32_e32 v2, 64, v3
; MUBUF-NEXT: s_mov_b32 s4, 0 ; MUBUF-NEXT: s_mov_b32 s4, 0
; MUBUF-NEXT: s_add_u32 s32, s32, 0x180000 ; MUBUF-NEXT: s_add_u32 s32, s32, 0x180000
; MUBUF-NEXT: buffer_store_dword v4, off, s[0:3], s33 ; MUBUF-NEXT: buffer_store_dword v4, off, s[0:3], s33
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: BB1_1: ; %loadstoreloop ; MUBUF-NEXT: BB1_1: ; %loadstoreloop
; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1 ; MUBUF-NEXT: ; =>This Inner Loop Header: Depth=1
; MUBUF-NEXT: v_add_u32_e32 v5, s4, v3 ; MUBUF-NEXT: v_add_u32_e32 v5, s4, v3
; MUBUF-NEXT: s_add_i32 s4, s4, 1 ; MUBUF-NEXT: s_add_i32 s4, s4, 1
; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120 ; MUBUF-NEXT: s_cmpk_lt_u32 s4, 0x2120
; MUBUF-NEXT: buffer_store_byte v4, v5, s[0:3], 0 offen ; MUBUF-NEXT: buffer_store_byte v4, v5, s[0:3], 0 offen
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_cbranch_scc1 BB1_1 ; MUBUF-NEXT: s_cbranch_scc1 BB1_1
; MUBUF-NEXT: ; %bb.2: ; %split ; MUBUF-NEXT: ; %bb.2: ; %split
; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33 ; MUBUF-NEXT: v_lshrrev_b32_e64 v3, 6, s33
; MUBUF-NEXT: v_add_u32_e32 v3, 0x1000, v3 ; MUBUF-NEXT: v_add_u32_e32 v3, 0x1000, v3
; MUBUF-NEXT: v_add_u32_e32 v3, 0x20d0, v3 ; MUBUF-NEXT: v_add_u32_e32 v3, 0x20d0, v3
; MUBUF-NEXT: buffer_load_dword v4, v3, s[0:3], 0 offen ; MUBUF-NEXT: buffer_load_dword v4, v3, s[0:3], 0 offen glc
; MUBUF-NEXT: buffer_load_dword v3, v3, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v5, v2, s[0:3], 0 offen ; MUBUF-NEXT: buffer_load_dword v3, v3, s[0:3], 0 offen offset:4 glc
; MUBUF-NEXT: buffer_load_dword v6, v2, s[0:3], 0 offen offset:4 ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v5, v2, s[0:3], 0 offen glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: buffer_load_dword v6, v2, s[0:3], 0 offen offset:4 glc
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_sub_u32 s32, s32, 0x180000 ; MUBUF-NEXT: s_sub_u32 s32, s32, 0x180000
; MUBUF-NEXT: s_mov_b32 s33, s5 ; MUBUF-NEXT: s_mov_b32 s33, s5
; MUBUF-NEXT: s_waitcnt vmcnt(1)
; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v4, v5 ; MUBUF-NEXT: v_add_co_u32_e32 v2, vcc, v4, v5
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v6, vcc ; MUBUF-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v6, vcc
; MUBUF-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; MUBUF-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_setpc_b64 s[30:31] ; MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; FLATSCR-LABEL: func_local_stack_offset_uses_sp: ; FLATSCR-LABEL: func_local_stack_offset_uses_sp:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR-NEXT: s_add_u32 s0, s32, 0x1fff ; FLATSCR-NEXT: s_add_u32 s0, s32, 0x1fff
; FLATSCR-NEXT: s_mov_b32 s2, s33 ; FLATSCR-NEXT: s_mov_b32 s2, s33
; FLATSCR-NEXT: s_and_b32 s33, s0, 0xffffe000 ; FLATSCR-NEXT: s_and_b32 s33, s0, 0xffffe000
; FLATSCR-NEXT: v_mov_b32_e32 v2, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v2, 0
; FLATSCR-NEXT: s_mov_b32 s0, 0 ; FLATSCR-NEXT: s_mov_b32 s0, 0
; FLATSCR-NEXT: s_add_u32 s32, s32, 0x6000 ; FLATSCR-NEXT: s_add_u32 s32, s32, 0x6000
; FLATSCR-NEXT: scratch_store_dword off, v2, s33 ; FLATSCR-NEXT: scratch_store_dword off, v2, s33
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: BB1_1: ; %loadstoreloop ; FLATSCR-NEXT: BB1_1: ; %loadstoreloop
; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1 ; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1
; FLATSCR-NEXT: s_add_u32 vcc_hi, s33, 0x1000 ; FLATSCR-NEXT: s_add_u32 vcc_hi, s33, 0x1000
; FLATSCR-NEXT: s_add_u32 s1, vcc_hi, s0 ; FLATSCR-NEXT: s_add_u32 s1, vcc_hi, s0
; FLATSCR-NEXT: s_add_i32 s0, s0, 1 ; FLATSCR-NEXT: s_add_i32 s0, s0, 1
; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2120 ; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2120
; FLATSCR-NEXT: scratch_store_byte off, v2, s1 ; FLATSCR-NEXT: scratch_store_byte off, v2, s1
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_cbranch_scc1 BB1_1 ; FLATSCR-NEXT: s_cbranch_scc1 BB1_1
; FLATSCR-NEXT: ; %bb.2: ; %split ; FLATSCR-NEXT: ; %bb.2: ; %split
; FLATSCR-NEXT: s_movk_i32 s0, 0x2000 ; FLATSCR-NEXT: s_movk_i32 s0, 0x2000
; FLATSCR-NEXT: s_add_u32 s1, s33, 0x1000 ; FLATSCR-NEXT: s_add_u32 s1, s33, 0x1000
; FLATSCR-NEXT: s_add_u32 s0, s1, s0 ; FLATSCR-NEXT: s_add_u32 s0, s1, s0
; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s0 offset:208 ; FLATSCR-NEXT: scratch_load_dwordx2 v[2:3], off, s0 offset:208 glc
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_add_u32 s0, s33, 0x1000 ; FLATSCR-NEXT: s_add_u32 s0, s33, 0x1000
; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s0 offset:64 ; FLATSCR-NEXT: scratch_load_dwordx2 v[4:5], off, s0 offset:64 glc
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_sub_u32 s32, s32, 0x6000 ; FLATSCR-NEXT: s_sub_u32 s32, s32, 0x6000
; FLATSCR-NEXT: s_mov_b32 s33, s2 ; FLATSCR-NEXT: s_mov_b32 s33, s2
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4 ; FLATSCR-NEXT: v_add_co_u32_e32 v2, vcc, v2, v4
; FLATSCR-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc ; FLATSCR-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v5, vcc
; FLATSCR-NEXT: global_store_dwordx2 v[0:1], v[2:3], off ; FLATSCR-NEXT: global_store_dwordx2 v[0:1], v[2:3], off
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_setpc_b64 s[30:31] ; FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%pin.low = alloca i32, align 8192, addrspace(5) %pin.low = alloca i32, align 8192, addrspace(5)
%local.area = alloca [1060 x i64], align 4096, addrspace(5) %local.area = alloca [1060 x i64], align 4096, addrspace(5)
Show All 15 Lines

llvm/test/CodeGen/AMDGPU/mad-combine.ll

Show All 11 Lines
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare float @llvm.fabs.f32(float) #0 declare float @llvm.fabs.f32(float) #0
declare float @llvm.fma.f32(float, float, float) #0 declare float @llvm.fma.f32(float, float, float) #0
declare float @llvm.fmuladd.f32(float, float, float) #0 declare float @llvm.fmuladd.f32(float, float, float) #0
; (fadd (fmul x, y), z) -> (fma x, y, z) ; (fadd (fmul x, y), z) -> (fma x, y, z)
; FUNC-LABEL: {{^}}combine_to_mad_f32_0: ; FUNC-LABEL: {{^}}combine_to_mad_f32_0:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-STD: v_mac_f32_e32 [[C]], [[A]], [[B]] ; SI-STD: v_mac_f32_e32 [[C]], [[A]], [[B]]
; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]] ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
; SI-DENORM-SLOWFMAF-NOT: v_fma ; SI-DENORM-SLOWFMAF-NOT: v_fma
; SI-DENORM-SLOWFMAF-NOT: v_mad ; SI-DENORM-SLOWFMAF-NOT: v_mad
Show All 16 Linesdefine amdgpu_kernel void @combine_to_mad_f32_0(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
%mul = fmul float %a, %b %mul = fmul float %a, %b
%fma = fadd float %mul, %c %fma = fadd float %mul, %c
store float %fma, float addrspace(1)* %gep.out store float %fma, float addrspace(1)* %gep.out
ret void ret void
} }
; (fadd (fmul x, y), z) -> (fma x, y, z) ; (fadd (fmul x, y), z) -> (fma x, y, z)
; FUNC-LABEL: {{^}}combine_to_mad_f32_0_2use: ; FUNC-LABEL: {{^}}combine_to_mad_f32_0_2use:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12 glc{{$}}
; SI-STD-DAG: v_mac_f32_e32 [[C]], [[A]], [[B]] ; SI-STD-DAG: v_mac_f32_e32 [[C]], [[A]], [[B]]
; SI-STD-DAG: v_mac_f32_e32 [[D]], [[A]], [[B]] ; SI-STD-DAG: v_mac_f32_e32 [[D]], [[A]], [[B]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], [[C]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], [[C]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], [[D]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], [[D]]
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]] ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
Show All 25 Linesdefine amdgpu_kernel void @combine_to_mad_f32_0_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
store volatile float %fma0, float addrspace(1)* %gep.out.0 store volatile float %fma0, float addrspace(1)* %gep.out.0
store volatile float %fma1, float addrspace(1)* %gep.out.1 store volatile float %fma1, float addrspace(1)* %gep.out.1
ret void ret void
} }
; (fadd x, (fmul y, z)) -> (fma y, z, x) ; (fadd x, (fmul y, z)) -> (fma y, z, x)
; FUNC-LABEL: {{^}}combine_to_mad_f32_1: ; FUNC-LABEL: {{^}}combine_to_mad_f32_1:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-STD: v_mac_f32_e32 [[C]], [[A]], [[B]] ; SI-STD: v_mac_f32_e32 [[C]], [[A]], [[B]]
; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]] ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], [[C]]
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]] ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]] ; SI-DENORM-SLOWFMAF: v_add_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
; SI-DENORM: buffer_store_dword [[RESULT]] ; SI-DENORM: buffer_store_dword [[RESULT]]
Show All 12 Linesdefine amdgpu_kernel void @combine_to_mad_f32_1(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
%mul = fmul float %a, %b %mul = fmul float %a, %b
%fma = fadd float %c, %mul %fma = fadd float %c, %mul
store float %fma, float addrspace(1)* %gep.out store float %fma, float addrspace(1)* %gep.out
ret void ret void
} }
; (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) ; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32: ; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]] ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]] ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], [[A]], [[B]], -[[C]]
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]] ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]] ; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
; SI: buffer_store_dword [[RESULT]] ; SI: buffer_store_dword [[RESULT]]
Show All 11 Linesdefine amdgpu_kernel void @combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
%mul = fmul float %a, %b %mul = fmul float %a, %b
%fma = fsub float %mul, %c %fma = fsub float %mul, %c
store float %fma, float addrspace(1)* %gep.out store float %fma, float addrspace(1)* %gep.out
ret void ret void
} }
; (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) ; (fsub (fmul x, y), z) -> (fma x, y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32_2use: ; FUNC-LABEL: {{^}}combine_to_mad_fsub_0_f32_2use:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12 glc{{$}}
; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]] ; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]]
; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]] ; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[A]], [[B]], -[[C]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]] ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
Show All 22 Linesdefine amdgpu_kernel void @combine_to_mad_fsub_0_f32_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
%fma1 = fsub float %mul, %d %fma1 = fsub float %mul, %d
store volatile float %fma0, float addrspace(1)* %gep.out.0 store volatile float %fma0, float addrspace(1)* %gep.out.0
store volatile float %fma1, float addrspace(1)* %gep.out.1 store volatile float %fma1, float addrspace(1)* %gep.out.1
ret void ret void
} }
; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) ; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32: ; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]] ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]]
; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]] ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], [[C]]
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]] ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]] ; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[TMP]]
; SI: buffer_store_dword [[RESULT]] ; SI: buffer_store_dword [[RESULT]]
Show All 11 Linesdefine amdgpu_kernel void @combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
%mul = fmul float %a, %b %mul = fmul float %a, %b
%fma = fsub float %c, %mul %fma = fsub float %c, %mul
store float %fma, float addrspace(1)* %gep.out store float %fma, float addrspace(1)* %gep.out
ret void ret void
} }
; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) ; (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32_2use: ; FUNC-LABEL: {{^}}combine_to_mad_fsub_1_f32_2use:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12 glc{{$}}
; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]] ; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]]
; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]] ; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], [[C]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], [[D]]
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]] ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
Show All 22 Linesdefine amdgpu_kernel void @combine_to_mad_fsub_1_f32_2use(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
%fma1 = fsub float %d, %mul %fma1 = fsub float %d, %mul
store volatile float %fma0, float addrspace(1)* %gep.out.0 store volatile float %fma0, float addrspace(1)* %gep.out.0
store volatile float %fma1, float addrspace(1)* %gep.out.1 store volatile float %fma1, float addrspace(1)* %gep.out.1
ret void ret void
} }
; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z)) ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32: ; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], -[[B]], -[[C]] ; SI-STD: v_mad_f32 [[RESULT:v[0-9]+]], [[A]], -[[B]], -[[C]]
; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], -[[C]] ; SI-DENORM-FASTFMAF: v_fma_f32 [[RESULT:v[0-9]+]], -[[A]], [[B]], -[[C]]
; SI-DENORM-SLOWFMAF: v_mul_f32_e64 [[TMP:v[0-9]+]], [[A]], -[[B]] ; SI-DENORM-SLOWFMAF: v_mul_f32_e64 [[TMP:v[0-9]+]], [[A]], -[[B]]
; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]] ; SI-DENORM-SLOWFMAF: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP]], [[C]]
Show All 14 Linesdefine amdgpu_kernel void @combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
%fma = fsub float %mul.neg, %c %fma = fsub float %mul.neg, %c
store float %fma, float addrspace(1)* %gep.out store float %fma, float addrspace(1)* %gep.out
ret void ret void
} }
; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z)) ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_neg: ; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_neg:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12 glc{{$}}
; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], -[[B]], -[[C]] ; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], [[A]], -[[B]], -[[C]]
; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], -[[B]], -[[D]] ; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], -[[B]], -[[D]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], -[[D]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], -[[A]], [[B]], -[[D]]
; SI-DENORM-SLOWFMAF: v_mul_f32_e64 [[TMP:v[0-9]+]], [[A]], -[[B]] ; SI-DENORM-SLOWFMAF: v_mul_f32_e64 [[TMP:v[0-9]+]], [[A]], -[[B]]
Show All 24 Linesdefine amdgpu_kernel void @combine_to_mad_fsub_2_f32_2uses_neg(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
store volatile float %fma0, float addrspace(1)* %gep.out.0 store volatile float %fma0, float addrspace(1)* %gep.out.0
store volatile float %fma1, float addrspace(1)* %gep.out.1 store volatile float %fma1, float addrspace(1)* %gep.out.1
ret void ret void
} }
; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z)) ; (fsub (fneg (fmul x, y)), z) -> (fma (fneg x), y, (fneg z))
; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_mul: ; FUNC-LABEL: {{^}}combine_to_mad_fsub_2_f32_2uses_mul:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12 glc{{$}}
; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]] ; SI-STD-DAG: v_mad_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]] ; SI-STD-DAG: v_mad_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], -[[A]], [[B]], -[[C]]
; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]] ; SI-DENORM-FASTFMAF-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[A]], [[B]], -[[D]]
; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]] ; SI-DENORM-SLOWFMAF: v_mul_f32_e32 [[TMP:v[0-9]+]], [[A]], [[B]]
Show All 25 Linesdefine amdgpu_kernel void @combine_to_mad_fsub_2_f32_2uses_mul(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
store volatile float %fma0, float addrspace(1)* %gep.out.0 store volatile float %fma0, float addrspace(1)* %gep.out.0
store volatile float %fma1, float addrspace(1)* %gep.out.1 store volatile float %fma1, float addrspace(1)* %gep.out.1
ret void ret void
} }
; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z))) ; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_0_f32: ; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_0_f32:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12 glc{{$}}
; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-STD: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]] ; SI-STD: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]] ; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
; SI-STD: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[C]] ; SI-STD: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[C]]
; SI-DENORM: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]] ; SI-DENORM: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
; SI-DENORM: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]] ; SI-DENORM: v_fma_f32 [[TMP1:v[0-9]+]], [[A]], [[B]], [[TMP0]]
; SI-DENORM: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[C]] ; SI-DENORM: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP1]], [[C]]
Show All 21 Linesdefine amdgpu_kernel void @aggressive_combine_to_mad_fsub_0_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
store float %tmp2, float addrspace(1)* %gep.out store float %tmp2, float addrspace(1)* %gep.out
ret void ret void
} }
; fold (fsub x, (fma y, z, (fmul u, v))) ; fold (fsub x, (fma y, z, (fmul u, v)))
; -> (fma (fneg y), z, (fma (fneg u), v, x)) ; -> (fma (fneg y), z, (fma (fneg u), v, x))
; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_1_f32: ; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_1_f32:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12 glc{{$}}
; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-STD: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]] ; SI-STD: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]] ; SI-STD: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
; SI-STD: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP1]] ; SI-STD: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP1]]
; SI-DENORM: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]] ; SI-DENORM: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
; SI-DENORM: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]] ; SI-DENORM: v_fma_f32 [[TMP1:v[0-9]+]], [[B]], [[C]], [[TMP0]]
; SI-DENORM: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP1]] ; SI-DENORM: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP1]]
Show All 21 Linesdefine amdgpu_kernel void @aggressive_combine_to_mad_fsub_1_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
store float %tmp2, float addrspace(1)* %gep.out store float %tmp2, float addrspace(1)* %gep.out
ret void ret void
} }
; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z))) ; fold (fsub (fma x, y, (fmul u, v)), z) -> (fma x, y (fma u, v, (fneg z)))
; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_2_f32: ; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_2_f32:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12 glc{{$}}
; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-STD-SAFE: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]] ; SI-STD-SAFE: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
; SI-STD-SAFE: v_mac_f32_e32 [[TMP0]], [[A]], [[B]] ; SI-STD-SAFE: v_mac_f32_e32 [[TMP0]], [[A]], [[B]]
; SI-STD-SAFE: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP0]], [[C]] ; SI-STD-SAFE: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[TMP0]], [[C]]
; SI-STD-UNSAFE: v_mad_f32 [[RESULT:v[0-9]+]], [[D]], [[E]], -[[C]] ; SI-STD-UNSAFE: v_mad_f32 [[RESULT:v[0-9]+]], [[D]], [[E]], -[[C]]
; SI-STD-UNSAFE: v_mac_f32_e32 [[RESULT]], [[A]], [[B]] ; SI-STD-UNSAFE: v_mac_f32_e32 [[RESULT]], [[A]], [[B]]
Show All 30 Linesdefine amdgpu_kernel void @aggressive_combine_to_mad_fsub_2_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #1 {
store float %tmp2, float addrspace(1)* %gep.out store float %tmp2, float addrspace(1)* %gep.out
ret void ret void
} }
; fold (fsub x, (fmuladd y, z, (fmul u, v))) ; fold (fsub x, (fmuladd y, z, (fmul u, v)))
; -> (fmuladd (fneg y), z, (fmuladd (fneg u), v, x)) ; -> (fmuladd (fneg y), z, (fmuladd (fneg u), v, x))
; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_3_f32: ; FUNC-LABEL: {{^}}aggressive_combine_to_mad_fsub_3_f32:
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}} ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 glc{{$}}
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}} ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 glc{{$}}
; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12{{$}} ; SI-DAG: buffer_load_dword [[D:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:12 glc{{$}}
; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; SI-DAG: buffer_load_dword [[E:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16 glc{{$}}
; SI-STD-SAFE: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]] ; SI-STD-SAFE: v_mul_f32_e32 [[TMP0:v[0-9]+]], [[D]], [[E]]
; SI-STD-SAFE: v_mac_f32_e32 [[TMP0]], [[B]], [[C]] ; SI-STD-SAFE: v_mac_f32_e32 [[TMP0]], [[B]], [[C]]
; SI-STD-SAFE: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP0]] ; SI-STD-SAFE: v_sub_f32_e32 [[RESULT:v[0-9]+]], [[A]], [[TMP0]]
; SI-STD-UNSAFE: v_mad_f32 [[TMP:v[0-9]+]], -[[D]], [[E]], [[A]] ; SI-STD-UNSAFE: v_mad_f32 [[TMP:v[0-9]+]], -[[D]], [[E]], [[A]]
; SI-STD-UNSAFE: v_mad_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP]] ; SI-STD-UNSAFE: v_mad_f32 [[RESULT:v[0-9]+]], -[[B]], [[C]], [[TMP]]
Show All 37 Lines

llvm/test/CodeGen/AMDGPU/mad-mix-hi.ll

Show First 20 Lines • Show All 114 Lines • ▼ Show 20 Linesdefine <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt(half %src0, half %src1, half %src2) #0 {
ret <2 x half> %vec.result ret <2 x half> %vec.result
} }
; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use: ; GCN-LABEL: {{^}}v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]{{$}} ; GFX9-NEXT: v_mad_mixlo_f16 v3, v0, v1, v2 op_sel_hi:[1,1,1]{{$}}
; GFX9-NEXT: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v3 ; GFX9-NEXT: global_store_short v{{\[[0-9]+:[0-9]+\]}}, v3
; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use(half %src0, half %src1, half %src2) #0 { define <2 x half> @v_mad_mixhi_f16_f16lo_f16lo_f16lo_undeflo_clamp_postcvt_multi_use(half %src0, half %src1, half %src2) #0 {
%src0.ext = fpext half %src0 to float %src0.ext = fpext half %src0 to float
%src1.ext = fpext half %src1 to float %src1.ext = fpext half %src1 to float
%src2.ext = fpext half %src2 to float %src2.ext = fpext half %src2 to float
%result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext) %result = tail call float @llvm.fmuladd.f32(float %src0.ext, float %src1.ext, float %src2.ext)
%cvt.result = fptrunc float %result to half %cvt.result = fptrunc float %result to half
store volatile half %cvt.result, half addrspace(1)* undef store volatile half %cvt.result, half addrspace(1)* undef
Show All 15 Lines

llvm/test/CodeGen/AMDGPU/madak.ll

Show All 35 Lines
; Make sure this is only folded with one use. This is a code size ; Make sure this is only folded with one use. This is a code size
; optimization and if we fold the immediate multiple times, we'll undo ; optimization and if we fold the immediate multiple times, we'll undo
; it. ; it.
; GCN-LABEL: {{^}}madak_2_use_f32: ; GCN-LABEL: {{^}}madak_2_use_f32:
; GFX9: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 ; GFX9: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
; GFX10: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 ; GFX10: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
; GFX6-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GFX6-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; GFX6-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GFX6-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GFX6-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 ; GFX6-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
; GFX8_9_10: {{flat|global}}_load_dword [[VA:v[0-9]+]], ; GFX8_9_10: {{flat|global}}_load_dword [[VA:v[0-9]+]],
; GFX8_9_10: {{flat|global}}_load_dword [[VB:v[0-9]+]], ; GFX8_9_10: {{flat|global}}_load_dword [[VB:v[0-9]+]],
; GFX8_9_10: {{flat|global}}_load_dword [[VC:v[0-9]+]], ; GFX8_9_10: {{flat|global}}_load_dword [[VC:v[0-9]+]],
; GFX6-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 ; GFX6-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
; GFX8-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000 ; GFX8-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x41200000
; GFX6_8_9-DAG: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000 ; GFX6_8_9-DAG: v_madak_f32 {{v[0-9]+}}, [[VA]], [[VB]], 0x41200000
▲ Show 20 Lines • Show All 218 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/madmk.ll

; RUN: llc -march=amdgcn -mattr=+mad-mac-f32-insts -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mattr=+mad-mac-f32-insts -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; XUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; FIXME: None of these trigger madmk emission anymore. It is still ; FIXME: None of these trigger madmk emission anymore. It is still
; possible, but requires the correct registers to be used which is ; possible, but requires the correct registers to be used which is
; hard to trigger. ; hard to trigger.
declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
declare float @llvm.fabs.f32(float) nounwind readnone declare float @llvm.fabs.f32(float) nounwind readnone
; GCN-LABEL: {{^}}madmk_f32: ; GCN-LABEL: {{^}}madmk_f32:
; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GCN: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]] ; GCN: v_mac_f32_e32 [[VB]], 0x41200000, [[VA]]
define amdgpu_kernel void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { define amdgpu_kernel void @madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
%a = load volatile float, float addrspace(1)* %gep.0, align 4 %a = load volatile float, float addrspace(1)* %gep.0, align 4
%b = load volatile float, float addrspace(1)* %gep.1, align 4 %b = load volatile float, float addrspace(1)* %gep.1, align 4
%mul = fmul float %a, 10.0 %mul = fmul float %a, 10.0
%madmk = fadd float %mul, %b %madmk = fadd float %mul, %b
store float %madmk, float addrspace(1)* %out.gep, align 4 store float %madmk, float addrspace(1)* %out.gep, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}madmk_2_use_f32: ; GCN-LABEL: {{^}}madmk_2_use_f32:
; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 ; GCN-DAG: buffer_load_dword [[VC:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000 ; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000
; GCN-DAG: v_mac_f32_e32 [[VB]], [[SK]], [[VA]] ; GCN-DAG: v_mac_f32_e32 [[VB]], [[SK]], [[VA]]
; GCN-DAG: v_mac_f32_e32 [[VC]], [[SK]], [[VA]] ; GCN-DAG: v_mac_f32_e32 [[VC]], [[SK]], [[VA]]
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { define amdgpu_kernel void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
Show All 16 Linesdefine amdgpu_kernel void @madmk_2_use_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 {
store float %madmk0, float addrspace(1)* %out.gep.0, align 4 store float %madmk0, float addrspace(1)* %out.gep.0, align 4
store float %madmk1, float addrspace(1)* %out.gep.1, align 4 store float %madmk1, float addrspace(1)* %out.gep.1, align 4
ret void ret void
} }
; We don't get any benefit if the constant is an inline immediate. ; We don't get any benefit if the constant is an inline immediate.
; GCN-LABEL: {{^}}madmk_inline_imm_f32: ; GCN-LABEL: {{^}}madmk_inline_imm_f32:
; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GCN: v_mac_f32_e32 [[VB]], 4.0, [[VA]] ; GCN: v_mac_f32_e32 [[VB]], 4.0, [[VA]]
define amdgpu_kernel void @madmk_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { define amdgpu_kernel void @madmk_inline_imm_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @scalar_vector_madmk_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in, float %a) #0 {
%mul = fmul float %a, 10.0 %mul = fmul float %a, 10.0
%madmk = fadd float %mul, %b %madmk = fadd float %mul, %b
store float %madmk, float addrspace(1)* %out.gep, align 4 store float %madmk, float addrspace(1)* %out.gep, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}no_madmk_src0_modifier_f32: ; GCN-LABEL: {{^}}no_madmk_src0_modifier_f32:
; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000 ; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x41200000
; GCN: v_mad_f32 {{v[0-9]+}}, |[[VA]]|, [[SK]], [[VB]] ; GCN: v_mad_f32 {{v[0-9]+}}, |[[VA]]|, [[SK]], [[VB]]
define amdgpu_kernel void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { define amdgpu_kernel void @no_madmk_src0_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
%a = load volatile float, float addrspace(1)* %gep.0, align 4 %a = load volatile float, float addrspace(1)* %gep.0, align 4
%b = load volatile float, float addrspace(1)* %gep.1, align 4 %b = load volatile float, float addrspace(1)* %gep.1, align 4
%a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone %a.fabs = call float @llvm.fabs.f32(float %a) nounwind readnone
%mul = fmul float %a.fabs, 10.0 %mul = fmul float %a.fabs, 10.0
%madmk = fadd float %mul, %b %madmk = fadd float %mul, %b
store float %madmk, float addrspace(1)* %out.gep, align 4 store float %madmk, float addrspace(1)* %out.gep, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}no_madmk_src2_modifier_f32: ; GCN-LABEL: {{^}}no_madmk_src2_modifier_f32:
; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; GCN-DAG: buffer_load_dword [[VA:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; GCN-DAG: buffer_load_dword [[VB:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{[sv][0-9]+}}, |{{v[0-9]+}}| ; GCN: v_mad_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{[sv][0-9]+}}, |{{v[0-9]+}}|
define amdgpu_kernel void @no_madmk_src2_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 { define amdgpu_kernel void @no_madmk_src2_modifier_f32(float addrspace(1)* noalias %out, float addrspace(1)* noalias %in) #0 {
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone %tid = tail call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
%gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid %gep.0 = getelementptr float, float addrspace(1)* %in, i32 %tid
%gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1 %gep.1 = getelementptr float, float addrspace(1)* %gep.0, i32 1
%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid %out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/memory-legalizer-flat-volatile.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 -amdgcn-skip-cache-invalidations -verify-machineinstrs < %s | FileCheck --check-prefixes=SKIP-CACHE-INV %s
define amdgpu_kernel void @flat_nontemporal_load_0(
; GFX7-LABEL: flat_nontemporal_load_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dword v0, v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: flat_store_dword v[2:3], v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: flat_nontemporal_load_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1] glc dlc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s3
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: flat_store_dword v[0:1], v2
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: flat_nontemporal_load_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] glc dlc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s3
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: flat_store_dword v[0:1], v2
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: flat_nontemporal_load_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: flat_load_dword v0, v[0:1] glc
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v3, s3
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: flat_store_dword v[2:3], v0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32* %in, i32* %out) {
entry:
%val = load volatile i32, i32* %in, align 4
store i32 %val, i32* %out
ret void
}
define amdgpu_kernel void @flat_nontemporal_load_1(
; GFX7-LABEL: flat_nontemporal_load_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s0, v2
; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX7-NEXT: flat_load_dword v2, v[2:3] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: flat_nontemporal_load_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_add_co_u32_e64 v0, s0, s0, v0
; GFX10-WGP-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1] glc dlc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s3
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: flat_store_dword v[0:1], v2
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: flat_nontemporal_load_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_add_co_u32_e64 v0, s0, s0, v0
; GFX10-CU-NEXT: v_add_co_ci_u32_e64 v1, s0, s1, 0, s0
; GFX10-CU-NEXT: flat_load_dword v2, v[0:1] glc dlc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s3
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: flat_store_dword v[0:1], v2
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: flat_nontemporal_load_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v3, s1
; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v2, vcc, s0, v2
; SKIP-CACHE-INV-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; SKIP-CACHE-INV-NEXT: flat_load_dword v2, v[2:3] glc
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s3
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: flat_store_dword v[0:1], v2
; SKIP-CACHE-INV-NEXT: s_endpgm
i32* %in, i32* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32* %in, i32 %tid
%val = load volatile i32, i32* %val.gep, align 4
store i32 %val, i32* %out
ret void
}
define amdgpu_kernel void @flat_nontemporal_store_0(
; GFX7-LABEL: flat_nontemporal_store_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: flat_store_dword v[2:3], v0
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: flat_nontemporal_store_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1]
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s3
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: flat_store_dword v[0:1], v2
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: flat_nontemporal_store_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: flat_load_dword v2, v[0:1]
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s3
; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-CU-NEXT: flat_store_dword v[0:1], v2
; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: flat_nontemporal_store_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: flat_load_dword v0, v[0:1]
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v3, s3
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: flat_store_dword v[2:3], v0
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: s_endpgm
i32* %in, i32* %out) {
entry:
%val = load i32, i32* %in, align 4
store volatile i32 %val, i32* %out
ret void
}
define amdgpu_kernel void @flat_nontemporal_store_1(
; GFX7-LABEL: flat_nontemporal_store_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: v_mov_b32_e32 v2, s1
; GFX7-NEXT: flat_load_dword v2, v[1:2]
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX7-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: flat_nontemporal_store_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s1
; GFX10-WGP-NEXT: v_add_co_u32_e64 v0, s0, s2, v0
; GFX10-WGP-NEXT: flat_load_dword v2, v[1:2]
; GFX10-WGP-NEXT: v_add_co_ci_u32_e64 v1, s0, s3, 0, s0
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: flat_store_dword v[0:1], v2
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: flat_nontemporal_store_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s1
; GFX10-CU-NEXT: v_add_co_u32_e64 v0, s0, s2, v0
; GFX10-CU-NEXT: flat_load_dword v2, v[1:2]
; GFX10-CU-NEXT: v_add_co_ci_u32_e64 v1, s0, s3, 0, s0
; GFX10-CU-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-CU-NEXT: flat_store_dword v[0:1], v2
; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: flat_nontemporal_store_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s1
; SKIP-CACHE-INV-NEXT: flat_load_dword v2, v[1:2]
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s3
; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; SKIP-CACHE-INV-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: flat_store_dword v[0:1], v2
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: s_endpgm
i32* %in, i32* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32* %in, align 4
%out.gep = getelementptr inbounds i32, i32* %out, i32 %tid
store volatile i32 %val, i32* %out.gep
ret void
}
define amdgpu_kernel void @flat_volatile_workgroup_acquire_load(
; GFX7-LABEL: flat_volatile_workgroup_acquire_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: flat_store_dword v[2:3], v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: flat_volatile_workgroup_acquire_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: flat_load_dword v2, v[0:1] glc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s3
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: flat_store_dword v[0:1], v2
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: flat_volatile_workgroup_acquire_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: flat_load_dword v2, v[0:1]
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s3
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: flat_store_dword v[0:1], v2
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: flat_volatile_workgroup_acquire_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: flat_load_dword v0, v[0:1]
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v3, s3
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: flat_store_dword v[2:3], v0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32* %in, i32* %out) {
entry:
%val = load atomic volatile i32, i32* %in syncscope("workgroup") acquire, align 4
store i32 %val, i32* %out
ret void
}
define amdgpu_kernel void @flat_volatile_workgroup_release_store(
; GFX7-LABEL: flat_volatile_workgroup_release_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: flat_volatile_workgroup_release_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v2, s2
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: flat_store_dword v[0:1], v2
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: flat_volatile_workgroup_release_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v2, s2
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: flat_store_dword v[0:1], v2
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: flat_volatile_workgroup_release_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dword s2, s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s2
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: flat_store_dword v[0:1], v2
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 %in, i32* %out) {
entry:
store atomic volatile i32 %in, i32* %out syncscope("workgroup") release, align 4
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x()

llvm/test/CodeGen/AMDGPU/memory-legalizer-global-volatile.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 -amdgcn-skip-cache-invalidations -verify-machineinstrs < %s | FileCheck --check-prefixes=SKIP-CACHE-INV %s
define amdgpu_kernel void @global_volatile_load_0(
; GFX6-LABEL: global_volatile_load_0:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s0, s4
; GFX6-NEXT: s_mov_b32 s1, s5
; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b32 s4, s6
; GFX6-NEXT: s_mov_b32 s5, s7
; GFX6-NEXT: s_mov_b32 s6, s2
; GFX6-NEXT: s_mov_b32 s7, s3
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: global_volatile_load_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dword v0, v[0:1] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
; GFX7-NEXT: flat_store_dword v[2:3], v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: global_volatile_load_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: global_load_dword v1, v0, s[0:1] glc dlc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v0, v1, s[2:3]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: global_volatile_load_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: global_load_dword v1, v0, s[0:1] glc dlc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v0, v1, s[2:3]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: global_volatile_load_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_mov_b32 s0, s4
; SKIP-CACHE-INV-NEXT: s_mov_b32 s1, s5
; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: s_mov_b32 s4, s6
; SKIP-CACHE-INV-NEXT: s_mov_b32 s5, s7
; SKIP-CACHE-INV-NEXT: s_mov_b32 s6, s2
; SKIP-CACHE-INV-NEXT: s_mov_b32 s7, s3
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry:
%val = load volatile i32, i32 addrspace(1)* %in, align 4
store i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @global_volatile_load_1(
; GFX6-LABEL: global_volatile_load_1:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s0, s6
; GFX6-NEXT: s_mov_b32 s1, s7
; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: s_mov_b32 s7, s3
; GFX6-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: global_volatile_load_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v3, s1
; GFX7-NEXT: v_add_i32_e32 v2, vcc, s0, v2
; GFX7-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX7-NEXT: flat_load_dword v2, v[2:3] glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: global_volatile_load_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: global_load_dword v0, v0, s[0:1] glc dlc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[2:3]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: global_volatile_load_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: global_load_dword v0, v0, s[0:1] glc dlc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[2:3]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: global_volatile_load_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, 0
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_mov_b32 s0, s6
; SKIP-CACHE-INV-NEXT: s_mov_b32 s1, s7
; SKIP-CACHE-INV-NEXT: s_mov_b32 s6, 0
; SKIP-CACHE-INV-NEXT: s_mov_b32 s7, s3
; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v[0:1], s[4:7], 0 addr64 glc
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
%val = load volatile i32, i32 addrspace(1)* %val.gep, align 4
store i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @global_volatile_store_0(
; GFX6-LABEL: global_volatile_store_0:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX6-NEXT: s_mov_b32 s4, s2
; GFX6-NEXT: s_mov_b32 s5, s3
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: global_volatile_store_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: global_volatile_store_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: global_store_dword v0, v1, s[2:3]
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: global_volatile_store_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: global_store_dword v0, v1, s[2:3]
; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: global_volatile_store_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 s7, 0xf000
; SKIP-CACHE-INV-NEXT: s_mov_b32 s6, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0x0
; SKIP-CACHE-INV-NEXT: s_mov_b32 s4, s2
; SKIP-CACHE-INV-NEXT: s_mov_b32 s5, s3
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry:
%val = load i32, i32 addrspace(1)* %in, align 4
store volatile i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @global_volatile_store_1(
; GFX6-LABEL: global_volatile_store_1:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s7, 0xf000
; GFX6-NEXT: s_mov_b32 s6, 0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX6-NEXT: v_mov_b32_e32 v1, 0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX6-NEXT: s_mov_b64 s[4:5], s[2:3]
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: global_volatile_store_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX7-NEXT: v_mov_b32_e32 v1, s3
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, s0
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: global_volatile_store_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: global_store_dword v0, v1, s[2:3]
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: global_volatile_store_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: global_store_dword v0, v1, s[2:3]
; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: global_volatile_store_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 s7, 0xf000
; SKIP-CACHE-INV-NEXT: s_mov_b32 s6, 0
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, 0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0x0
; SKIP-CACHE-INV-NEXT: s_mov_b64 s[4:5], s[2:3]
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v2, s0
; SKIP-CACHE-INV-NEXT: buffer_store_dword v2, v[0:1], s[4:7], 0 addr64
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
store volatile i32 %val, i32 addrspace(1)* %out.gep
ret void
}
define amdgpu_kernel void @global_volatile_workgroup_acquire_load(
; GFX6-LABEL: global_volatile_workgroup_acquire_load:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_mov_b32 s0, s4
; GFX6-NEXT: s_mov_b32 s1, s5
; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_mov_b32 s4, s6
; GFX6-NEXT: s_mov_b32 s5, s7
; GFX6-NEXT: s_mov_b32 s6, s2
; GFX6-NEXT: s_mov_b32 s7, s3
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: global_volatile_workgroup_acquire_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_load_dword v0, v[0:1]
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v3, s3
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: flat_store_dword v[2:3], v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: global_volatile_workgroup_acquire_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: global_load_dword v1, v0, s[0:1] glc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: global_store_dword v0, v1, s[2:3]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: global_volatile_workgroup_acquire_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: global_load_dword v1, v0, s[0:1]
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v0, v1, s[2:3]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: global_volatile_workgroup_acquire_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_mov_b32 s0, s4
; SKIP-CACHE-INV-NEXT: s_mov_b32 s1, s5
; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, off, s[0:3], 0
; SKIP-CACHE-INV-NEXT: s_mov_b32 s4, s6
; SKIP-CACHE-INV-NEXT: s_mov_b32 s5, s7
; SKIP-CACHE-INV-NEXT: s_mov_b32 s6, s2
; SKIP-CACHE-INV-NEXT: s_mov_b32 s7, s3
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(1)* %out) {
entry:
%val = load atomic volatile i32, i32 addrspace(1)* %in syncscope("workgroup") acquire, align 4
store i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @global_volatile_workgroup_release_store(
; GFX6-LABEL: global_volatile_workgroup_release_store:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: global_volatile_workgroup_release_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v2, s2
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: global_volatile_workgroup_release_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: global_volatile_workgroup_release_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-CU-NEXT: v_mov_b32_e32 v0, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: global_volatile_workgroup_release_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dword s4, s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s4
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 %in, i32 addrspace(1)* %out) {
entry:
store atomic volatile i32 %in, i32 addrspace(1)* %out syncscope("workgroup") release, align 4
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x()

llvm/test/CodeGen/AMDGPU/memory-legalizer-local-volatile.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 -amdgcn-skip-cache-invalidations -verify-machineinstrs < %s | FileCheck --check-prefixes=SKIP-CACHE-INV %s
define amdgpu_kernel void @local_volatile_load_0(
; GFX6-LABEL: local_volatile_load_0:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: ds_read_b32 v0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_volatile_load_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: ds_read_b32 v2, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_volatile_load_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_volatile_load_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_volatile_load_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dword s4, s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s4
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(3)* %in, i32 addrspace(1)* %out) {
entry:
%val = load volatile i32, i32 addrspace(3)* %in, align 4
store i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @local_volatile_load_1(
; GFX6-LABEL: local_volatile_load_1:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: ds_read_b32 v0, v0
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_volatile_load_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: ds_read_b32 v2, v0
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_volatile_load_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_volatile_load_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_volatile_load_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dword s4, s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v0, vcc, s4, v0
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(3)* %in, i32 addrspace(1)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %tid
%val = load volatile i32, i32 addrspace(3)* %val.gep, align 4
store i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @local_volatile_store_0(
; GFX6-LABEL: local_volatile_store_0:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_volatile_store_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x2
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_volatile_store_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_volatile_store_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_volatile_store_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_load_dword s1, s[2:3], 0x0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(3)* %out) {
entry:
%val = load i32, i32 addrspace(1)* %in, align 4
store volatile i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_volatile_store_1(
; GFX6-LABEL: local_volatile_store_1:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_volatile_store_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x2
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_volatile_store_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_volatile_store_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_volatile_store_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_load_dword s1, s[2:3], 0x0
; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(3)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid
store volatile i32 %val, i32 addrspace(3)* %out.gep
ret void
}
define amdgpu_kernel void @local_volatile_workgroup_acquire_load(
; GFX6-LABEL: local_volatile_workgroup_acquire_load:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dword s2, s[0:1], 0x9
; GFX6-NEXT: s_load_dword s0, s[0:1], 0xa
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: ds_read_b32 v0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: ds_write_b32 v1, v0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_volatile_workgroup_acquire_load:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: ds_read_b32 v0, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: ds_write_b32 v1, v0
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_volatile_workgroup_acquire_load:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s1
; GFX10-WGP-NEXT: ds_read_b32 v0, v0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: buffer_gl0_inv
; GFX10-WGP-NEXT: ds_write_b32 v1, v0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_volatile_workgroup_acquire_load:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s1
; GFX10-CU-NEXT: ds_read_b32 v0, v0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v1, v0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_volatile_workgroup_acquire_load:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s0
; SKIP-CACHE-INV-NEXT: ds_read_b32 v0, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: ds_write_b32 v1, v0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(3)* %in, i32 addrspace(3)* %out) {
entry:
%val = load atomic volatile i32, i32 addrspace(3)* %in syncscope("workgroup") acquire, align 4
store i32 %val, i32 addrspace(3)* %out
ret void
}
define amdgpu_kernel void @local_volatile_workgroup_release_store(
; GFX6-LABEL: local_volatile_workgroup_release_store:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_load_dword s2, s[0:1], 0x9
; GFX6-NEXT: s_load_dword s0, s[0:1], 0xa
; GFX6-NEXT: s_mov_b32 m0, -1
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v1, s2
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: ds_write_b32 v0, v1
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: local_volatile_workgroup_release_store:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_mov_b32 m0, -1
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s1
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: ds_write_b32 v0, v1
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: local_volatile_workgroup_release_store:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s1
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: ds_write_b32 v0, v1
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: local_volatile_workgroup_release_store:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s1
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: ds_write_b32 v0, v1
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: local_volatile_workgroup_release_store:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_mov_b32 m0, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: ds_write_b32 v0, v1
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 %in, i32 addrspace(3)* %out) {
entry:
store atomic volatile i32 %in, i32 addrspace(3)* %out syncscope("workgroup") release, align 4
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x()

llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX6 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX7 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-WGP %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -mattr=+cumode -verify-machineinstrs < %s | FileCheck --check-prefixes=GFX10-CU %s
; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx700 -amdgcn-skip-cache-invalidations -verify-machineinstrs < %s | FileCheck --check-prefixes=SKIP-CACHE-INV %s
define amdgpu_kernel void @private_volatile_load_0(
; GFX6-LABEL: private_volatile_load_0:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX6-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: s_mov_b32 s11, 0xe8f000
; GFX6-NEXT: s_add_u32 s8, s8, s3
; GFX6-NEXT: s_addc_u32 s9, s9, 0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: private_volatile_load_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX7-NEXT: s_add_u32 s8, s8, s7
; GFX7-NEXT: s_addc_u32 s9, s9, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s2
; GFX7-NEXT: buffer_load_dword v2, v0, s[8:11], 0 offen glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: private_volatile_load_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s2
; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc dlc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: private_volatile_load_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s2
; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc dlc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: private_volatile_load_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[8:9]
; SKIP-CACHE-INV-NEXT: s_mov_b32 s8, s0
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
; SKIP-CACHE-INV-NEXT: s_load_dword s4, s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_add_u32 s8, s8, s3
; SKIP-CACHE-INV-NEXT: s_addc_u32 s9, s9, 0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s4
; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
entry:
%val = load volatile i32, i32 addrspace(5)* %in, align 4
store i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @private_volatile_load_1(
; GFX6-LABEL: private_volatile_load_1:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GFX6-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GFX6-NEXT: s_load_dword s4, s[0:1], 0x9
; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; GFX6-NEXT: s_mov_b32 s10, -1
; GFX6-NEXT: s_mov_b32 s11, 0xe8f000
; GFX6-NEXT: s_add_u32 s8, s8, s3
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX6-NEXT: s_addc_u32 s9, s9, 0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s4, v0
; GFX6-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_mov_b32 s3, 0xf000
; GFX6-NEXT: s_mov_b32 s2, -1
; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: private_volatile_load_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2
; GFX7-NEXT: s_add_u32 s8, s8, s7
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: s_addc_u32 s9, s9, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: buffer_load_dword v2, v0, s[8:11], 0 offen glc
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: v_mov_b32_e32 v1, s1
; GFX7-NEXT: flat_store_dword v[0:1], v2
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: private_volatile_load_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-WGP-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc dlc
; GFX10-WGP-NEXT: s_waitcnt vmcnt(0)
; GFX10-WGP-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: private_volatile_load_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x8
; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-CU-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc dlc
; GFX10-CU-NEXT: s_waitcnt vmcnt(0)
; GFX10-CU-NEXT: global_store_dword v1, v0, s[0:1]
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: private_volatile_load_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[8:9]
; SKIP-CACHE-INV-NEXT: s_mov_b32 s8, s0
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[8:11], s[8:9], 0x0
; SKIP-CACHE-INV-NEXT: s_load_dword s4, s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SKIP-CACHE-INV-NEXT: s_mov_b32 s2, -1
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_add_u32 s8, s8, s3
; SKIP-CACHE-INV-NEXT: s_addc_u32 s9, s9, 0
; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v0, vcc, s4, v0
; SKIP-CACHE-INV-NEXT: buffer_load_dword v0, v0, s[8:11], 0 offen glc
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: s_mov_b32 s3, 0xf000
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(5)* %in, i32 addrspace(1)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(5)* %in, i32 %tid
%val = load volatile i32, i32 addrspace(5)* %val.gep, align 4
store i32 %val, i32 addrspace(1)* %out
ret void
}
define amdgpu_kernel void @private_volatile_store_0(
; GFX6-LABEL: private_volatile_store_0:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
; GFX6-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_mov_b32 s7, 0xe8f000
; GFX6-NEXT: s_add_u32 s4, s4, s3
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
; GFX6-NEXT: s_addc_u32 s5, s5, 0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v0, s1
; GFX6-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: private_volatile_store_0:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x2
; GFX7-NEXT: s_add_u32 s8, s8, s7
; GFX7-NEXT: s_addc_u32 s9, s9, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX7-NEXT: v_mov_b32_e32 v1, s2
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v0, s0
; GFX7-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: private_volatile_store_0:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s2
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v0, s0
; GFX10-WGP-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: private_volatile_store_0:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s2
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v0, s0
; GFX10-CU-NEXT: buffer_store_dword v0, v1, s[8:11], 0 offen
; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: private_volatile_store_0:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[4:5]
; SKIP-CACHE-INV-NEXT: s_mov_b32 s4, s0
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_add_u32 s4, s4, s3
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_addc_u32 s5, s5, 0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_load_dword s1, s[2:3], 0x0
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v0, s1
; SKIP-CACHE-INV-NEXT: buffer_store_dword v0, v1, s[4:7], 0 offen
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
entry:
%val = load i32, i32 addrspace(1)* %in, align 4
store volatile i32 %val, i32 addrspace(5)* %out
ret void
}
define amdgpu_kernel void @private_volatile_store_1(
; GFX6-LABEL: private_volatile_store_1:
; GFX6: ; %bb.0: ; %entry
; GFX6-NEXT: s_mov_b32 s4, SCRATCH_RSRC_DWORD0
; GFX6-NEXT: s_mov_b32 s5, SCRATCH_RSRC_DWORD1
; GFX6-NEXT: s_mov_b32 s6, -1
; GFX6-NEXT: s_mov_b32 s7, 0xe8f000
; GFX6-NEXT: s_add_u32 s4, s4, s3
; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; GFX6-NEXT: s_load_dword s0, s[0:1], 0xb
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX6-NEXT: s_addc_u32 s5, s5, 0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: s_load_dword s1, s[2:3], 0x0
; GFX6-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_waitcnt lgkmcnt(0)
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: s_endpgm
;
; GFX7-LABEL: private_volatile_store_1:
; GFX7: ; %bb.0: ; %entry
; GFX7-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX7-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX7-NEXT: s_load_dword s2, s[4:5], 0x2
; GFX7-NEXT: s_add_u32 s8, s8, s7
; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX7-NEXT: s_addc_u32 s9, s9, 0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX7-NEXT: v_add_i32_e32 v0, vcc, s2, v0
; GFX7-NEXT: s_waitcnt lgkmcnt(0)
; GFX7-NEXT: v_mov_b32_e32 v1, s0
; GFX7-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen
; GFX7-NEXT: s_waitcnt vmcnt(0)
; GFX7-NEXT: s_endpgm
;
; GFX10-WGP-LABEL: private_volatile_store_1:
; GFX10-WGP: ; %bb.0: ; %entry
; GFX10-WGP-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-WGP-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-WGP-NEXT: s_clause 0x1
; GFX10-WGP-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-WGP-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-WGP-NEXT: s_add_u32 s8, s8, s7
; GFX10-WGP-NEXT: s_addc_u32 s9, s9, 0
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-WGP-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-WGP-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-WGP-NEXT: v_mov_b32_e32 v1, s0
; GFX10-WGP-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen
; GFX10-WGP-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-WGP-NEXT: s_endpgm
;
; GFX10-CU-LABEL: private_volatile_store_1:
; GFX10-CU: ; %bb.0: ; %entry
; GFX10-CU-NEXT: s_mov_b64 s[10:11], s[2:3]
; GFX10-CU-NEXT: s_mov_b64 s[8:9], s[0:1]
; GFX10-CU-NEXT: s_clause 0x1
; GFX10-CU-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX10-CU-NEXT: s_load_dword s2, s[4:5], 0x8
; GFX10-CU-NEXT: s_add_u32 s8, s8, s7
; GFX10-CU-NEXT: s_addc_u32 s9, s9, 0
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: s_load_dword s0, s[0:1], 0x0
; GFX10-CU-NEXT: v_lshl_add_u32 v0, v0, 2, s2
; GFX10-CU-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-CU-NEXT: v_mov_b32_e32 v1, s0
; GFX10-CU-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen
; GFX10-CU-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-CU-NEXT: s_endpgm
;
; SKIP-CACHE-INV-LABEL: private_volatile_store_1:
; SKIP-CACHE-INV: ; %bb.0: ; %entry
; SKIP-CACHE-INV-NEXT: s_getpc_b64 s[4:5]
; SKIP-CACHE-INV-NEXT: s_mov_b32 s4, s0
; SKIP-CACHE-INV-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x0
; SKIP-CACHE-INV-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_add_u32 s4, s4, s3
; SKIP-CACHE-INV-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x9
; SKIP-CACHE-INV-NEXT: s_load_dword s0, s[0:1], 0xb
; SKIP-CACHE-INV-NEXT: s_addc_u32 s5, s5, 0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: s_load_dword s1, s[2:3], 0x0
; SKIP-CACHE-INV-NEXT: v_add_i32_e32 v0, vcc, s0, v0
; SKIP-CACHE-INV-NEXT: s_waitcnt lgkmcnt(0)
; SKIP-CACHE-INV-NEXT: v_mov_b32_e32 v1, s1
; SKIP-CACHE-INV-NEXT: buffer_store_dword v1, v0, s[4:7], 0 offen
; SKIP-CACHE-INV-NEXT: s_waitcnt vmcnt(0)
; SKIP-CACHE-INV-NEXT: s_endpgm
i32 addrspace(1)* %in, i32 addrspace(5)* %out) {
entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(1)* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(5)* %out, i32 %tid
store volatile i32 %val, i32 addrspace(5)* %out.gep
ret void
}
declare i32 @llvm.amdgcn.workitem.id.x()

llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll

Show First 20 Lines • Show All 148 Lines • ▼ Show 20 Lines
define void @slsr1_0(i32 %b.arg, i32 %s.arg) #0 { define void @slsr1_0(i32 %b.arg, i32 %s.arg) #0 {
; GFX9-LABEL: slsr1_0: ; GFX9-LABEL: slsr1_0:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_mul_u32_u24_e32 v3, v0, v1 ; GFX9-NEXT: v_mul_u32_u24_e32 v3, v0, v1
; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v1 ; GFX9-NEXT: v_and_b32_e32 v2, 0xffffff, v1
; GFX9-NEXT: global_store_dword v[0:1], v3, off ; GFX9-NEXT: global_store_dword v[0:1], v3, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v2 ; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v2
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 ; GFX9-NEXT: v_add_u32_e32 v0, v0, v2
; GFX9-NEXT: global_store_dword v[0:1], v0, off ; GFX9-NEXT: global_store_dword v[0:1], v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
%b = and i32 %b.arg, 16777215 %b = and i32 %b.arg, 16777215
%s = and i32 %s.arg, 16777215 %s = and i32 %s.arg, 16777215
; CHECK-LABEL: @slsr1( ; CHECK-LABEL: @slsr1(
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/multilevel-break.ll

Show First 20 Lines • Show All 228 Lines • ▼ Show 20 Lines
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: s_and_b64 vcc, exec, vcc ; GCN-NEXT: s_and_b64 vcc, exec, vcc
; GCN-NEXT: s_mov_b64 s[8:9], -1 ; GCN-NEXT: s_mov_b64 s[8:9], -1
; GCN-NEXT: s_cbranch_vccz BB1_1 ; GCN-NEXT: s_cbranch_vccz BB1_1
; GCN-NEXT: ; %bb.8: ; %case0 ; GCN-NEXT: ; %bb.8: ; %case0
; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1 ; GCN-NEXT: ; in Loop: Header=BB1_2 Depth=1
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0
; GCN-NEXT: s_mov_b64 s[8:9], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 s[8:9], 0
; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1 ; GCN-NEXT: v_cmp_ge_i32_e32 vcc, v0, v1
; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec ; GCN-NEXT: s_andn2_b64 s[6:7], s[6:7], exec
; GCN-NEXT: s_and_b64 s[10:11], vcc, exec ; GCN-NEXT: s_and_b64 s[10:11], vcc, exec
; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11] ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
; GCN-NEXT: s_branch BB1_1 ; GCN-NEXT: s_branch BB1_1
; GCN-NEXT: BB1_9: ; %loop.exit.guard ; GCN-NEXT: BB1_9: ; %loop.exit.guard
; GCN-NEXT: s_or_b64 exec, exec, s[0:1] ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
; GCN-NEXT: s_and_saveexec_b64 s[0:1], s[4:5] ; GCN-NEXT: s_and_saveexec_b64 s[0:1], s[4:5]
Show All 35 Lines

llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll

Show First 20 Lines • Show All 180 Lines • ▼ Show 20 Lines
; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0 ; GCN-NEXT: buffer_load_dword v1, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_lt_i32_e64 s[0:1], 8, v1 ; GCN-NEXT: v_cmp_lt_i32_e64 s[0:1], 8, v1
; GCN-NEXT: s_and_b64 vcc, exec, s[0:1] ; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]
; GCN-NEXT: s_cbranch_vccz BB1_3 ; GCN-NEXT: s_cbranch_vccz BB1_3
; GCN-NEXT: BB1_6: ; %bb31 ; GCN-NEXT: BB1_6: ; %bb31
; GCN-NEXT: v_mov_b32_e32 v0, 0 ; GCN-NEXT: v_mov_b32_e32 v0, 0
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; IR-LABEL: @nested_loop_conditions( ; IR-LABEL: @nested_loop_conditions(
; IR-NEXT: bb: ; IR-NEXT: bb:
; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4 ; IR-NEXT: [[MY_TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x() #4
; IR-NEXT: [[MY_TMP1:%.*]] = zext i32 [[MY_TMP]] to i64 ; IR-NEXT: [[MY_TMP1:%.*]] = zext i32 [[MY_TMP]] to i64
; IR-NEXT: [[MY_TMP2:%.*]] = getelementptr inbounds i64, i64 addrspace(1)* [[ARG:%.*]], i64 [[MY_TMP1]] ; IR-NEXT: [[MY_TMP2:%.*]] = getelementptr inbounds i64, i64 addrspace(1)* [[ARG:%.*]], i64 [[MY_TMP1]]
; IR-NEXT: [[MY_TMP3:%.*]] = load i64, i64 addrspace(1)* [[MY_TMP2]], align 16 ; IR-NEXT: [[MY_TMP3:%.*]] = load i64, i64 addrspace(1)* [[MY_TMP2]], align 16
; IR-NEXT: [[MY_TMP932:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* undef, align 16 ; IR-NEXT: [[MY_TMP932:%.*]] = load <4 x i32>, <4 x i32> addrspace(1)* undef, align 16
▲ Show 20 Lines • Show All 147 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_u32_e32 v0, v2, v0 ; MUBUF-NEXT: v_add_u32_e32 v0, v2, v0
; MUBUF-NEXT: s_waitcnt lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: global_store_dword v1, v0, s[4:5] ; MUBUF-NEXT: global_store_dword v1, v0, s[4:5]
; MUBUF-NEXT: BB0_3: ; %bb.2 ; MUBUF-NEXT: BB0_3: ; %bb.2
; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: global_store_dword v[0:1], v0, off ; MUBUF-NEXT: global_store_dword v[0:1], v0, off
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_endpgm ; MUBUF-NEXT: s_endpgm
; ;
; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4: ; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align4:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; FLATSCR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8 ; FLATSCR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; FLATSCR-NEXT: s_mov_b32 s32, 16 ; FLATSCR-NEXT: s_mov_b32 s32, 16
Show All 19 Lines
; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v0, v2, v0 ; FLATSCR-NEXT: v_add_u32_e32 v0, v2, v0
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; FLATSCR-NEXT: global_store_dword v1, v0, s[0:1] ; FLATSCR-NEXT: global_store_dword v1, v0, s[0:1]
; FLATSCR-NEXT: BB0_3: ; %bb.2 ; FLATSCR-NEXT: BB0_3: ; %bb.2
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_endpgm ; FLATSCR-NEXT: s_endpgm
entry: entry:
%cond0 = icmp eq i32 %arg.cond0, 0 %cond0 = icmp eq i32 %arg.cond0, 0
br i1 %cond0, label %bb.0, label %bb.2 br i1 %cond0, label %bb.0, label %bb.2
bb.0: bb.0:
%alloca = alloca [16 x i32], align 4, addrspace(5) %alloca = alloca [16 x i32], align 4, addrspace(5)
▲ Show 20 Lines • Show All 52 Lines • ▼ Show 20 Lines
; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0 ; MUBUF-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x0
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_u32_e32 v0, v2, v0 ; MUBUF-NEXT: v_add_u32_e32 v0, v2, v0
; MUBUF-NEXT: s_waitcnt lgkmcnt(0) ; MUBUF-NEXT: s_waitcnt lgkmcnt(0)
; MUBUF-NEXT: global_store_dword v1, v0, s[4:5] ; MUBUF-NEXT: global_store_dword v1, v0, s[4:5]
; MUBUF-NEXT: BB1_2: ; %bb.1 ; MUBUF-NEXT: BB1_2: ; %bb.1
; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: global_store_dword v[0:1], v0, off ; MUBUF-NEXT: global_store_dword v[0:1], v0, off
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_endpgm ; MUBUF-NEXT: s_endpgm
; ;
; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64: ; FLATSCR-LABEL: kernel_non_entry_block_static_alloca_uniformly_reached_align64:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5 ; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s2, s5
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0 ; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s3, 0
; FLATSCR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8 ; FLATSCR-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x8
; FLATSCR-NEXT: s_mov_b32 s32, 64 ; FLATSCR-NEXT: s_mov_b32 s32, 64
Show All 14 Lines
; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0 ; FLATSCR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x0
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v0, v2, v0 ; FLATSCR-NEXT: v_add_u32_e32 v0, v2, v0
; FLATSCR-NEXT: s_waitcnt lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt lgkmcnt(0)
; FLATSCR-NEXT: global_store_dword v1, v0, s[0:1] ; FLATSCR-NEXT: global_store_dword v1, v0, s[0:1]
; FLATSCR-NEXT: BB1_2: ; %bb.1 ; FLATSCR-NEXT: BB1_2: ; %bb.1
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_endpgm ; FLATSCR-NEXT: s_endpgm
entry: entry:
%cond = icmp eq i32 %arg.cond, 0 %cond = icmp eq i32 %arg.cond, 0
br i1 %cond, label %bb.0, label %bb.1 br i1 %cond, label %bb.0, label %bb.1
bb.0: bb.0:
%alloca = alloca [16 x i32], align 64, addrspace(5) %alloca = alloca [16 x i32], align 64, addrspace(5)
%gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0 %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
▲ Show 20 Lines • Show All 46 Lines • ▼ Show 20 Lines
; MUBUF-NEXT: s_mov_b32 s32, s6 ; MUBUF-NEXT: s_mov_b32 s32, s6
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_u32_e32 v2, v2, v3 ; MUBUF-NEXT: v_add_u32_e32 v2, v2, v3
; MUBUF-NEXT: global_store_dword v[0:1], v2, off ; MUBUF-NEXT: global_store_dword v[0:1], v2, off
; MUBUF-NEXT: BB2_3: ; %bb.2 ; MUBUF-NEXT: BB2_3: ; %bb.2
; MUBUF-NEXT: s_or_b64 exec, exec, s[4:5] ; MUBUF-NEXT: s_or_b64 exec, exec, s[4:5]
; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: global_store_dword v[0:1], v0, off ; MUBUF-NEXT: global_store_dword v[0:1], v0, off
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_sub_u32 s32, s32, 0x400 ; MUBUF-NEXT: s_sub_u32 s32, s32, 0x400
; MUBUF-NEXT: s_mov_b32 s33, s7 ; MUBUF-NEXT: s_mov_b32 s33, s7
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_setpc_b64 s[30:31] ; MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; FLATSCR-LABEL: func_non_entry_block_static_alloca_align4: ; FLATSCR-LABEL: func_non_entry_block_static_alloca_align4:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR-NEXT: s_mov_b32 s5, s33 ; FLATSCR-NEXT: s_mov_b32 s5, s33
; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2 ; FLATSCR-NEXT: v_cmp_eq_u32_e32 vcc, 0, v2
; FLATSCR-NEXT: s_mov_b32 s33, s32 ; FLATSCR-NEXT: s_mov_b32 s33, s32
Show All 18 Lines
; FLATSCR-NEXT: s_mov_b32 s32, s4 ; FLATSCR-NEXT: s_mov_b32 s32, s4
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3 ; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3
; FLATSCR-NEXT: global_store_dword v[0:1], v2, off ; FLATSCR-NEXT: global_store_dword v[0:1], v2, off
; FLATSCR-NEXT: BB2_3: ; %bb.2 ; FLATSCR-NEXT: BB2_3: ; %bb.2
; FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1] ; FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1]
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_sub_u32 s32, s32, 16 ; FLATSCR-NEXT: s_sub_u32 s32, s32, 16
; FLATSCR-NEXT: s_mov_b32 s33, s5 ; FLATSCR-NEXT: s_mov_b32 s33, s5
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_setpc_b64 s[30:31] ; FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%cond0 = icmp eq i32 %arg.cond0, 0 %cond0 = icmp eq i32 %arg.cond0, 0
br i1 %cond0, label %bb.0, label %bb.2 br i1 %cond0, label %bb.0, label %bb.2
bb.0: bb.0:
%alloca = alloca [16 x i32], align 4, addrspace(5) %alloca = alloca [16 x i32], align 4, addrspace(5)
▲ Show 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; MUBUF-NEXT: s_mov_b32 s32, s6 ; MUBUF-NEXT: s_mov_b32 s32, s6
; MUBUF-NEXT: s_waitcnt vmcnt(0) ; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: v_add_u32_e32 v2, v2, v3 ; MUBUF-NEXT: v_add_u32_e32 v2, v2, v3
; MUBUF-NEXT: global_store_dword v[0:1], v2, off ; MUBUF-NEXT: global_store_dword v[0:1], v2, off
; MUBUF-NEXT: BB3_2: ; %bb.1 ; MUBUF-NEXT: BB3_2: ; %bb.1
; MUBUF-NEXT: s_or_b64 exec, exec, s[4:5] ; MUBUF-NEXT: s_or_b64 exec, exec, s[4:5]
; MUBUF-NEXT: v_mov_b32_e32 v0, 0 ; MUBUF-NEXT: v_mov_b32_e32 v0, 0
; MUBUF-NEXT: global_store_dword v[0:1], v0, off ; MUBUF-NEXT: global_store_dword v[0:1], v0, off
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_sub_u32 s32, s32, 0x2000 ; MUBUF-NEXT: s_sub_u32 s32, s32, 0x2000
; MUBUF-NEXT: s_mov_b32 s33, s7 ; MUBUF-NEXT: s_mov_b32 s33, s7
; MUBUF-NEXT: s_waitcnt vmcnt(0)
; MUBUF-NEXT: s_setpc_b64 s[30:31] ; MUBUF-NEXT: s_setpc_b64 s[30:31]
; ;
; FLATSCR-LABEL: func_non_entry_block_static_alloca_align64: ; FLATSCR-LABEL: func_non_entry_block_static_alloca_align64:
; FLATSCR: ; %bb.0: ; %entry ; FLATSCR: ; %bb.0: ; %entry
; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; FLATSCR-NEXT: s_add_u32 s0, s32, 63 ; FLATSCR-NEXT: s_add_u32 s0, s32, 63
; FLATSCR-NEXT: s_mov_b32 s3, s33 ; FLATSCR-NEXT: s_mov_b32 s3, s33
; FLATSCR-NEXT: s_and_b32 s33, s0, 0xffffffc0 ; FLATSCR-NEXT: s_and_b32 s33, s0, 0xffffffc0
Show All 13 Lines
; FLATSCR-NEXT: s_mov_b32 s32, s2 ; FLATSCR-NEXT: s_mov_b32 s32, s2
; FLATSCR-NEXT: s_waitcnt vmcnt(0) ; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3 ; FLATSCR-NEXT: v_add_u32_e32 v2, v2, v3
; FLATSCR-NEXT: global_store_dword v[0:1], v2, off ; FLATSCR-NEXT: global_store_dword v[0:1], v2, off
; FLATSCR-NEXT: BB3_2: ; %bb.1 ; FLATSCR-NEXT: BB3_2: ; %bb.1
; FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1] ; FLATSCR-NEXT: s_or_b64 exec, exec, s[0:1]
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0 ; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
; FLATSCR-NEXT: global_store_dword v[0:1], v0, off ; FLATSCR-NEXT: global_store_dword v[0:1], v0, off
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_sub_u32 s32, s32, 0x80 ; FLATSCR-NEXT: s_sub_u32 s32, s32, 0x80
; FLATSCR-NEXT: s_mov_b32 s33, s3 ; FLATSCR-NEXT: s_mov_b32 s33, s3
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
; FLATSCR-NEXT: s_setpc_b64 s[30:31] ; FLATSCR-NEXT: s_setpc_b64 s[30:31]
entry: entry:
%cond = icmp eq i32 %arg.cond, 0 %cond = icmp eq i32 %arg.cond, 0
br i1 %cond, label %bb.0, label %bb.1 br i1 %cond, label %bb.0, label %bb.1
bb.0: bb.0:
%alloca = alloca [16 x i32], align 64, addrspace(5) %alloca = alloca [16 x i32], align 64, addrspace(5)
%gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0 %gep0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
Show All 18 Lines

llvm/test/CodeGen/AMDGPU/private-access-no-objects.ll

Show All 28 Lines
define amdgpu_kernel void @store_to_inttoptr() #0 { define amdgpu_kernel void @store_to_inttoptr() #0 {
store volatile i32 0, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*) store volatile i32 0, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}load_from_undef: ; GCN-LABEL: {{^}}load_from_undef:
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1] ; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3] ; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, 0 offen{{$}} ; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, 0 offen glc{{$}}
define amdgpu_kernel void @load_from_undef() #0 { define amdgpu_kernel void @load_from_undef() #0 {
%ld = load volatile i32, i32 addrspace(5)* undef %ld = load volatile i32, i32 addrspace(5)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_from_inttoptr: ; GCN-LABEL: {{^}}load_from_inttoptr:
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1] ; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3] ; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, 0 offset:124{{$}} ; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, 0 offset:124 glc{{$}}
define amdgpu_kernel void @load_from_inttoptr() #0 { define amdgpu_kernel void @load_from_inttoptr() #0 {
%ld = load volatile i32, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*) %ld = load volatile i32, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/rsq.ll

Show All 38 Lines
} }
; Recognize that this is rsqrt(a) * rcp(b) * c, ; Recognize that this is rsqrt(a) * rcp(b) * c,
; not 1 / ( 1 / sqrt(a)) * rcp(b) * c. ; not 1 / ( 1 / sqrt(a)) * rcp(b) * c.
; NOTE: c * rcp( sqrt(a) * b ) is generated when we move rcp generation to AMGGPUCogenPrepare. ; NOTE: c * rcp( sqrt(a) * b ) is generated when we move rcp generation to AMGGPUCogenPrepare.
; SI-LABEL: @rsqrt_fmul ; SI-LABEL: @rsqrt_fmul
; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}} ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 glc{{$}}
; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4
; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8
; SI-UNSAFE-DAG: v_sqrt_f32_e32 [[SQRT:v[0-9]+]], [[A]] ; SI-UNSAFE-DAG: v_sqrt_f32_e32 [[SQRT:v[0-9]+]], [[A]]
; SI-UNSAFE-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[SQRT]], [[B]] ; SI-UNSAFE-DAG: v_mul_f32_e32 [[MUL:v[0-9]+]], [[SQRT]], [[B]]
; SI-UNSAFE-DAG: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[MUL]] ; SI-UNSAFE-DAG: v_rcp_f32_e32 [[RCP:v[0-9]+]], [[MUL]]
; SI-UNSAFE-DAG: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[RCP]] ; SI-UNSAFE-DAG: v_mul_f32_e32 [[RESULT:v[0-9]+]], [[C]], [[RCP]]
; SI-UNSAFE: buffer_store_dword [[RESULT]] ; SI-UNSAFE: buffer_store_dword [[RESULT]]
▲ Show 20 Lines • Show All 89 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/select.f16.ll

Show All 18 Lines
; SI-NEXT: s_mov_b32 s8, s10 ; SI-NEXT: s_mov_b32 s8, s10
; SI-NEXT: s_mov_b32 s9, s11 ; SI-NEXT: s_mov_b32 s9, s11
; SI-NEXT: s_mov_b32 s22, s2 ; SI-NEXT: s_mov_b32 s22, s2
; SI-NEXT: s_mov_b32 s23, s3 ; SI-NEXT: s_mov_b32 s23, s3
; SI-NEXT: s_mov_b32 s10, s2 ; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3 ; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: s_mov_b32 s14, s2 ; SI-NEXT: s_mov_b32 s14, s2
; SI-NEXT: s_mov_b32 s15, s3 ; SI-NEXT: s_mov_b32 s15, s3
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 ; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 glc
; SI-NEXT: buffer_load_ushort v1, off, s[20:23], 0 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 ; SI-NEXT: buffer_load_ushort v1, off, s[20:23], 0 glc
; SI-NEXT: buffer_load_ushort v3, off, s[12:15], 0 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v3, off, s[12:15], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_waitcnt vmcnt(3)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v3, v3 ; SI-NEXT: v_cvt_f32_f16_e32 v3, v3
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 ; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: select_f16: ; VI-LABEL: select_f16:
Show All 12 Lines
; VI-NEXT: s_mov_b32 s8, s10 ; VI-NEXT: s_mov_b32 s8, s10
; VI-NEXT: s_mov_b32 s9, s11 ; VI-NEXT: s_mov_b32 s9, s11
; VI-NEXT: s_mov_b32 s22, s2 ; VI-NEXT: s_mov_b32 s22, s2
; VI-NEXT: s_mov_b32 s23, s3 ; VI-NEXT: s_mov_b32 s23, s3
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_mov_b32 s14, s2 ; VI-NEXT: s_mov_b32 s14, s2
; VI-NEXT: s_mov_b32 s15, s3 ; VI-NEXT: s_mov_b32 s15, s3
; VI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 glc
; VI-NEXT: buffer_load_ushort v1, off, s[20:23], 0 ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[20:23], 0 glc
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0 ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v3, off, s[12:15], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; VI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_short v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %b, half addrspace(1)* %b,
half addrspace(1)* %c, half addrspace(1)* %c,
half addrspace(1)* %d) { half addrspace(1)* %d) {
Show All 22 Lines
; SI-NEXT: s_mov_b32 s16, s4 ; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5 ; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s18, s10 ; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11 ; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0.5, v0 ; SI-NEXT: v_cmp_lt_f32_e32 vcc, 0.5, v0
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: select_f16_imm_a: ; VI-LABEL: select_f16_imm_a:
Show All 9 Lines
; VI-NEXT: s_mov_b32 s16, s4 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s17, s5 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10 ; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11 ; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, 0.5, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %b, half addrspace(1)* %b,
half addrspace(1)* %c, half addrspace(1)* %c,
half addrspace(1)* %d) { half addrspace(1)* %d) {
entry: entry:
Show All 20 Lines
; SI-NEXT: s_mov_b32 s16, s4 ; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5 ; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s18, s10 ; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11 ; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0.5, v0 ; SI-NEXT: v_cmp_gt_f32_e32 vcc, 0.5, v0
; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: select_f16_imm_b: ; VI-LABEL: select_f16_imm_b:
Show All 9 Lines
; VI-NEXT: s_mov_b32 s16, s4 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s17, s5 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10 ; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11 ; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0 ; VI-NEXT: v_cmp_gt_f16_e32 vcc, 0.5, v0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %c, half addrspace(1)* %c,
half addrspace(1)* %d) { half addrspace(1)* %d) {
entry: entry:
Show All 20 Lines
; SI-NEXT: s_mov_b32 s16, s4 ; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5 ; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s18, s10 ; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11 ; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v1 ; SI-NEXT: v_cmp_nlt_f32_e32 vcc, v0, v1
; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v2, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v2, vcc
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: select_f16_imm_c: ; VI-LABEL: select_f16_imm_c:
Show All 9 Lines
; VI-NEXT: s_mov_b32 s16, s4 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s17, s5 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10 ; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11 ; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, 0x3800 ; VI-NEXT: v_mov_b32_e32 v3, 0x3800
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1 ; VI-NEXT: v_cmp_nlt_f16_e32 vcc, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %b, half addrspace(1)* %b,
half addrspace(1)* %d) { half addrspace(1)* %d) {
entry: entry:
Show All 20 Lines
; SI-NEXT: s_mov_b32 s16, s4 ; SI-NEXT: s_mov_b32 s16, s4
; SI-NEXT: s_mov_b32 s17, s5 ; SI-NEXT: s_mov_b32 s17, s5
; SI-NEXT: s_mov_b32 s4, s6 ; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s7 ; SI-NEXT: s_mov_b32 s5, s7
; SI-NEXT: s_mov_b32 s18, s10 ; SI-NEXT: s_mov_b32 s18, s10
; SI-NEXT: s_mov_b32 s19, s11 ; SI-NEXT: s_mov_b32 s19, s11
; SI-NEXT: s_mov_b32 s6, s10 ; SI-NEXT: s_mov_b32 s6, s10
; SI-NEXT: s_mov_b32 s7, s11 ; SI-NEXT: s_mov_b32 s7, s11
; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; SI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; SI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b32 s8, s0 ; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1 ; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1 ; SI-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v2, vcc ; SI-NEXT: v_cndmask_b32_e32 v0, 0.5, v2, vcc
; SI-NEXT: v_cvt_f16_f32_e32 v0, v0 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v0
; SI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; SI-NEXT: buffer_store_short v0, off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: select_f16_imm_d: ; VI-LABEL: select_f16_imm_d:
Show All 9 Lines
; VI-NEXT: s_mov_b32 s16, s4 ; VI-NEXT: s_mov_b32 s16, s4
; VI-NEXT: s_mov_b32 s17, s5 ; VI-NEXT: s_mov_b32 s17, s5
; VI-NEXT: s_mov_b32 s4, s6 ; VI-NEXT: s_mov_b32 s4, s6
; VI-NEXT: s_mov_b32 s5, s7 ; VI-NEXT: s_mov_b32 s5, s7
; VI-NEXT: s_mov_b32 s18, s10 ; VI-NEXT: s_mov_b32 s18, s10
; VI-NEXT: s_mov_b32 s19, s11 ; VI-NEXT: s_mov_b32 s19, s11
; VI-NEXT: s_mov_b32 s6, s10 ; VI-NEXT: s_mov_b32 s6, s10
; VI-NEXT: s_mov_b32 s7, s11 ; VI-NEXT: s_mov_b32 s7, s11
; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[12:15], 0 glc
; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[16:19], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[4:7], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, 0x3800 ; VI-NEXT: v_mov_b32_e32 v3, 0x3800
; VI-NEXT: s_mov_b32 s8, s0 ; VI-NEXT: s_mov_b32 s8, s0
; VI-NEXT: s_mov_b32 s9, s1 ; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1 ; VI-NEXT: v_cmp_lt_f16_e32 vcc, v0, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; VI-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; VI-NEXT: buffer_store_short v0, off, s[8:11], 0 ; VI-NEXT: buffer_store_short v0, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r, half addrspace(1)* %r,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %b, half addrspace(1)* %b,
half addrspace(1)* %c) { half addrspace(1)* %c) {
entry: entry:
▲ Show 20 Lines • Show All 521 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/shl.ll

Show First 20 Lines • Show All 288 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s8, s6 ; GCN-NEXT: s_mov_b32 s8, s6
; GCN-NEXT: s_mov_b32 s9, s7 ; GCN-NEXT: s_mov_b32 s9, s7
; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v1, 0
; GCN-NEXT: s_mov_b32 s14, 0 ; GCN-NEXT: s_mov_b32 s14, 0
; GCN-NEXT: s_mov_b32 s15, s3 ; GCN-NEXT: s_mov_b32 s15, s3
; GCN-NEXT: s_mov_b64 s[12:13], s[6:7] ; GCN-NEXT: s_mov_b64 s[12:13], s[6:7]
; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 ; GCN-NEXT: buffer_load_ushort v2, off, s[8:11], 0 glc
; GCN-NEXT: buffer_load_ushort v0, v[0:1], s[12:15], 0 addr64 offset:2 ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_ushort v0, v[0:1], s[12:15], 0 addr64 offset:2 glc
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b32 s0, s4 ; GCN-NEXT: s_mov_b32 s0, s4
; GCN-NEXT: s_mov_b32 s1, s5 ; GCN-NEXT: s_mov_b32 s1, s5
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0 ; GCN-NEXT: v_add_i32_e32 v0, vcc, 3, v0
; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GCN-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GCN-NEXT: v_lshl_b32_e32 v0, v2, v0 ; GCN-NEXT: v_lshl_b32_e32 v0, v2, v0
; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_short v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; EG-LABEL: shl_i16_computed_amount: ; EG-LABEL: shl_i16_computed_amount:
; EG: ; %bb.0: ; EG: ; %bb.0:
▲ Show 20 Lines • Show All 1,325 Lines • ▼ Show 20 Lines
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_load_dword s0, s[0:1], 0x9 ; GCN-NEXT: s_load_dword s0, s[0:1], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1 ; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_lshl_b32 s0, s0, 1 ; GCN-NEXT: s_lshl_b32 s0, s0, 1
; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v0, s0
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; ;
; EG-LABEL: test_mul2: ; EG-LABEL: test_mul2:
; EG: ; %bb.0: ; EG: ; %bb.0:
; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[] ; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1 ; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
; EG-NEXT: CF_END ; EG-NEXT: CF_END
; EG-NEXT: PAD ; EG-NEXT: PAD
▲ Show 20 Lines • Show All 77 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/shrink-add-sub-constant.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, 0 ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[2:3] ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_dword v3, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[2:3], s[6:7] ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 ; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v3 ; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v3
; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_dword v3, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_i32_x_sub_64_multi_use: ; VI-LABEL: v_test_i32_x_sub_64_multi_use:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v3, v[0:1] ; VI-NEXT: flat_load_dword v3, v[0:1] glc
; VI-NEXT: flat_load_dword v4, v[0:1] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v4, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3 ; VI-NEXT: v_subrev_u32_e32 v2, vcc, 64, v3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_subrev_u32_e32 v3, vcc, 64, v4 ; VI-NEXT: v_subrev_u32_e32 v3, vcc, 64, v4
; VI-NEXT: flat_store_dword v[0:1], v2 ; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_dword v[0:1], v3 ; VI-NEXT: flat_store_dword v[0:1], v3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_i32_x_sub_64_multi_use: ; GFX9-LABEL: v_test_i32_x_sub_64_multi_use:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[2:3] ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] glc
; GFX9-NEXT: global_load_dword v2, v0, s[2:3]
; GFX9-NEXT: s_waitcnt vmcnt(1)
; GFX9-NEXT: v_subrev_u32_e32 v1, 64, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[2:3] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_subrev_u32_e32 v1, 64, v1
; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v2 ; GFX9-NEXT: v_subrev_u32_e32 v2, 64, v2
; GFX9-NEXT: global_store_dword v0, v1, s[0:1] ; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_dword v0, v2, s[0:1] ; GFX9-NEXT: global_store_dword v0, v2, s[0:1]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_test_i32_x_sub_64_multi_use: ; GFX10-LABEL: v_test_i32_x_sub_64_multi_use:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_dword v1, v0, s[2:3] glc dlc
; GFX10-NEXT: global_load_dword v1, v0, s[2:3]
; GFX10-NEXT: global_load_dword v2, v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, 64, v1
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_dword v2, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_subrev_nc_u32_e32 v1, 64, v1
; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v2 ; GFX10-NEXT: v_subrev_nc_u32_e32 v2, 64, v2
; GFX10-NEXT: global_store_dword v0, v1, s[0:1] ; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_dword v0, v2, s[0:1] ; GFX10-NEXT: global_store_dword v0, v2, s[0:1]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext %gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i64 %tid.ext
%gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext %gep.out = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 %tid.ext
%x = load volatile i32, i32 addrspace(1)* %gep %x = load volatile i32, i32 addrspace(1)* %gep
%y = load volatile i32, i32 addrspace(1)* %gep %y = load volatile i32, i32 addrspace(1)* %gep
%result0 = sub i32 %x, 64 %result0 = sub i32 %x, 64
▲ Show 20 Lines • Show All 645 Lines • ▼ Show 20 Lines
; SI: ; %bb.0: ; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 ; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000 ; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, 0 ; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; SI-NEXT: v_mov_b32_e32 v1, 0 ; SI-NEXT: v_mov_b32_e32 v1, 0
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[2:3] ; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: buffer_load_ushort v2, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v3, v[0:1], s[4:7], 0 addr64 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_mov_b64 s[2:3], s[6:7] ; SI-NEXT: s_mov_b64 s[2:3], s[6:7]
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2 ; SI-NEXT: v_subrev_i32_e32 v2, vcc, 64, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v3 ; SI-NEXT: v_subrev_i32_e32 v3, vcc, 64, v3
; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_short v2, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_short v3, v[0:1], s[0:3], 0 addr64 ; SI-NEXT: buffer_store_short v3, v[0:1], s[0:3], 0 addr64
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_i16_x_sub_64_multi_use: ; VI-LABEL: v_test_i16_x_sub_64_multi_use:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 1, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_ushort v3, v[0:1] ; VI-NEXT: flat_load_ushort v3, v[0:1] glc
; VI-NEXT: flat_load_ushort v4, v[0:1] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_ushort v4, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2
; VI-NEXT: v_mov_b32_e32 v1, s1 ; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_subrev_u16_e32 v2, 64, v3 ; VI-NEXT: v_subrev_u16_e32 v2, 64, v3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_subrev_u16_e32 v3, 64, v4 ; VI-NEXT: v_subrev_u16_e32 v3, 64, v4
; VI-NEXT: flat_store_short v[0:1], v2 ; VI-NEXT: flat_store_short v[0:1], v2
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_store_short v[0:1], v3 ; VI-NEXT: flat_store_short v[0:1], v3
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; ;
; GFX9-LABEL: v_test_i16_x_sub_64_multi_use: ; GFX9-LABEL: v_test_i16_x_sub_64_multi_use:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] ; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] glc
; GFX9-NEXT: global_load_ushort v2, v0, s[2:3] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_waitcnt vmcnt(1) ; GFX9-NEXT: global_load_ushort v2, v0, s[2:3] glc
; GFX9-NEXT: v_subrev_u16_e32 v1, 64, v1
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_subrev_u16_e32 v1, 64, v1
; GFX9-NEXT: v_subrev_u16_e32 v2, 64, v2 ; GFX9-NEXT: v_subrev_u16_e32 v2, 64, v2
; GFX9-NEXT: global_store_short v0, v1, s[0:1] ; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_store_short v0, v2, s[0:1] ; GFX9-NEXT: global_store_short v0, v2, s[0:1]
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; GFX10-LABEL: v_test_i16_x_sub_64_multi_use: ; GFX10-LABEL: v_test_i16_x_sub_64_multi_use:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0 ; GFX10-NEXT: v_lshlrev_b32_e32 v0, 1, v0
; GFX10-NEXT: s_waitcnt lgkmcnt(0) ; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_clause 0x1 ; GFX10-NEXT: global_load_ushort v1, v0, s[2:3] glc dlc
; GFX10-NEXT: global_load_ushort v1, v0, s[2:3]
; GFX10-NEXT: global_load_ushort v2, v0, s[2:3]
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_sub_nc_u16_e64 v1, v1, 64
; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: global_load_ushort v2, v0, s[2:3] glc dlc
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_sub_nc_u16_e64 v1, v1, 64
; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 64 ; GFX10-NEXT: v_sub_nc_u16_e64 v2, v2, 64
; GFX10-NEXT: global_store_short v0, v1, s[0:1] ; GFX10-NEXT: global_store_short v0, v1, s[0:1]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: global_store_short v0, v2, s[0:1] ; GFX10-NEXT: global_store_short v0, v2, s[0:1]
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_endpgm ; GFX10-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext %gep = getelementptr inbounds i16, i16 addrspace(1)* %in, i64 %tid.ext
%gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext %gep.out = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext
%x = load volatile i16, i16 addrspace(1)* %gep %x = load volatile i16, i16 addrspace(1)* %gep
%y = load volatile i16, i16 addrspace(1)* %gep %y = load volatile i16, i16 addrspace(1)* %gep
%result0 = sub i16 %x, 64 %result0 = sub i16 %x, 64
▲ Show 20 Lines • Show All 1,340 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/si-annotate-cf.ll

Show First 20 Lines • Show All 206 Lines • ▼ Show 20 Lines
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_mov_b64 s[12:13], -1 ; SI-NEXT: s_mov_b64 s[12:13], -1
; SI-NEXT: s_mov_b64 vcc, s[4:5] ; SI-NEXT: s_mov_b64 vcc, s[4:5]
; SI-NEXT: s_cbranch_vccz BB3_1 ; SI-NEXT: s_cbranch_vccz BB3_1
; SI-NEXT: ; %bb.7: ; %if.else ; SI-NEXT: ; %bb.7: ; %if.else
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_mov_b64 s[12:13], 0 ; SI-NEXT: s_mov_b64 s[12:13], 0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_branch BB3_1 ; SI-NEXT: s_branch BB3_1
; SI-NEXT: BB3_8: ; %loop.exit.guard4 ; SI-NEXT: BB3_8: ; %loop.exit.guard4
; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; SI-NEXT: ; in Loop: Header=BB3_4 Depth=1
; SI-NEXT: s_and_b64 vcc, exec, s[10:11] ; SI-NEXT: s_and_b64 vcc, exec, s[10:11]
; SI-NEXT: s_cbranch_vccz BB3_4 ; SI-NEXT: s_cbranch_vccz BB3_4
; SI-NEXT: ; %bb.9: ; %loop.exit.guard ; SI-NEXT: ; %bb.9: ; %loop.exit.guard
; SI-NEXT: s_and_b64 vcc, exec, s[14:15] ; SI-NEXT: s_and_b64 vcc, exec, s[14:15]
; SI-NEXT: s_cbranch_vccz BB3_13 ; SI-NEXT: s_cbranch_vccz BB3_13
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_mov_b64 s[12:13], -1 ; FLAT-NEXT: s_mov_b64 s[12:13], -1
; FLAT-NEXT: s_mov_b64 vcc, s[4:5] ; FLAT-NEXT: s_mov_b64 vcc, s[4:5]
; FLAT-NEXT: s_cbranch_vccz BB3_1 ; FLAT-NEXT: s_cbranch_vccz BB3_1
; FLAT-NEXT: ; %bb.7: ; %if.else ; FLAT-NEXT: ; %bb.7: ; %if.else
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_mov_b64 s[12:13], 0 ; FLAT-NEXT: s_mov_b64 s[12:13], 0
; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; FLAT-NEXT: buffer_store_dword v0, off, s[4:7], 0
; FLAT-NEXT: s_waitcnt vmcnt(0)
; FLAT-NEXT: s_branch BB3_1 ; FLAT-NEXT: s_branch BB3_1
; FLAT-NEXT: BB3_8: ; %loop.exit.guard4 ; FLAT-NEXT: BB3_8: ; %loop.exit.guard4
; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1 ; FLAT-NEXT: ; in Loop: Header=BB3_4 Depth=1
; FLAT-NEXT: s_and_b64 vcc, exec, s[10:11] ; FLAT-NEXT: s_and_b64 vcc, exec, s[10:11]
; FLAT-NEXT: s_cbranch_vccz BB3_4 ; FLAT-NEXT: s_cbranch_vccz BB3_4
; FLAT-NEXT: ; %bb.9: ; %loop.exit.guard ; FLAT-NEXT: ; %bb.9: ; %loop.exit.guard
; FLAT-NEXT: s_and_b64 vcc, exec, s[14:15] ; FLAT-NEXT: s_and_b64 vcc, exec, s[14:15]
; FLAT-NEXT: s_cbranch_vccz BB3_13 ; FLAT-NEXT: s_cbranch_vccz BB3_13
▲ Show 20 Lines • Show All 57 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/sign_extend.ll

Show First 20 Lines • Show All 345 Lines • ▼ Show 20 Lines
; SI-NEXT: s_mov_b32 s6, -1 ; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_ashr_i32 s1, s0, 24 ; SI-NEXT: s_ashr_i32 s1, s0, 24
; SI-NEXT: s_bfe_i32 s2, s0, 0x80010 ; SI-NEXT: s_bfe_i32 s2, s0, 0x80010
; SI-NEXT: s_bfe_i32 s3, s0, 0x80008 ; SI-NEXT: s_bfe_i32 s3, s0, 0x80008
; SI-NEXT: s_sext_i32_i8 s0, s0 ; SI-NEXT: s_sext_i32_i8 s0, s0
; SI-NEXT: v_mov_b32_e32 v0, s0 ; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s3 ; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s2 ; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s1 ; SI-NEXT: v_mov_b32_e32 v0, s1
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_sext_v4i8_to_v4i32: ; VI-LABEL: s_sext_v4i8_to_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
; VI-NEXT: s_load_dword s0, s[0:1], 0x2c ; VI-NEXT: s_load_dword s0, s[0:1], 0x2c
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_lshrrev_b16_e64 v0, 8, s0 ; VI-NEXT: v_lshrrev_b16_e64 v0, 8, s0
; VI-NEXT: s_ashr_i32 s1, s0, 24 ; VI-NEXT: s_ashr_i32 s1, s0, 24
; VI-NEXT: s_bfe_i32 s2, s0, 0x80010 ; VI-NEXT: s_bfe_i32 s2, s0, 0x80010
; VI-NEXT: s_sext_i32_i8 s0, s0 ; VI-NEXT: s_sext_i32_i8 s0, s0
; VI-NEXT: v_bfe_i32 v0, v0, 0, 8 ; VI-NEXT: v_bfe_i32 v0, v0, 0, 8
; VI-NEXT: v_mov_b32_e32 v1, s0 ; VI-NEXT: v_mov_b32_e32 v1, s0
; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v1, off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_mov_b32_e32 v0, s2
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s1 ; VI-NEXT: v_mov_b32_e32 v0, s1
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%cast = bitcast i32 %a to <4 x i8> %cast = bitcast i32 %a to <4 x i8>
%ext = sext <4 x i8> %cast to <4 x i32> %ext = sext <4 x i8> %cast to <4 x i32>
%elt0 = extractelement <4 x i32> %ext, i32 0 %elt0 = extractelement <4 x i32> %ext, i32 0
%elt1 = extractelement <4 x i32> %ext, i32 1 %elt1 = extractelement <4 x i32> %ext, i32 1
%elt2 = extractelement <4 x i32> %ext, i32 2 %elt2 = extractelement <4 x i32> %ext, i32 2
%elt3 = extractelement <4 x i32> %ext, i32 3 %elt3 = extractelement <4 x i32> %ext, i32 3
store volatile i32 %elt0, i32 addrspace(1)* %out store volatile i32 %elt0, i32 addrspace(1)* %out
Show All 20 Lines
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_ashrrev_i32_e32 v1, 24, v0 ; SI-NEXT: v_ashrrev_i32_e32 v1, 24, v0
; SI-NEXT: v_bfe_i32 v2, v0, 16, 8 ; SI-NEXT: v_bfe_i32 v2, v0, 16, 8
; SI-NEXT: v_bfe_i32 v3, v0, 8, 8 ; SI-NEXT: v_bfe_i32 v3, v0, 8, 8
; SI-NEXT: v_bfe_i32 v0, v0, 0, 8 ; SI-NEXT: v_bfe_i32 v0, v0, 0, 8
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_sext_v4i8_to_v4i32: ; VI-LABEL: v_sext_v4i8_to_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s6 ; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7 ; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0 ; VI-NEXT: buffer_load_dword v0, off, s[8:11], 0
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_lshrrev_b16_e32 v1, 8, v0 ; VI-NEXT: v_lshrrev_b16_e32 v1, 8, v0
; VI-NEXT: v_ashrrev_i32_e32 v2, 24, v0 ; VI-NEXT: v_ashrrev_i32_e32 v2, 24, v0
; VI-NEXT: v_bfe_i32 v3, v0, 16, 8 ; VI-NEXT: v_bfe_i32 v3, v0, 16, 8
; VI-NEXT: v_bfe_i32 v0, v0, 0, 8 ; VI-NEXT: v_bfe_i32 v0, v0, 0, 8
; VI-NEXT: v_bfe_i32 v1, v1, 0, 8 ; VI-NEXT: v_bfe_i32 v1, v1, 0, 8
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%a = load i32, i32 addrspace(1)* %in %a = load i32, i32 addrspace(1)* %in
%cast = bitcast i32 %a to <4 x i8> %cast = bitcast i32 %a to <4 x i8>
%ext = sext <4 x i8> %cast to <4 x i32> %ext = sext <4 x i8> %cast to <4 x i32>
%elt0 = extractelement <4 x i32> %ext, i32 0 %elt0 = extractelement <4 x i32> %ext, i32 0
%elt1 = extractelement <4 x i32> %ext, i32 1 %elt1 = extractelement <4 x i32> %ext, i32 1
%elt2 = extractelement <4 x i32> %ext, i32 2 %elt2 = extractelement <4 x i32> %ext, i32 2
%elt3 = extractelement <4 x i32> %ext, i32 3 %elt3 = extractelement <4 x i32> %ext, i32 3
Show All 14 Lines
; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_ashr_i64 s[4:5], s[6:7], 48 ; SI-NEXT: s_ashr_i64 s[4:5], s[6:7], 48
; SI-NEXT: s_ashr_i32 s5, s6, 16 ; SI-NEXT: s_ashr_i32 s5, s6, 16
; SI-NEXT: s_sext_i32_i16 s6, s6 ; SI-NEXT: s_sext_i32_i16 s6, s6
; SI-NEXT: v_mov_b32_e32 v0, s6 ; SI-NEXT: v_mov_b32_e32 v0, s6
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s5 ; SI-NEXT: v_mov_b32_e32 v0, s5
; SI-NEXT: s_sext_i32_i16 s7, s7 ; SI-NEXT: s_sext_i32_i16 s7, s7
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s7 ; SI-NEXT: v_mov_b32_e32 v0, s7
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt expcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: s_sext_v4i16_to_v4i32: ; VI-LABEL: s_sext_v4i16_to_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_ashr_i32 s5, s6, 16 ; VI-NEXT: s_ashr_i32 s5, s6, 16
; VI-NEXT: s_sext_i32_i16 s6, s6 ; VI-NEXT: s_sext_i32_i16 s6, s6
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: v_mov_b32_e32 v0, s6 ; VI-NEXT: v_mov_b32_e32 v0, s6
; VI-NEXT: s_ashr_i32 s4, s7, 16 ; VI-NEXT: s_ashr_i32 s4, s7, 16
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s5 ; VI-NEXT: v_mov_b32_e32 v0, s5
; VI-NEXT: s_sext_i32_i16 s7, s7 ; VI-NEXT: s_sext_i32_i16 s7, s7
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s7 ; VI-NEXT: v_mov_b32_e32 v0, s7
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%cast = bitcast i64 %a to <4 x i16> %cast = bitcast i64 %a to <4 x i16>
%ext = sext <4 x i16> %cast to <4 x i32> %ext = sext <4 x i16> %cast to <4 x i32>
%elt0 = extractelement <4 x i32> %ext, i32 0 %elt0 = extractelement <4 x i32> %ext, i32 0
%elt1 = extractelement <4 x i32> %ext, i32 1 %elt1 = extractelement <4 x i32> %ext, i32 1
%elt2 = extractelement <4 x i32> %ext, i32 2 %elt2 = extractelement <4 x i32> %ext, i32 2
%elt3 = extractelement <4 x i32> %ext, i32 3 %elt3 = extractelement <4 x i32> %ext, i32 3
store volatile i32 %elt0, i32 addrspace(1)* %out store volatile i32 %elt0, i32 addrspace(1)* %out
Show All 18 Lines
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_waitcnt vmcnt(0) ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_ashr_i64 v[2:3], v[0:1], 48 ; SI-NEXT: v_ashr_i64 v[2:3], v[0:1], 48
; SI-NEXT: v_ashrrev_i32_e32 v3, 16, v0 ; SI-NEXT: v_ashrrev_i32_e32 v3, 16, v0
; SI-NEXT: v_bfe_i32 v0, v0, 0, 16 ; SI-NEXT: v_bfe_i32 v0, v0, 0, 16
; SI-NEXT: v_bfe_i32 v1, v1, 0, 16 ; SI-NEXT: v_bfe_i32 v1, v1, 0, 16
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v3, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0 ; SI-NEXT: buffer_store_dword v2, off, s[0:3], 0
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
; ;
; VI-LABEL: v_sext_v4i16_to_v4i32: ; VI-LABEL: v_sext_v4i16_to_v4i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s8, s6 ; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7 ; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0 ; VI-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_ashrrev_i32_e32 v3, 16, v0 ; VI-NEXT: v_ashrrev_i32_e32 v3, 16, v0
; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 ; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
; VI-NEXT: v_ashrrev_i32_e32 v2, 16, v1 ; VI-NEXT: v_ashrrev_i32_e32 v2, 16, v1
; VI-NEXT: v_bfe_i32 v1, v1, 0, 16 ; VI-NEXT: v_bfe_i32 v1, v1, 0, 16
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v3, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v2, off, s[0:3], 0
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%a = load i64, i64 addrspace(1)* %in %a = load i64, i64 addrspace(1)* %in
%cast = bitcast i64 %a to <4 x i16> %cast = bitcast i64 %a to <4 x i16>
%ext = sext <4 x i16> %cast to <4 x i32> %ext = sext <4 x i16> %cast to <4 x i32>
%elt0 = extractelement <4 x i32> %ext, i32 0 %elt0 = extractelement <4 x i32> %ext, i32 0
%elt1 = extractelement <4 x i32> %ext, i32 1 %elt1 = extractelement <4 x i32> %ext, i32 1
%elt2 = extractelement <4 x i32> %ext, i32 2 %elt2 = extractelement <4 x i32> %ext, i32 2
%elt3 = extractelement <4 x i32> %ext, i32 3 %elt3 = extractelement <4 x i32> %ext, i32 3
Show All 10 Lines

llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s
; Make sure the stack is never realigned for entry functions. ; Make sure the stack is never realigned for entry functions.
define amdgpu_kernel void @max_alignment_128() #0 { define amdgpu_kernel void @max_alignment_128() #0 {
; VI-LABEL: max_alignment_128: ; VI-LABEL: max_alignment_128:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_add_u32 s4, s4, s7 ; VI-NEXT: s_add_u32 s4, s4, s7
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8 ; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; VI-NEXT: s_add_u32 s0, s0, s7 ; VI-NEXT: s_add_u32 s0, s0, s7
; VI-NEXT: s_addc_u32 s1, s1, 0 ; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v0, 9 ; VI-NEXT: v_mov_b32_e32 v0, 9
; VI-NEXT: s_mov_b32 flat_scratch_lo, s5 ; VI-NEXT: s_mov_b32 flat_scratch_lo, s5
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; VI-NEXT: .section .rodata,#alloc ; VI-NEXT: .section .rodata,#alloc
; VI-NEXT: .p2align 6 ; VI-NEXT: .p2align 6
; VI-NEXT: .amdhsa_kernel max_alignment_128 ; VI-NEXT: .amdhsa_kernel max_alignment_128
; VI-NEXT: .amdhsa_group_segment_fixed_size 0 ; VI-NEXT: .amdhsa_group_segment_fixed_size 0
; VI-NEXT: .amdhsa_private_segment_fixed_size 256 ; VI-NEXT: .amdhsa_private_segment_fixed_size 256
; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1 ; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 ; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
Show All 30 Lines
; GFX9-LABEL: max_alignment_128: ; GFX9-LABEL: max_alignment_128:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX9-NEXT: s_add_u32 s0, s0, s7 ; GFX9-NEXT: s_add_u32 s0, s0, s7
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: v_mov_b32_e32 v0, 9 ; GFX9-NEXT: v_mov_b32_e32 v0, 9
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:128
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: .section .rodata,#alloc ; GFX9-NEXT: .section .rodata,#alloc
; GFX9-NEXT: .p2align 6 ; GFX9-NEXT: .p2align 6
; GFX9-NEXT: .amdhsa_kernel max_alignment_128 ; GFX9-NEXT: .amdhsa_kernel max_alignment_128
; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0 ; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
; GFX9-NEXT: .amdhsa_private_segment_fixed_size 256 ; GFX9-NEXT: .amdhsa_private_segment_fixed_size 256
; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1 ; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 ; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
Show All 37 Lines
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_add_u32 s4, s4, s7 ; VI-NEXT: s_add_u32 s4, s4, s7
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8 ; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; VI-NEXT: s_add_u32 s0, s0, s7 ; VI-NEXT: s_add_u32 s0, s0, s7
; VI-NEXT: s_addc_u32 s1, s1, 0 ; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v0, 9 ; VI-NEXT: v_mov_b32_e32 v0, 9
; VI-NEXT: s_mov_b32 flat_scratch_lo, s5 ; VI-NEXT: s_mov_b32 flat_scratch_lo, s5
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; VI-NEXT: .section .rodata,#alloc ; VI-NEXT: .section .rodata,#alloc
; VI-NEXT: .p2align 6 ; VI-NEXT: .p2align 6
; VI-NEXT: .amdhsa_kernel stackrealign_attr ; VI-NEXT: .amdhsa_kernel stackrealign_attr
; VI-NEXT: .amdhsa_group_segment_fixed_size 0 ; VI-NEXT: .amdhsa_group_segment_fixed_size 0
; VI-NEXT: .amdhsa_private_segment_fixed_size 8 ; VI-NEXT: .amdhsa_private_segment_fixed_size 8
; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1 ; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 ; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
Show All 30 Lines
; GFX9-LABEL: stackrealign_attr: ; GFX9-LABEL: stackrealign_attr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX9-NEXT: s_add_u32 s0, s0, s7 ; GFX9-NEXT: s_add_u32 s0, s0, s7
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: v_mov_b32_e32 v0, 9 ; GFX9-NEXT: v_mov_b32_e32 v0, 9
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: .section .rodata,#alloc ; GFX9-NEXT: .section .rodata,#alloc
; GFX9-NEXT: .p2align 6 ; GFX9-NEXT: .p2align 6
; GFX9-NEXT: .amdhsa_kernel stackrealign_attr ; GFX9-NEXT: .amdhsa_kernel stackrealign_attr
; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0 ; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
; GFX9-NEXT: .amdhsa_private_segment_fixed_size 8 ; GFX9-NEXT: .amdhsa_private_segment_fixed_size 8
; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1 ; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 ; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
Show All 37 Lines
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_add_u32 s4, s4, s7 ; VI-NEXT: s_add_u32 s4, s4, s7
; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8 ; VI-NEXT: s_lshr_b32 flat_scratch_hi, s4, 8
; VI-NEXT: s_add_u32 s0, s0, s7 ; VI-NEXT: s_add_u32 s0, s0, s7
; VI-NEXT: s_addc_u32 s1, s1, 0 ; VI-NEXT: s_addc_u32 s1, s1, 0
; VI-NEXT: v_mov_b32_e32 v0, 9 ; VI-NEXT: v_mov_b32_e32 v0, 9
; VI-NEXT: s_mov_b32 flat_scratch_lo, s5 ; VI-NEXT: s_mov_b32 flat_scratch_lo, s5
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
; VI-NEXT: .section .rodata,#alloc ; VI-NEXT: .section .rodata,#alloc
; VI-NEXT: .p2align 6 ; VI-NEXT: .p2align 6
; VI-NEXT: .amdhsa_kernel alignstack_attr ; VI-NEXT: .amdhsa_kernel alignstack_attr
; VI-NEXT: .amdhsa_group_segment_fixed_size 0 ; VI-NEXT: .amdhsa_group_segment_fixed_size 0
; VI-NEXT: .amdhsa_private_segment_fixed_size 128 ; VI-NEXT: .amdhsa_private_segment_fixed_size 128
; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1 ; VI-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 ; VI-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
Show All 30 Lines
; GFX9-LABEL: alignstack_attr: ; GFX9-LABEL: alignstack_attr:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7 ; GFX9-NEXT: s_add_u32 flat_scratch_lo, s4, s7
; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0 ; GFX9-NEXT: s_addc_u32 flat_scratch_hi, s5, 0
; GFX9-NEXT: s_add_u32 s0, s0, s7 ; GFX9-NEXT: s_add_u32 s0, s0, s7
; GFX9-NEXT: s_addc_u32 s1, s1, 0 ; GFX9-NEXT: s_addc_u32 s1, s1, 0
; GFX9-NEXT: v_mov_b32_e32 v0, 9 ; GFX9-NEXT: v_mov_b32_e32 v0, 9
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:4
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; GFX9-NEXT: .section .rodata,#alloc ; GFX9-NEXT: .section .rodata,#alloc
; GFX9-NEXT: .p2align 6 ; GFX9-NEXT: .p2align 6
; GFX9-NEXT: .amdhsa_kernel alignstack_attr ; GFX9-NEXT: .amdhsa_kernel alignstack_attr
; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0 ; GFX9-NEXT: .amdhsa_group_segment_fixed_size 0
; GFX9-NEXT: .amdhsa_private_segment_fixed_size 128 ; GFX9-NEXT: .amdhsa_private_segment_fixed_size 128
; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1 ; GFX9-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0 ; GFX9-NEXT: .amdhsa_user_sgpr_dispatch_ptr 0
Show All 38 Lines

llvm/test/CodeGen/AMDGPU/stack-realign.ll

Show First 20 Lines • Show All 159 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_mov_b64 exec, s[4:5] ; GCN-NEXT: s_mov_b64 exec, s[4:5]
; GCN-NEXT: v_writelane_b32 [[VGPR_REG]], s33, 2 ; GCN-NEXT: v_writelane_b32 [[VGPR_REG]], s33, 2
; GCN-DAG: v_writelane_b32 [[VGPR_REG]], s34, 3 ; GCN-DAG: v_writelane_b32 [[VGPR_REG]], s34, 3
; GCN-DAG: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0xffc0 ; GCN-DAG: s_add_u32 [[SCRATCH_REG:s[0-9]+]], s32, 0xffc0
; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xffff0000 ; GCN: s_and_b32 s33, [[SCRATCH_REG]], 0xffff0000
; GCN: s_mov_b32 s34, s32 ; GCN: s_mov_b32 s34, s32
; GCN: v_mov_b32_e32 v32, 0 ; GCN: v_mov_b32_e32 v32, 0
; GCN: buffer_store_dword v32, off, s[0:3], s33 offset:1024 ; GCN: buffer_store_dword v32, off, s[0:3], s33 offset:1024
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s34 ; GCN-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s34
; GCN-NEXT: s_add_u32 s32, s32, 0x30000 ; GCN-NEXT: s_add_u32 s32, s32, 0x30000
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s32
; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5] ; GCN-NEXT: s_swappc_b64 s[30:31], s[4:5]
; GCN: s_sub_u32 s32, s32, 0x30000 ; GCN: s_sub_u32 s32, s32, 0x30000
; GCN-NEXT: v_readlane_b32 s33, [[VGPR_REG]], 2 ; GCN-NEXT: v_readlane_b32 s33, [[VGPR_REG]], 2
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
define void @no_free_scratch_sgpr_for_bp_copy(<32 x i32> %a, i32 %b) #0 { define void @no_free_scratch_sgpr_for_bp_copy(<32 x i32> %a, i32 %b) #0 {
; GCN-LABEL: no_free_scratch_sgpr_for_bp_copy: ; GCN-LABEL: no_free_scratch_sgpr_for_bp_copy:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN: v_writelane_b32 [[VGPR_REG:v[0-9]+]], s34, 0 ; GCN: v_writelane_b32 [[VGPR_REG:v[0-9]+]], s34, 0
; GCN-NEXT: s_mov_b32 s34, s32 ; GCN-NEXT: s_mov_b32 s34, s32
; GCN-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s34 ; GCN-NEXT: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s34
; GCN: v_readlane_b32 s34, [[VGPR_REG:v[0-9]+]], 0 ; GCN: v_readlane_b32 s34, [[VGPR_REG:v[0-9]+]], 0
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s33 offset:128 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s33 offset:128
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ;;#ASMSTART ; GCN-NEXT: ;;#ASMSTART
; GCN-NEXT: ;;#ASMEND ; GCN-NEXT: ;;#ASMEND
; GCN: s_waitcnt vmcnt(0) ; GCN: s_setpc_b64 s[30:31]
; GCN-NEXT: s_setpc_b64 s[30:31]
%local_val = alloca i32, align 128, addrspace(5) %local_val = alloca i32, align 128, addrspace(5)
store volatile i32 %b, i32 addrspace(5)* %local_val, align 128 store volatile i32 %b, i32 addrspace(5)* %local_val, align 128
; Use all clobberable registers, so BP has to spill to a VGPR. ; Use all clobberable registers, so BP has to spill to a VGPR.
call void asm sideeffect "", call void asm sideeffect "",
"~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9} "~{s0},~{s1},~{s2},~{s3},~{s4},~{s5},~{s6},~{s7},~{s8},~{s9}
,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19} ,~{s10},~{s11},~{s12},~{s13},~{s14},~{s15},~{s16},~{s17},~{s18},~{s19}
,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29} ,~{s20},~{s21},~{s22},~{s23},~{s24},~{s25},~{s26},~{s27},~{s28},~{s29}
,~{vcc_hi}"() #0 ,~{vcc_hi}"() #0
▲ Show 20 Lines • Show All 78 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/store-hi16.ll

Show First 20 Lines • Show All 640 Lines • ▼ Show 20 Linesentry:
%gep = getelementptr inbounds i16, i16 addrspace(3)* %out, i64 32767 %gep = getelementptr inbounds i16, i16 addrspace(3)* %out, i64 32767
store i16 %hi, i16 addrspace(3)* %gep store i16 %hi, i16 addrspace(3)* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_v2i16_to_offset: ; GCN-LABEL: {{^}}store_private_hi_v2i16_to_offset:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX900-MUBUF: buffer_store_dword ; GFX900-MUBUF: buffer_store_dword
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s32 offset:4094 ; GFX900-MUBUF-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s32 offset:4094
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR: scratch_store_dword ; GFX900-FLATSCR: scratch_store_dword
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_store_short_d16_hi off, v0, s32 offset:4094 ; GFX900-FLATSCR-NEXT: scratch_store_short_d16_hi off, v0, s32 offset:4094
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
define void @store_private_hi_v2i16_to_offset(i32 %arg) #0 { define void @store_private_hi_v2i16_to_offset(i32 %arg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i16], align 2, addrspace(5) %obj1 = alloca [4096 x i16], align 2, addrspace(5)
%bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32 addrspace(5)* %bc store volatile i32 123, i32 addrspace(5)* %bc
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2027 %gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2027
store i16 %hi, i16 addrspace(5)* %gep store i16 %hi, i16 addrspace(5)* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_v2i16_i8_to_offset: ; GCN-LABEL: {{^}}store_private_hi_v2i16_i8_to_offset:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX900-MUBUF: buffer_store_dword ; GFX900-MUBUF: buffer_store_dword
; GFX900-MUBUF-NEXT: s_waitcnt vmcnt(0)
; GFX900-MUBUF-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s32 offset:4095 ; GFX900-MUBUF-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s32 offset:4095
; GFX900-FLATSCR: scratch_store_dword ; GFX900-FLATSCR: scratch_store_dword
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
; GFX900-FLATSCR-NEXT: scratch_store_byte_d16_hi off, v0, s32 offset:4095 ; GFX900-FLATSCR-NEXT: scratch_store_byte_d16_hi off, v0, s32 offset:4095
; GFX900-FLATSCR-NEXT: s_waitcnt vmcnt(0)
define void @store_private_hi_v2i16_i8_to_offset(i32 %arg) #0 { define void @store_private_hi_v2i16_i8_to_offset(i32 %arg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4, addrspace(5) %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2, addrspace(5) %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32 addrspace(5)* %bc store volatile i32 123, i32 addrspace(5)* %bc
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4055
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
store i8 %trunc, i8 addrspace(5)* %gep store i8 %trunc, i8 addrspace(5)* %gep
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

llvm/test/CodeGen/AMDGPU/sub.v2i16.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,GFX9 ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,GFX9
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,VI ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,VI
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @v_test_sub_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_sub_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
; GFX9-LABEL: v_test_sub_v2i16: ; GFX9-LABEL: v_test_sub_v2i16:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] ; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
; GFX9-NEXT: global_load_dword v0, v0, s[8:9]
; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v0, v0, s[8:9] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: v_pk_sub_i16 v0, v1, v0 ; GFX9-NEXT: v_pk_sub_i16 v0, v1, v0
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16: ; VI-LABEL: v_test_sub_v2i16:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_sub_u16_e32 v2, v0, v1 ; VI-NEXT: v_sub_u16_e32 v2, v0, v1
; VI-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_or_b32_e32 v0, v2, v0 ; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @v_test_sub_v2i16_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { define amdgpu_kernel void @v_test_sub_v2i16_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
; GFX9-LABEL: v_test_sub_v2i16_constant: ; GFX9-LABEL: v_test_sub_v2i16_constant:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v0, v0, s[6:7] ; GFX9-NEXT: global_load_dword v0, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s4, 0x1c8007b ; GFX9-NEXT: s_mov_b32 s4, 0x1c8007b
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_constant: ; VI-LABEL: v_test_sub_v2i16_constant:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, 0xfffffe38 ; VI-NEXT: v_mov_b32_e32 v1, 0xfffffe38
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_u16_e32 v2, 0xff85, v0 ; VI-NEXT: v_add_u16_e32 v2, 0xff85, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v2, v0 ; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = sub <2 x i16> %a, <i16 123, i16 456> %add = sub <2 x i16> %a, <i16 123, i16 456>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @v_test_sub_v2i16_neg_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { define amdgpu_kernel void @v_test_sub_v2i16_neg_constant(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
; GFX9-LABEL: v_test_sub_v2i16_neg_constant: ; GFX9-LABEL: v_test_sub_v2i16_neg_constant:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v0, v0, s[6:7] ; GFX9-NEXT: global_load_dword v0, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s4, 0xfc21fcb3 ; GFX9-NEXT: s_mov_b32 s4, 0xfc21fcb3
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_neg_constant: ; VI-LABEL: v_test_sub_v2i16_neg_constant:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, 0x3df ; VI-NEXT: v_mov_b32_e32 v1, 0x3df
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_u16_e32 v2, 0x34d, v0 ; VI-NEXT: v_add_u16_e32 v2, 0x34d, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v2, v0 ; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = sub <2 x i16> %a, <i16 -845, i16 -991> %add = sub <2 x i16> %a, <i16 -845, i16 -991>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @v_test_sub_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { define amdgpu_kernel void @v_test_sub_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
; GFX9-LABEL: v_test_sub_v2i16_inline_neg1: ; GFX9-LABEL: v_test_sub_v2i16_inline_neg1:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v0, v0, s[6:7] ; GFX9-NEXT: global_load_dword v0, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, -1 op_sel_hi:[1,0] ; GFX9-NEXT: v_pk_sub_i16 v0, v0, -1 op_sel_hi:[1,0]
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_inline_neg1: ; VI-LABEL: v_test_sub_v2i16_inline_neg1:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, 1 ; VI-NEXT: v_mov_b32_e32 v1, 1
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_u16_e32 v2, 1, v0 ; VI-NEXT: v_add_u16_e32 v2, 1, v0
; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_e32 v0, v2, v0 ; VI-NEXT: v_or_b32_e32 v0, v2, v0
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = sub <2 x i16> %a, <i16 -1, i16 -1> %add = sub <2 x i16> %a, <i16 -1, i16 -1>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @v_test_sub_v2i16_inline_lo_zero_hi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { define amdgpu_kernel void @v_test_sub_v2i16_inline_lo_zero_hi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
; GFX9-LABEL: v_test_sub_v2i16_inline_lo_zero_hi: ; GFX9-LABEL: v_test_sub_v2i16_inline_lo_zero_hi:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v0, v0, s[6:7] ; GFX9-NEXT: global_load_dword v0, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, 32 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, 32
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_inline_lo_zero_hi: ; VI-LABEL: v_test_sub_v2i16_inline_lo_zero_hi:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s3 ; VI-NEXT: v_mov_b32_e32 v1, s3
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0 ; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
; VI-NEXT: v_subrev_u16_e32 v0, 32, v0 ; VI-NEXT: v_subrev_u16_e32 v0, 32, v0
; VI-NEXT: v_or_b32_e32 v0, v0, v1 ; VI-NEXT: v_or_b32_e32 v0, v0, v1
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = sub <2 x i16> %a, <i16 32, i16 0> %add = sub <2 x i16> %a, <i16 32, i16 0>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; The high element gives fp ; The high element gives fp
define amdgpu_kernel void @v_test_sub_v2i16_inline_fp_split(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { define amdgpu_kernel void @v_test_sub_v2i16_inline_fp_split(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
; GFX9-LABEL: v_test_sub_v2i16_inline_fp_split: ; GFX9-LABEL: v_test_sub_v2i16_inline_fp_split:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_mov_b32 s3, 0xf000 ; GFX9-NEXT: s_mov_b32 s3, 0xf000
; GFX9-NEXT: s_mov_b32 s2, -1 ; GFX9-NEXT: s_mov_b32 s2, -1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v0, v0, s[6:7] ; GFX9-NEXT: global_load_dword v0, v0, s[6:7] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s4 ; GFX9-NEXT: s_mov_b32 s0, s4
; GFX9-NEXT: s_mov_b32 s4, 1.0 ; GFX9-NEXT: s_mov_b32 s4, 1.0
; GFX9-NEXT: s_mov_b32 s1, s5 ; GFX9-NEXT: s_mov_b32 s1, s5
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4 ; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_inline_fp_split: ; VI-LABEL: v_test_sub_v2i16_inline_fp_split:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; VI-NEXT: s_mov_b32 s3, 0xf000 ; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_mov_b32 s2, -1
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v0
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, 0xffffc080 ; VI-NEXT: v_mov_b32_e32 v1, 0xffffc080
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_add_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD ; VI-NEXT: v_add_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = sub <2 x i16> %a, <i16 0, i16 16256> %add = sub <2 x i16> %a, <i16 0, i16 16256>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i32: ; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] ; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
; GFX9-NEXT: global_load_dword v0, v0, s[0:1] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v0, v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v1, v0 ; GFX9-NEXT: v_pk_sub_i16 v0, v1, v0
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0 ; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_zext_to_v2i32: ; VI-LABEL: v_test_sub_v2i16_zext_to_v2i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v1, v[0:1] ; VI-NEXT: flat_load_dword v1, v[0:1] glc
; VI-NEXT: flat_load_dword v2, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_sub_u16_e32 v0, v1, v2 ; VI-NEXT: v_sub_u16_e32 v0, v1, v2
; VI-NEXT: v_sub_u16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_sub_u16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
Show All 10 Lines
; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i64: ; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: v_mov_b32_e32 v1, 0 ; GFX9-NEXT: v_mov_b32_e32 v1, 0
; GFX9-NEXT: v_mov_b32_e32 v3, v1 ; GFX9-NEXT: v_mov_b32_e32 v3, v1
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v2, v0, s[6:7] ; GFX9-NEXT: global_load_dword v2, v0, s[6:7] glc
; GFX9-NEXT: global_load_dword v0, v0, s[0:1] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v0, v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v2, v2, v0 ; GFX9-NEXT: v_pk_sub_i16 v2, v2, v0
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2 ; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v2
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_zext_to_v2i64: ; VI-LABEL: v_test_sub_v2i16_zext_to_v2i64:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v4, v[0:1] ; VI-NEXT: flat_load_dword v4, v[0:1] glc
; VI-NEXT: flat_load_dword v2, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v2, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, 0 ; VI-NEXT: v_mov_b32_e32 v1, 0
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: v_mov_b32_e32 v3, v1 ; VI-NEXT: v_mov_b32_e32 v3, v1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_sub_u16_e32 v0, v4, v2 ; VI-NEXT: v_sub_u16_e32 v0, v4, v2
; VI-NEXT: v_sub_u16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_sub_u16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 ; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i64>, <2 x i64> addrspace(1)* %out, i32 %tid
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid %gep.in1 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in1, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1 %b = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in1
%add = sub <2 x i16> %a, %b %add = sub <2 x i16> %a, %b
%ext = zext <2 x i16> %add to <2 x i64> %ext = zext <2 x i16> %add to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FIXME: Need to handle non-uniform case for function below (load without gep). ; FIXME: Need to handle non-uniform case for function below (load without gep).
define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 { define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0, <2 x i16> addrspace(1)* %in1) #1 {
; GFX9-LABEL: v_test_sub_v2i16_sext_to_v2i32: ; GFX9-LABEL: v_test_sub_v2i16_sext_to_v2i32:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX9-NEXT: s_waitcnt lgkmcnt(0) ; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] ; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
; GFX9-NEXT: global_load_dword v0, v0, s[0:1] ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: global_load_dword v0, v0, s[0:1] glc
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_mov_b32 s7, 0xf000 ; GFX9-NEXT: s_mov_b32 s7, 0xf000
; GFX9-NEXT: s_mov_b32 s6, -1 ; GFX9-NEXT: s_mov_b32 s6, -1
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_pk_sub_i16 v0, v1, v0 ; GFX9-NEXT: v_pk_sub_i16 v0, v1, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 16, v0 ; GFX9-NEXT: v_ashrrev_i32_e32 v1, 16, v0
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16 ; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; GFX9-NEXT: s_endpgm ; GFX9-NEXT: s_endpgm
; ;
; VI-LABEL: v_test_sub_v2i16_sext_to_v2i32: ; VI-LABEL: v_test_sub_v2i16_sext_to_v2i32:
; VI: ; %bb.0: ; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 ; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 ; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0 ; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v1, s7 ; VI-NEXT: v_mov_b32_e32 v1, s7
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2 ; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_mov_b32_e32 v3, s1 ; VI-NEXT: v_mov_b32_e32 v3, s1
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2 ; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc ; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; VI-NEXT: flat_load_dword v0, v[0:1] ; VI-NEXT: flat_load_dword v0, v[0:1] glc
; VI-NEXT: flat_load_dword v1, v[2:3] ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: flat_load_dword v1, v[2:3] glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: s_mov_b32 s7, 0xf000 ; VI-NEXT: s_mov_b32 s7, 0xf000
; VI-NEXT: s_mov_b32 s6, -1 ; VI-NEXT: s_mov_b32 s6, -1
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_sub_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 ; VI-NEXT: v_sub_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
; VI-NEXT: v_sub_u16_e32 v0, v0, v1 ; VI-NEXT: v_sub_u16_e32 v0, v0, v1
; VI-NEXT: v_bfe_i32 v0, v0, 0, 16 ; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
; VI-NEXT: v_bfe_i32 v1, v2, 0, 16 ; VI-NEXT: v_bfe_i32 v1, v2, 0, 16
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid %gep.out = getelementptr inbounds <2 x i32>, <2 x i32> addrspace(1)* %out, i32 %tid
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll

Show All 38 Lines
; FIXME: Extra undef subregister copy should be removed before ; FIXME: Extra undef subregister copy should be removed before
; overwritten with defined copy ; overwritten with defined copy
define amdgpu_ps float @valley_partially_undef_copy() #0 { define amdgpu_ps float @valley_partially_undef_copy() #0 {
; CHECK-LABEL: valley_partially_undef_copy: ; CHECK-LABEL: valley_partially_undef_copy:
; CHECK: ; %bb.0: ; %bb ; CHECK: ; %bb.0: ; %bb
; CHECK-NEXT: s_mov_b32 s3, 0xf000 ; CHECK-NEXT: s_mov_b32 s3, 0xf000
; CHECK-NEXT: s_mov_b32 s2, -1 ; CHECK-NEXT: s_mov_b32 s2, -1
; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], 0 ; CHECK-NEXT: buffer_load_dword v1, off, s[0:3], 0 glc
; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], 0 ; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: buffer_load_dword v0, off, s[0:3], 0 glc
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc00000 ; CHECK-NEXT: v_mov_b32_e32 v2, 0x7fc00000
; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 0 ; CHECK-NEXT: buffer_store_dword v2, off, s[0:3], 0
; CHECK-NEXT: s_waitcnt vmcnt(1)
; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1 ; CHECK-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v1
; CHECK-NEXT: BB1_1: ; %bb9 ; CHECK-NEXT: BB1_1: ; %bb9
; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
; CHECK-NEXT: s_andn2_b64 vcc, exec, s[0:1] ; CHECK-NEXT: s_andn2_b64 vcc, exec, s[0:1]
; CHECK-NEXT: s_cbranch_vccnz BB1_1 ; CHECK-NEXT: s_cbranch_vccnz BB1_1
; CHECK-NEXT: ; %bb.2: ; %bb11 ; CHECK-NEXT: ; %bb.2: ; %bb11
; CHECK-NEXT: s_mov_b32 s3, 0xf000 ; CHECK-NEXT: s_mov_b32 s3, 0xf000
Show All 37 Lines
; CHECK-NEXT: v_mov_b32_e32 v0, v5 ; CHECK-NEXT: v_mov_b32_e32 v0, v5
; CHECK-NEXT: v_mov_b32_e32 v1, v6 ; CHECK-NEXT: v_mov_b32_e32 v1, v6
; CHECK-NEXT: v_mov_b32_e32 v2, v7 ; CHECK-NEXT: v_mov_b32_e32 v2, v7
; CHECK-NEXT: v_mov_b32_e32 v3, v8 ; CHECK-NEXT: v_mov_b32_e32 v3, v8
; CHECK-NEXT: s_mov_b32 s3, 0xf000 ; CHECK-NEXT: s_mov_b32 s3, 0xf000
; CHECK-NEXT: s_mov_b32 s2, -1 ; CHECK-NEXT: s_mov_b32 s2, -1
; CHECK-NEXT: v_mov_b32_e32 v0, v6 ; CHECK-NEXT: v_mov_b32_e32 v0, v6
; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; CHECK-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; CHECK-NEXT: s_waitcnt vmcnt(0)
; CHECK-NEXT: ;;#ASMSTART ; CHECK-NEXT: ;;#ASMSTART
; CHECK-NEXT: v_nop ; CHECK-NEXT: v_nop
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
; CHECK-NEXT: s_endpgm ; CHECK-NEXT: s_endpgm
%tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"() %tmp0 = call i32 asm sideeffect "v_mov_b32_e32 v5, 5", "={v5}"()
%tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"() %tmp1 = call i32 asm sideeffect "v_mov_b32_e32 v6, 6", "={v6}"()
%partially.undef.0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0 %partially.undef.0 = insertelement <4 x i32> undef, i32 %tmp0, i32 0
Show All 11 Lines

llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll

Show All 36 Linesdefine amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, float %a, float %b) #0 {
%fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1 %fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1
store float %fma, float addrspace(1)* %out, align 4 store float %fma, float addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}test_use_s_v_s: ; GCN-LABEL: {{^}}test_use_s_v_s:
; GCN-DAG: s_load_dwordx2 s{{\[}}[[SA:[0-9]+]]:[[SB:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}} ; GCN-DAG: s_load_dwordx2 s{{\[}}[[SA:[0-9]+]]:[[SB:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
; SI: buffer_load_dword [[VA0:v[0-9]+]] ; SI: buffer_load_dword [[VA0:v[0-9]+]]
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_dword [[VA1:v[0-9]+]] ; SI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]
; SI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOT: v_mov_b32 ; GCN-NOT: v_mov_b32
; VI: buffer_load_dword [[VA0:v[0-9]+]] ; VI: buffer_load_dword [[VA0:v[0-9]+]]
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_dword [[VA1:v[0-9]+]] ; VI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]
; VI-NEXT: s_waitcnt vmcnt(0)
; GCN-NOT: v_mov_b32 ; GCN-NOT: v_mov_b32
; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[SB]] ; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[SB]]
; GCN-NOT: v_mov_b32 ; GCN-NOT: v_mov_b32
; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SA]], [[VA0]], [[VB]] ; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SA]], [[VA0]], [[VB]]
; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SA]], [[VA1]], [[VB]] ; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SA]], [[VA1]], [[VB]]
; GCN: buffer_store_dword [[RESULT0]] ; GCN: buffer_store_dword [[RESULT0]]
▲ Show 20 Lines • Show All 214 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/v_mac.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=+mad-mac-f32-insts -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck --check-prefixes=SI,GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mattr=+mad-mac-f32-insts -denormal-fp-math-f32=preserve-sign -verify-machineinstrs < %s | FileCheck --check-prefixes=SI,GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=VI-FLUSH,GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -denormal-fp-math=preserve-sign -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=VI-FLUSH,GCN %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -denormal-fp-math=ieee -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -denormal-fp-math=ieee -denormal-fp-math-f32=preserve-sign -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}mac_vvv: ; GCN-LABEL: {{^}}mac_vvv:
; GCN: buffer_load_dword [[A:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0{{$}} ; GCN: buffer_load_dword [[A:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 glc{{$}}
; GCN: buffer_load_dword [[B:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:4 ; GCN: buffer_load_dword [[B:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:4
; GCN: buffer_load_dword [[C:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8 ; GCN: buffer_load_dword [[C:v[0-9]+]], off, s[{{[0-9]+:[0-9]+}}], 0 offset:8
; GCN: v_mac_f32_e32 [[C]], [[A]], [[B]] ; GCN: v_mac_f32_e32 [[C]], [[A]], [[B]]
; GCN: buffer_store_dword [[C]] ; GCN: buffer_store_dword [[C]]
define amdgpu_kernel void @mac_vvv(float addrspace(1)* %out, float addrspace(1)* %in) #0 { define amdgpu_kernel void @mac_vvv(float addrspace(1)* %out, float addrspace(1)* %in) #0 {
entry: entry:
%b_ptr = getelementptr float, float addrspace(1)* %in, i32 1 %b_ptr = getelementptr float, float addrspace(1)* %in, i32 1
%c_ptr = getelementptr float, float addrspace(1)* %in, i32 2 %c_ptr = getelementptr float, float addrspace(1)* %in, i32 2
▲ Show 20 Lines • Show All 273 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/v_madak_f16.ll

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
; SI-NEXT: s_mov_b32 s17, s9 ; SI-NEXT: s_mov_b32 s17, s9
; SI-NEXT: s_mov_b32 s19, s3 ; SI-NEXT: s_mov_b32 s19, s3
; SI-NEXT: s_mov_b32 s8, s10 ; SI-NEXT: s_mov_b32 s8, s10
; SI-NEXT: s_mov_b32 s9, s11 ; SI-NEXT: s_mov_b32 s9, s11
; SI-NEXT: s_mov_b32 s10, s2 ; SI-NEXT: s_mov_b32 s10, s2
; SI-NEXT: s_mov_b32 s11, s3 ; SI-NEXT: s_mov_b32 s11, s3
; SI-NEXT: s_mov_b32 s14, s2 ; SI-NEXT: s_mov_b32 s14, s2
; SI-NEXT: s_mov_b32 s15, s3 ; SI-NEXT: s_mov_b32 s15, s3
; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 ; SI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 glc
; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0 ; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: buffer_load_ushort v2, off, s[12:15], 0 glc
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_mov_b32_e32 v3, 0x41200000 ; SI-NEXT: v_mov_b32_e32 v3, 0x41200000
; SI-NEXT: s_mov_b32 s0, s4 ; SI-NEXT: s_mov_b32 s0, s4
; SI-NEXT: s_mov_b32 s1, s5 ; SI-NEXT: s_mov_b32 s1, s5
; SI-NEXT: s_mov_b32 s8, s6 ; SI-NEXT: s_mov_b32 s8, s6
; SI-NEXT: s_mov_b32 s9, s7 ; SI-NEXT: s_mov_b32 s9, s7
; SI-NEXT: s_waitcnt vmcnt(2)
; SI-NEXT: v_cvt_f32_f16_e32 v0, v0 ; SI-NEXT: v_cvt_f32_f16_e32 v0, v0
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_cvt_f32_f16_e32 v1, v1 ; SI-NEXT: v_cvt_f32_f16_e32 v1, v1
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_cvt_f32_f16_e32 v2, v2 ; SI-NEXT: v_cvt_f32_f16_e32 v2, v2
; SI-NEXT: v_madak_f32 v1, v0, v1, 0x41200000 ; SI-NEXT: v_madak_f32 v1, v0, v1, 0x41200000
; SI-NEXT: v_mac_f32_e32 v3, v0, v2 ; SI-NEXT: v_mac_f32_e32 v3, v0, v2
; SI-NEXT: v_cvt_f16_f32_e32 v0, v1 ; SI-NEXT: v_cvt_f16_f32_e32 v0, v1
; SI-NEXT: v_cvt_f16_f32_e32 v1, v3 ; SI-NEXT: v_cvt_f16_f32_e32 v1, v3
; SI-NEXT: buffer_store_short v0, off, s[0:3], 0 ; SI-NEXT: buffer_store_short v0, off, s[0:3], 0
; SI-NEXT: buffer_store_short v1, off, s[8:11], 0 ; SI-NEXT: buffer_store_short v1, off, s[8:11], 0
; SI-NEXT: s_endpgm ; SI-NEXT: s_endpgm
Show All 10 Lines
; VI-NEXT: s_mov_b32 s17, s9 ; VI-NEXT: s_mov_b32 s17, s9
; VI-NEXT: s_mov_b32 s19, s3 ; VI-NEXT: s_mov_b32 s19, s3
; VI-NEXT: s_mov_b32 s8, s10 ; VI-NEXT: s_mov_b32 s8, s10
; VI-NEXT: s_mov_b32 s9, s11 ; VI-NEXT: s_mov_b32 s9, s11
; VI-NEXT: s_mov_b32 s10, s2 ; VI-NEXT: s_mov_b32 s10, s2
; VI-NEXT: s_mov_b32 s11, s3 ; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_mov_b32 s14, s2 ; VI-NEXT: s_mov_b32 s14, s2
; VI-NEXT: s_mov_b32 s15, s3 ; VI-NEXT: s_mov_b32 s15, s3
; VI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 ; VI-NEXT: buffer_load_ushort v0, off, s[16:19], 0 glc
; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 ; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[12:15], 0 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: buffer_load_ushort v2, off, s[12:15], 0 glc
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mov_b32_e32 v3, 0x4900 ; VI-NEXT: v_mov_b32_e32 v3, 0x4900
; VI-NEXT: s_mov_b32 s0, s4 ; VI-NEXT: s_mov_b32 s0, s4
; VI-NEXT: s_mov_b32 s1, s5 ; VI-NEXT: s_mov_b32 s1, s5
; VI-NEXT: s_mov_b32 s8, s6 ; VI-NEXT: s_mov_b32 s8, s6
; VI-NEXT: s_mov_b32 s9, s7 ; VI-NEXT: s_mov_b32 s9, s7
; VI-NEXT: s_waitcnt vmcnt(1)
; VI-NEXT: v_madak_f16 v1, v0, v1, 0x4900 ; VI-NEXT: v_madak_f16 v1, v0, v1, 0x4900
; VI-NEXT: s_waitcnt vmcnt(0)
; VI-NEXT: v_mac_f16_e32 v3, v0, v2 ; VI-NEXT: v_mac_f16_e32 v3, v0, v2
; VI-NEXT: buffer_store_short v1, off, s[0:3], 0 ; VI-NEXT: buffer_store_short v1, off, s[0:3], 0
; VI-NEXT: buffer_store_short v3, off, s[8:11], 0 ; VI-NEXT: buffer_store_short v3, off, s[8:11], 0
; VI-NEXT: s_endpgm ; VI-NEXT: s_endpgm
half addrspace(1)* %r0, half addrspace(1)* %r0,
half addrspace(1)* %r1, half addrspace(1)* %r1,
half addrspace(1)* %a, half addrspace(1)* %a,
half addrspace(1)* %b, half addrspace(1)* %b,
Show All 17 Lines

llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll

Show First 20 Lines • Show All 108 Lines • ▼ Show 20 Lines
; GCN-NEXT: v_mov_b32_e32 v2, 0 ; GCN-NEXT: v_mov_b32_e32 v2, 0
; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, 0 ; GCN-NEXT: s_mov_b32 s2, 0
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_mov_b64 s[0:1], s[6:7] ; GCN-NEXT: s_mov_b64 s[0:1], s[6:7]
; GCN-NEXT: v_lshlrev_b32_e32 v1, 4, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v1, 4, v0
; GCN-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; GCN-NEXT: v_lshlrev_b32_e32 v4, 2, v0
; GCN-NEXT: v_mov_b32_e32 v5, v2 ; GCN-NEXT: v_mov_b32_e32 v5, v2
; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 addr64 ; GCN-NEXT: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 addr64 glc
; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_mov_b64 s[6:7], s[2:3]
; GCN-NEXT: v_mov_b32_e32 v0, s8 ; GCN-NEXT: v_mov_b32_e32 v0, s8
; GCN-NEXT: buffer_store_dword v0, v[4:5], s[4:7], 0 addr64 ; GCN-NEXT: buffer_store_dword v0, v[4:5], s[4:7], 0 addr64
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%id.ext = sext i32 %id to i64 %id.ext = sext i32 %id to i64
%gep.in = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in, i64 %id.ext %gep.in = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %in, i64 %id.ext
%gep.out = getelementptr inbounds float, float addrspace(1)* %out, i64 %id.ext %gep.out = getelementptr inbounds float, float addrspace(1)* %out, i64 %id.ext
%vec = load volatile <4 x float>, <4 x float> addrspace(1)* %gep.in %vec = load volatile <4 x float>, <4 x float> addrspace(1)* %gep.in
%insert = insertelement <4 x float> %vec, float %val, i32 %idx %insert = insertelement <4 x float> %vec, float %val, i32 %idx
%extract = extractelement <4 x float> %insert, i32 %idx %extract = extractelement <4 x float> %insert, i32 %idx
store float %extract, float addrspace(1)* %gep.out store float %extract, float addrspace(1)* %gep.out
ret void ret void
} }
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }