[X86] Add TLBSYNC, INVLPGB and SNP instructions

[GGanesh]

Summary

This patch adds the AMD znver3 instructions INVLPGB, TLBSYNC and SNP. Tests are also added. These instructions needs to be included for znver3 features after adding Scheduler descriptions.

[craig.topper]

llvm/lib/Target/X86/X86InstrInfo.td

965

These feature flags should probably only be here if intrinsics are added. Without that nothing will ever check the features.

2937

TB should be PS since we have XD and XS instructions that use the same opcode. TB is supposed to indicate that 0xf2/0xf3 prefixes don't effect the instruction.

2954

TB should be PS since we have XD and XS opcodes.

llvm/lib/Target/X86/X86InstrSNP.td

21

Should this have In64BitMode in the requires field?

35

Same here

40

And here

[pengfei]

llvm/test/MC/Disassembler/X86/x86-32.txt

1013–1017

Are they 64 bit only instructions?

[GGanesh]

Updated the patch for the review comments from @craig.topper and @pengfei

1. The instructions are updated for prefix specifiers
2. Except for pvalidate all the SNP instructions are valid only in 64-bit environment. Corrected the test accordingly.
3. The modes (In64BitMode, In64BitMode) are updated in Instruction description.

[craig.topper]

LGTM

llvm/lib/Target/X86/X86InstrInfo.td

 def HasRDSEED    : Predicate<"Subtarget->hasRDSEED()">;
 def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
 def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
 def HasPrefetchW : Predicate<"Subtarget->hasPrefetchW()">;
 def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">;
 def HasLAHFSAHF  : Predicate<"Subtarget->hasLAHFSAHF()">;
 def HasMWAITX    : Predicate<"Subtarget->hasMWAITX()">;
 def HasCLZERO    : Predicate<"Subtarget->hasCLZERO()">;
+def HasINVLPGB   : Predicate<"Subtarget->hasINVLPGB()">;
+def HasTLBSYNC   : Predicate<"Subtarget->hasTLBSYNC()">;
 def HasCLDEMOTE  : Predicate<"Subtarget->hasCLDEMOTE()">;
 def HasMOVDIRI   : Predicate<"Subtarget->hasMOVDIRI()">;
 def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">;
 def HasPTWRITE   : Predicate<"Subtarget->hasPTWRITE()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
 def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
let SchedRW = [WriteLoad] in {
   def CLZERO64r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>,
                   TB, Requires<[HasCLZERO, In64BitMode]>;
 } // SchedRW
 
 def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;
 def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
 
 //===----------------------------------------------------------------------===//
+// INVLPGB Instruction
+// OPCODE 0F 01 FE
+//
+let SchedRW = [WriteSystem] in {
+  let Uses = [EAX, EDX] in
+  def INVLPGB32 : I<0x01, MRM_FE, (outs), (ins),
+                  "invlpgb}", []>,
+                  TB, Requires<[HasINVLPGB, Not64BitMode]>;
+  let Uses = [RAX, EDX] in
+  def INVLPGB64 : I<0x01, MRM_FE, (outs), (ins),
+                  "invlpgb", []>,
+                  TB, Requires<[HasINVLPGB, In64BitMode]>;
+} // SchedRW
+
+def : InstAlias<"invlpgb\t{%eax, %edx|eax, edx}", (INVLPGB32)>, Requires<[Not64BitMode]>;
+def : InstAlias<"invlpgb\t{%rax, %edx|rax, edx}", (INVLPGB64)>, Requires<[In64BitMode]>;
+
+//===----------------------------------------------------------------------===//
+// TLBSYNC Instruction
+// OPCODE 0F 01 FF
+//
+let SchedRW = [WriteSystem] in {
+  def TLBSYNC   : I<0x01, MRM_FF, (outs), (ins),
+                  "tlbsync", []>,
+                  TB, Requires<[HasTLBSYNC]>;
+} // SchedRW
+
+//===----------------------------------------------------------------------===//
 // HRESET Instruction
 //
 let Uses = [EAX], SchedRW = [WriteSystem] in
   def HRESET : Ii8<0xF0, MRM_C0, (outs), (ins i32u8imm:$imm), "hreset\t$imm", []>,
                    Requires<[HasHRESET]>, TAXS;
 
 //===----------------------------------------------------------------------===//
 // SERIALIZE Instruction

 include "X86InstrMMX.td"
 include "X86Instr3DNow.td"
 
 // MPX instructions
 include "X86InstrMPX.td"
 
 include "X86InstrVMX.td"
 include "X86InstrSVM.td"
+include "X86InstrSNP.td"
 
 include "X86InstrTSX.td"
 include "X86InstrSGX.td"
 
 include "X86InstrTDX.td"
 
 // Key Locker instructions
 include "X86InstrKL.td"

llvm/lib/Target/X86/X86InstrSNP.td

+//===-- X86InstrSNP.td - SNP Instruction Set Extension -----*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions that make up the AMD Secure Nested
+// Paging (SNP) instruction set.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// SNP instructions
+
+let SchedRW = [WriteSystem] in {
+// F3 0F 01 FF
+let Uses = [RAX] in
+def PSMASH: I<0x01, MRM_FF, (outs), (ins), "psmash", []>, XS,
+            Requires<[]>;
+
+// F2 0F 01 FF
+let Uses = [RAX] in
+def PVALIDATE64: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>,
+                 XD, Requires<[In64BitMode]>;
+
+let Uses = [EAX] in
+def PVALIDATE32: I<0x01, MRM_FF, (outs), (ins), "pvalidate",[]>,
+                 XD, Requires<[Not64BitMode]>;
+
+// F2 0F 01 FE
+let Uses = [RAX] in
+def RMPUPDATE: I<0x01, MRM_FE, (outs), (ins), "rmpupdate", []>, XD,
+               Requires<[]>;
+
+// F3 0F 01 FE
+let Uses = [RAX] in
+def RMPADJUST: I<0x01, MRM_FE, (outs), (ins), "rmpadjust", []>, XS,
+               Requires<[]>;
+} // SchedRW
+
+def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>;
+def : InstAlias<"pvalidate\t{%rax|rax}", (PVALIDATE64)>, Requires<[In64BitMode]>;
+def : InstAlias<"pvalidate\t{%eax|eax}", (PVALIDATE32)>, Requires<[Not64BitMode]>;
+def : InstAlias<"rmpupdate\t{%rax|rax}", (RMPUPDATE)>, Requires<[In64BitMode]>;
+def : InstAlias<"rmpadjust\t{%rax|rax}", (RMPADJUST)>, Requires<[In64BitMode]>;

llvm/lib/Target/X86/X86Subtarget.h

class X86Subtarget final : public X86GenSubtargetInfo {
   bool HasLAHFSAHF64 = false;
 
   /// Processor has MONITORX/MWAITX instructions.
   bool HasMWAITX = false;
 
   /// Processor has Cache Line Zero instruction
   bool HasCLZERO = false;
 
+  /// Processor has INVLPGB instruction.
+  bool HasINVLPGB = false;
+
+  /// Processor has TLBYSNC instruction.
+  bool HasTLBYSNC = false;
+
   /// Processor has Cache Line Demote instruction
   bool HasCLDEMOTE = false;
 
   /// Processor has MOVDIRI instruction (direct store integer).
   bool HasMOVDIRI = false;
 
   /// Processor has MOVDIR64B instruction (direct store 64 bytes).
   bool HasMOVDIR64B = false;
bool hasSSEPrefetch() const {
     // level OR if we have prfchw, but don't already have a read prefetch from
     // 3dnow.
     return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
   }
   bool hasRDSEED() const { return HasRDSEED; }
   bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); }
   bool hasMWAITX() const { return HasMWAITX; }
   bool hasCLZERO() const { return HasCLZERO; }
+  bool hasINVLPGB() const { return HasINVLPGB; }
   bool hasCLDEMOTE() const { return HasCLDEMOTE; }
   bool hasMOVDIRI() const { return HasMOVDIRI; }
   bool hasMOVDIR64B() const { return HasMOVDIR64B; }
   bool hasPTWRITE() const { return HasPTWRITE; }
   bool isSHLDSlow() const { return IsSHLDSlow; }
   bool isPMULLDSlow() const { return IsPMULLDSlow; }
   bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }

llvm/test/MC/Disassembler/X86/x86-32.txt

 0x0f 0x01 0xde
 
 # CHECK: invlpga
 0x0f 0x01 0xdf
 
 # CHECK: clzero
 0x0f,0x01,0xfc
 
+# CHECK: tlbsync
+0x0f,0x01,0xff
+
 # CHECK: movl $0, -4(%ebp)
 0xc7 0x45 0xfc 0x00 0x00 0x00 0x00
 
 # CHECK: movl %cr0, %ecx
 0x0f 0x20 0xc1
 
 # CHECK: leal 4(%esp), %ecx
 0x8d 0x4c 0x24 0x04 

 0x0f 0x01 0xe8
 
 # CHECK: xsusldtrk
 0xf2 0x0f 0x01 0xe8
 
 # CHECK: xresldtrk
 0xf2 0x0f 0x01 0xe9
 
+# CHECK: psmash
+0xf3 0x0f 0x01 0xff
+
+# CHECK: pvalidate
+0xf2 0x0f 0x01 0xff
+
+# CHECK: rmpupdate
+0xf2 0x0f 0x01 0xfe
+
+# CHECK: rmpadjust
+0xf3 0x0f 0x01 0xfe
+
 #CHECK: tdcall
 0x66 0x0f 0x01 0xcc
 
 # CHECK: hreset $1
 0xf3 0x0f 0x3a 0xf0 0xc0 0x01

llvm/test/MC/X86/SNP-32.s

+// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: pvalidate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xff]
+pvalidate
+
+// CHECK: pvalidate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xff]
+pvalidate %eax

llvm/test/MC/X86/SNP-64.s

+// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
+
+// CHECK: rmpupdate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xfe]
+rmpupdate
+
+// CHECK: psmash
+// CHECK: encoding: [0xf3,0x0f,0x01,0xff]
+psmash
+
+// CHECK: pvalidate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xff]
+pvalidate
+
+// CHECK: rmpadjust
+// CHECK: encoding: [0xf3,0x0f,0x01,0xfe]
+rmpadjust
+
+// CHECK: rmpupdate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xfe]
+rmpupdate %rax
+
+// CHECK: psmash
+// CHECK: encoding: [0xf3,0x0f,0x01,0xff]
+psmash %rax
+
+// CHECK: pvalidate
+// CHECK: encoding: [0xf2,0x0f,0x01,0xff]
+pvalidate %rax
+
+// CHECK: rmpadjust
+// CHECK: encoding: [0xf3,0x0f,0x01,0xfe]
+rmpadjust %rax

llvm/test/MC/X86/x86-32-coverage.s

 // CHECK:   mwaitx
 // CHECK:  encoding: [0x0f,0x01,0xfb]
           mwaitx %eax, %ecx, %ebx
 
 // CHECK:   clzero
 // CHECK:  encoding: [0x0f,0x01,0xfc]
           clzero
 
+// CHECK:   tlbsync 
+// CHECK:  encoding: [0x0f,0x01,0xff]
+          tlbsync
+
+// CHECK:   invlpgb
+// CHECK:  encoding: [0x0f,0x01,0xfe]
+          invlpgb %eax, %edx 
+
 // CHECK: lock addl %esi, (%edi)
 // INTEL: lock add dword ptr [edi], esi
 // CHECK:  encoding: [0xf0,0x01,0x37]
           lock add %esi, (%edi)
 
 // CHECK: cldemote 4(%eax)
 // CHECK:  encoding: [0x0f,0x1c,0x40,0x04]
           cldemote 4(%eax)

llvm/test/MC/X86/x86-32.s

 // CHECK:       clzero
 // CHECK:  encoding: [0x0f,0x01,0xfc]
                 clzero
 
 // CHECK:       clzero
 // CHECK:  encoding: [0x0f,0x01,0xfc]
                 clzero %eax
 
+// CHECK:       tlbsync 
+// CHECK:  encoding: [0x0f,0x01,0xff]
+                tlbsync
+
+// CHECK:       invlpgb
+// CHECK:  encoding: [0x0f,0x01,0xfe]
+                invlpgb %eax, %edx
+
 // radr://8017522
 // CHECK: wait
 // CHECK:  encoding: [0x9b]
   fwait
 
 // rdar://7873482
 // CHECK: [0x65,0xa1,0x7c,0x00,0x00,0x00]
         movl  %gs:124, %eax

llvm/test/MC/X86/x86-64.s

 // CHECK:       clzero
 // CHECK:  encoding: [0x0f,0x01,0xfc]
                 clzero
 
 // CHECK:       clzero
 // CHECK:  encoding: [0x0f,0x01,0xfc]
                 clzero %rax
 
+// CHECK:       tlbsync 
+// CHECK:  encoding: [0x0f,0x01,0xff]
+                tlbsync
+
+// CHECK:       invlpgb
+// CHECK:  encoding: [0x0f,0x01,0xfe]
+                invlpgb %rax, %edx 
+
 // CHECK:   movl %r15d, (%r15,%r15)
 // CHECK:  encoding: [0x47,0x89,0x3c,0x3f]
 movl %r15d, (%r15,%r15)
 
 // CHECK: nopq  3735928559(%rbx,%rcx,8)
 // CHECK:  encoding: [0x48,0x0f,0x1f,0x84,0xcb,0xef,0xbe,0xad,0xde]
 nopq  0xdeadbeef(%rbx,%rcx,8)