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[X86] Add TLBSYNC, INVLPGB and SNP instructions
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Authored by GGanesh on Jan 5 2021, 3:51 PM.

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Summary

This patch adds the AMD znver3 instructions INVLPGB, TLBSYNC and SNP. Tests are also added. These instructions needs to be included for znver3 features after adding Scheduler descriptions.

Diff Detail

Event Timeline

GGanesh created this revision.Jan 5 2021, 3:51 PM
GGanesh requested review of this revision.Jan 5 2021, 3:51 PM
craig.topper added inline comments.Jan 5 2021, 4:05 PM
llvm/lib/Target/X86/X86InstrInfo.td
965

These feature flags should probably only be here if intrinsics are added. Without that nothing will ever check the features.

2935

TB should be PS since we have XD and XS instructions that use the same opcode. TB is supposed to indicate that 0xf2/0xf3 prefixes don't effect the instruction.

2952

TB should be PS since we have XD and XS opcodes.

llvm/lib/Target/X86/X86InstrSNP.td
22

Should this have In64BitMode in the requires field?

36

Same here

41

And here

pengfei added inline comments.Jan 5 2021, 6:44 PM
llvm/test/MC/Disassembler/X86/x86-32.txt
1016–1020

Are they 64 bit only instructions?

GGanesh updated this revision to Diff 314823.Jan 6 2021, 1:53 AM

Updated the patch for the review comments from @craig.topper and @pengfei

  1. The instructions are updated for prefix specifiers
  2. Except for pvalidate all the SNP instructions are valid only in 64-bit environment. Corrected the test accordingly.
  3. The modes (In64BitMode, In64BitMode) are updated in Instruction description.
This revision is now accepted and ready to land.Jan 6 2021, 9:47 AM
This revision was automatically updated to reflect the committed changes.
GGanesh marked 6 inline comments as done.