[RISCV] Add vector mask arithmetic ISel patterns

[frasercrmck]

Summary

The patterns that want to use 'vnot' use a custom PatFrag. This is
because 'vnot' uses immAllOnesV which implicitly uses BUILD_VECTOR
rather than SPLAT_VECTOR.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

41

I couldn't find a way of using SplatPat here because it complained about using non-named inputs in a PatFrag. Is there a better way?

The best way to resolve this would be to fix OPC_CheckImmAllOnes but the link with BUILD_VECTOR goes quite deep and I can't find the best place to support SPLAT_VECTOR without introducing yet another function or moving functionality from isBuildVectorAllOnes into isConstantSplatVector, which I suspect will introduce a functionality change to many other targets.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

41

So to make some proposals more concrete to provide discussion (everything below also applies to all-zeros):

1. modify the immAllOnes SelectionDAGISel code to "inline" handle SPLAT_VECTOR

2. wrap isBuildVectorAllOnes and code that handles SPLAT_VECTOR in yet another function which is (currently) only called by the immAllOnes code.

3. defer isBuildVectorAllOnes to isConstantSplatVector when it sees ISD::SPLAT_VECTOR.

4. as above but rename isBuildVectorAllOnes to isConstantSplatAllOnes to show its new behaviour

Option 4 sounds best to me (because 1 and 2 aren't any good and 3 is half-hearted) but it remains to be seen how big the impact on other targets is. Any thoughts? My initial tests shows that vnot works and there's no obvious breakage in other targets.

And since that would affect other targets, would it be a separate patch after this one (replacing riscv_m_vnot with vnot to show that immAllOnes still works)?

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

41

I agree that option 4 sounds best, but a bulk change like that scares me due to the sheer number of places it is called.

One thought is to rename isBuildVectorAllOnes to isConstantSplatAllOnes, add a bool argument with a default that controls whether it looks at SPLAT_VECTOR. Add back a wrapper isBuildVectorAllOnes that just calls isConstantSplatAllOnes with SPLAT_VECTOR processing disabled. Then we don't have duplicate code and can migrate individual call sites with review and tests.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

41

I think your suggestion is a good way of getting this change in relatively atomically, allowing us to complete the work in a later patch.

can migrate individual call sites with review and tests

Last night I ran check-all with where we want to be (isBuildVectorAllOnes unconditionally handling splats) and it came back clean. If we were to follow through with that change, are we needing new tests to prove that SPLAT_VECTOR works in all existing cases isBuildVectorAllOnes is used? That sounds like the ideal situation but a lot of work, and I don't know how best to stress-test the SDAG like that, given that SPLAT_VECTOR is still quite the anomaly.

On the other hand, if the existing tests are enough then it should be a relatively quick follow-up. I'm just wary of introducing a "short-term" wrapper that we can't get rid of because we're unable to test all the code paths.

[craig.topper]

This patch LGTM. We can work on removing riscv_vnot as a follow up

[frasercrmck]

rebase onto main

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

 
 // Penalize the generic form with Complexity=1 to give the simm5/uimm5 variants
 // precedence
 def SplatPat       : ComplexPattern<vAny, 1, "selectVSplat", [], [], 1>;
 
 def SplatPat_simm5 : ComplexPattern<vAny, 1, "selectVSplatSimm5", []>;
 def SplatPat_uimm5 : ComplexPattern<vAny, 1, "selectVSplatUimm5", []>;
 
+// A mask-vector version of the standard 'vnot' fragment but using splat_vector
+// rather than (the implicit) build_vector
+def riscv_m_vnot : PatFrag<(ops node:$in),
+                           (xor node:$in, (splat_vector (XLenVT 1)))>;
+
 multiclass VPatUSLoadStoreSDNode<LLVMType type,
                                  LLVMType mask_type,
                                  int sew,
                                  LMULInfo vlmul,
                                  RegisterClass reg_rs1,
                                  VReg reg_class>
 {
   defvar load_instr = !cast<Instruction>("PseudoVLE"#sew#"_V_"#vlmul.MX);

 defm "" : VPatBinarySDNode_VV_VX<mulhu, "PseudoVMULHU">;
 
 // 12.11. Vector Integer Divide Instructions
 defm "" : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIVU">;
 defm "" : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIV">;
 defm "" : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
 defm "" : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
 
+// 16.1. Vector Mask-Register Logical Instructions
+foreach mti = AllMasks in {
+  def : Pat<(mti.Mask (and VR:$rs1, VR:$rs2)),
+            (!cast<Instruction>("PseudoVMAND_MM_"#mti.LMul.MX)
+                 VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
+  def : Pat<(mti.Mask (or VR:$rs1, VR:$rs2)),
+            (!cast<Instruction>("PseudoVMOR_MM_"#mti.LMul.MX)
+                 VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
+  def : Pat<(mti.Mask (xor VR:$rs1, VR:$rs2)),
+            (!cast<Instruction>("PseudoVMXOR_MM_"#mti.LMul.MX)
+                 VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
+
+  def : Pat<(mti.Mask (riscv_m_vnot (and VR:$rs1, VR:$rs2))),
+            (!cast<Instruction>("PseudoVMNAND_MM_"#mti.LMul.MX)
+                 VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
+  def : Pat<(mti.Mask (riscv_m_vnot (or VR:$rs1, VR:$rs2))),
+            (!cast<Instruction>("PseudoVMNOR_MM_"#mti.LMul.MX)
+                 VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
+  def : Pat<(mti.Mask (riscv_m_vnot (xor VR:$rs1, VR:$rs2))),
+            (!cast<Instruction>("PseudoVMXNOR_MM_"#mti.LMul.MX)
+                 VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
+
+  def : Pat<(mti.Mask (and VR:$rs1, (riscv_m_vnot VR:$rs2))),
+            (!cast<Instruction>("PseudoVMANDNOT_MM_"#mti.LMul.MX)
+                 VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
+  def : Pat<(mti.Mask (or VR:$rs1, (riscv_m_vnot VR:$rs2))),
+            (!cast<Instruction>("PseudoVMORNOT_MM_"#mti.LMul.MX)
+                 VR:$rs1, VR:$rs2, VLMax, mti.SEW)>;
+}
+
 } // Predicates = [HasStdExtV]
 
 //===----------------------------------------------------------------------===//
 // Vector Splats
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtV] in {
 foreach vti = AllIntegerVectors in {
   def : Pat<(vti.Vector (splat_vector GPR:$rs1)),
             (!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
               GPR:$rs1, VLMax, vti.SEW)>;
   def : Pat<(vti.Vector (splat_vector simm5:$rs1)),
             (!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
               simm5:$rs1, VLMax, vti.SEW)>;
 }
+
+foreach mti = AllMasks in {
+  def : Pat<(mti.Mask (splat_vector (XLenVT 1))),
+            (!cast<Instruction>("PseudoVMSET_M_"#mti.BX) VLMax, mti.SEW)>;
+  def : Pat<(mti.Mask (splat_vector (XLenVT 0))),
+            (!cast<Instruction>("PseudoVMCLR_M_"#mti.BX) VLMax, mti.SEW)>;
+}
 } // Predicates = [HasStdExtV]
 
 let Predicates = [HasStdExtV, IsRV32] in {
 foreach vti = AllIntegerVectors in {
   if !eq(vti.SEW, 64) then {
     def : Pat<(vti.Vector (rv32_splat_i64 GPR:$rs1)),
               (!cast<Instruction>("PseudoVMV_V_X_" # vti.LMul.MX)
                 GPR:$rs1, VLMax, vti.SEW)>;
     def : Pat<(vti.Vector (rv32_splat_i64 simm5:$rs1)),
               (!cast<Instruction>("PseudoVMV_V_I_" # vti.LMul.MX)
                 simm5:$rs1, VLMax, vti.SEW)>;
   }
 }
 } // Predicates = [HasStdExtV, IsRV32]

llvm/test/CodeGen/RISCV/rvv/vmarith-sdnode.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i1> @vmand_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
+; CHECK-LABEL: vmand_vv_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 1 x i1> %va, %vb
+  ret <vscale x 1 x i1> %vc
+}
+
+define <vscale x 2 x i1> @vmand_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
+; CHECK-LABEL: vmand_vv_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 2 x i1> %va, %vb
+  ret <vscale x 2 x i1> %vc
+}
+
+define <vscale x 4 x i1> @vmand_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
+; CHECK-LABEL: vmand_vv_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 4 x i1> %va, %vb
+  ret <vscale x 4 x i1> %vc
+}
+
+define <vscale x 8 x i1> @vmand_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
+; CHECK-LABEL: vmand_vv_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 8 x i1> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 16 x i1> @vmand_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
+; CHECK-LABEL: vmand_vv_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 16 x i1> %va, %vb
+  ret <vscale x 16 x i1> %vc
+}
+
+define <vscale x 1 x i1> @vmor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
+; CHECK-LABEL: vmor_vv_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 1 x i1> %va, %vb
+  ret <vscale x 1 x i1> %vc
+}
+
+define <vscale x 2 x i1> @vmor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
+; CHECK-LABEL: vmor_vv_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 2 x i1> %va, %vb
+  ret <vscale x 2 x i1> %vc
+}
+
+define <vscale x 4 x i1> @vmor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
+; CHECK-LABEL: vmor_vv_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 4 x i1> %va, %vb
+  ret <vscale x 4 x i1> %vc
+}
+
+define <vscale x 8 x i1> @vmor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
+; CHECK-LABEL: vmor_vv_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 8 x i1> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 16 x i1> @vmor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
+; CHECK-LABEL: vmor_vv_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 16 x i1> %va, %vb
+  ret <vscale x 16 x i1> %vc
+}
+
+define <vscale x 1 x i1> @vmxor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
+; CHECK-LABEL: vmxor_vv_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmxor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 1 x i1> %va, %vb
+  ret <vscale x 1 x i1> %vc
+}
+
+define <vscale x 2 x i1> @vmxor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
+; CHECK-LABEL: vmxor_vv_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmxor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 2 x i1> %va, %vb
+  ret <vscale x 2 x i1> %vc
+}
+
+define <vscale x 4 x i1> @vmxor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
+; CHECK-LABEL: vmxor_vv_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmxor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 4 x i1> %va, %vb
+  ret <vscale x 4 x i1> %vc
+}
+
+define <vscale x 8 x i1> @vmxor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
+; CHECK-LABEL: vmxor_vv_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmxor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 8 x i1> %va, %vb
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 16 x i1> @vmxor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
+; CHECK-LABEL: vmxor_vv_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmxor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 16 x i1> %va, %vb
+  ret <vscale x 16 x i1> %vc
+}
+
+define <vscale x 1 x i1> @vmnand_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
+; CHECK-LABEL: vmnand_vv_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmnand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 1 x i1> %va, %vb
+  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
+  %not = xor <vscale x 1 x i1> %vc, %splat
+  ret <vscale x 1 x i1> %not
+}
+
+define <vscale x 2 x i1> @vmnand_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
+; CHECK-LABEL: vmnand_vv_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmnand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 2 x i1> %va, %vb
+  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
+  %not = xor <vscale x 2 x i1> %vc, %splat
+  ret <vscale x 2 x i1> %not
+}
+
+define <vscale x 4 x i1> @vmnand_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
+; CHECK-LABEL: vmnand_vv_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmnand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 4 x i1> %va, %vb
+  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
+  %not = xor <vscale x 4 x i1> %vc, %splat
+  ret <vscale x 4 x i1> %not
+}
+
+define <vscale x 8 x i1> @vmnand_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
+; CHECK-LABEL: vmnand_vv_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmnand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 8 x i1> %va, %vb
+  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
+  %not = xor <vscale x 8 x i1> %vc, %splat
+  ret <vscale x 8 x i1> %not
+}
+
+define <vscale x 16 x i1> @vmnand_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
+; CHECK-LABEL: vmnand_vv_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmnand.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = and <vscale x 16 x i1> %va, %vb
+  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
+  %not = xor <vscale x 16 x i1> %vc, %splat
+  ret <vscale x 16 x i1> %not
+}
+
+define <vscale x 1 x i1> @vmnor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
+; CHECK-LABEL: vmnor_vv_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 1 x i1> %va, %vb
+  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
+  %not = xor <vscale x 1 x i1> %vc, %splat
+  ret <vscale x 1 x i1> %not
+}
+
+define <vscale x 2 x i1> @vmnor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
+; CHECK-LABEL: vmnor_vv_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 2 x i1> %va, %vb
+  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
+  %not = xor <vscale x 2 x i1> %vc, %splat
+  ret <vscale x 2 x i1> %not
+}
+
+define <vscale x 4 x i1> @vmnor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
+; CHECK-LABEL: vmnor_vv_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 4 x i1> %va, %vb
+  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
+  %not = xor <vscale x 4 x i1> %vc, %splat
+  ret <vscale x 4 x i1> %not
+}
+
+define <vscale x 8 x i1> @vmnor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
+; CHECK-LABEL: vmnor_vv_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 8 x i1> %va, %vb
+  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
+  %not = xor <vscale x 8 x i1> %vc, %splat
+  ret <vscale x 8 x i1> %not
+}
+
+define <vscale x 16 x i1> @vmnor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
+; CHECK-LABEL: vmnor_vv_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = or <vscale x 16 x i1> %va, %vb
+  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
+  %not = xor <vscale x 16 x i1> %vc, %splat
+  ret <vscale x 16 x i1> %not
+}
+
+define <vscale x 1 x i1> @vmxnor_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
+; CHECK-LABEL: vmxnor_vv_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmxnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 1 x i1> %va, %vb
+  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
+  %not = xor <vscale x 1 x i1> %vc, %splat
+  ret <vscale x 1 x i1> %not
+}
+
+define <vscale x 2 x i1> @vmxnor_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
+; CHECK-LABEL: vmxnor_vv_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmxnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 2 x i1> %va, %vb
+  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
+  %not = xor <vscale x 2 x i1> %vc, %splat
+  ret <vscale x 2 x i1> %not
+}
+
+define <vscale x 4 x i1> @vmxnor_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
+; CHECK-LABEL: vmxnor_vv_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmxnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 4 x i1> %va, %vb
+  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
+  %not = xor <vscale x 4 x i1> %vc, %splat
+  ret <vscale x 4 x i1> %not
+}
+
+define <vscale x 8 x i1> @vmxnor_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
+; CHECK-LABEL: vmxnor_vv_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmxnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 8 x i1> %va, %vb
+  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
+  %not = xor <vscale x 8 x i1> %vc, %splat
+  ret <vscale x 8 x i1> %not
+}
+
+define <vscale x 16 x i1> @vmxnor_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
+; CHECK-LABEL: vmxnor_vv_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmxnor.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %vc = xor <vscale x 16 x i1> %va, %vb
+  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
+  %not = xor <vscale x 16 x i1> %vc, %splat
+  ret <vscale x 16 x i1> %not
+}
+
+define <vscale x 1 x i1> @vmandnot_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
+; CHECK-LABEL: vmandnot_vv_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmandnot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
+  %not = xor <vscale x 1 x i1> %vb, %splat
+  %vc = and <vscale x 1 x i1> %va, %not
+  ret <vscale x 1 x i1> %vc
+}
+
+define <vscale x 2 x i1> @vmandnot_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
+; CHECK-LABEL: vmandnot_vv_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmandnot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
+  %not = xor <vscale x 2 x i1> %vb, %splat
+  %vc = and <vscale x 2 x i1> %va, %not
+  ret <vscale x 2 x i1> %vc
+}
+
+define <vscale x 4 x i1> @vmandnot_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
+; CHECK-LABEL: vmandnot_vv_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmandnot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
+  %not = xor <vscale x 4 x i1> %vb, %splat
+  %vc = and <vscale x 4 x i1> %va, %not
+  ret <vscale x 4 x i1> %vc
+}
+
+define <vscale x 8 x i1> @vmandnot_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
+; CHECK-LABEL: vmandnot_vv_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmandnot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
+  %not = xor <vscale x 8 x i1> %vb, %splat
+  %vc = and <vscale x 8 x i1> %va, %not
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 16 x i1> @vmandnot_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
+; CHECK-LABEL: vmandnot_vv_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmandnot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
+  %not = xor <vscale x 16 x i1> %vb, %splat
+  %vc = and <vscale x 16 x i1> %va, %not
+  ret <vscale x 16 x i1> %vc
+}
+
+define <vscale x 1 x i1> @vmornot_vv_nxv1i1(<vscale x 1 x i1> %va, <vscale x 1 x i1> %vb) {
+; CHECK-LABEL: vmornot_vv_nxv1i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmornot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
+  %not = xor <vscale x 1 x i1> %vb, %splat
+  %vc = or <vscale x 1 x i1> %va, %not
+  ret <vscale x 1 x i1> %vc
+}
+
+define <vscale x 2 x i1> @vmornot_vv_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %vb) {
+; CHECK-LABEL: vmornot_vv_nxv2i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmornot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
+  %not = xor <vscale x 2 x i1> %vb, %splat
+  %vc = or <vscale x 2 x i1> %va, %not
+  ret <vscale x 2 x i1> %vc
+}
+
+define <vscale x 4 x i1> @vmornot_vv_nxv4i1(<vscale x 4 x i1> %va, <vscale x 4 x i1> %vb) {
+; CHECK-LABEL: vmornot_vv_nxv4i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmornot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
+  %not = xor <vscale x 4 x i1> %vb, %splat
+  %vc = or <vscale x 4 x i1> %va, %not
+  ret <vscale x 4 x i1> %vc
+}
+
+define <vscale x 8 x i1> @vmornot_vv_nxv8i1(<vscale x 8 x i1> %va, <vscale x 8 x i1> %vb) {
+; CHECK-LABEL: vmornot_vv_nxv8i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmornot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
+  %not = xor <vscale x 8 x i1> %vb, %splat
+  %vc = or <vscale x 8 x i1> %va, %not
+  ret <vscale x 8 x i1> %vc
+}
+
+define <vscale x 16 x i1> @vmornot_vv_nxv16i1(<vscale x 16 x i1> %va, <vscale x 16 x i1> %vb) {
+; CHECK-LABEL: vmornot_vv_nxv16i1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmornot.mm v0, v0, v16
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i1> undef, i1 1, i32 0
+  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
+  %not = xor <vscale x 16 x i1> %vb, %splat
+  %vc = or <vscale x 16 x i1> %va, %not
+  ret <vscale x 16 x i1> %vc
+}
+

llvm/test/CodeGen/RISCV/rvv/vsplats-i1.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
+
+define <vscale x 1 x i1> @vsplat_nxv1i1_0() {
+; CHECK-LABEL: vsplat_nxv1i1_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i1> undef, i1 0, i32 0
+  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
+  ret <vscale x 1 x i1> %splat
+}
+
+define <vscale x 1 x i1> @vsplat_nxv1i1_1() {
+; CHECK-LABEL: vsplat_nxv1i1_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf8,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 1 x i1> undef, i1 -1, i32 0
+  %splat = shufflevector <vscale x 1 x i1> %head, <vscale x 1 x i1> undef, <vscale x 1 x i32> zeroinitializer
+  ret <vscale x 1 x i1> %splat
+}
+
+define <vscale x 2 x i1> @vsplat_nxv2i1_0() {
+; CHECK-LABEL: vsplat_nxv2i1_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i1> undef, i1 0, i32 0
+  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
+  ret <vscale x 2 x i1> %splat
+}
+
+define <vscale x 2 x i1> @vsplat_nxv2i1_1() {
+; CHECK-LABEL: vsplat_nxv2i1_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf4,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 2 x i1> undef, i1 -1, i32 0
+  %splat = shufflevector <vscale x 2 x i1> %head, <vscale x 2 x i1> undef, <vscale x 2 x i32> zeroinitializer
+  ret <vscale x 2 x i1> %splat
+}
+
+define <vscale x 4 x i1> @vsplat_nxv4i1_0() {
+; CHECK-LABEL: vsplat_nxv4i1_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i1> undef, i1 0, i32 0
+  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
+  ret <vscale x 4 x i1> %splat
+}
+
+define <vscale x 4 x i1> @vsplat_nxv4i1_1() {
+; CHECK-LABEL: vsplat_nxv4i1_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,mf2,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 4 x i1> undef, i1 -1, i32 0
+  %splat = shufflevector <vscale x 4 x i1> %head, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
+  ret <vscale x 4 x i1> %splat
+}
+
+define <vscale x 8 x i1> @vsplat_nxv8i1_0() {
+; CHECK-LABEL: vsplat_nxv8i1_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i1> undef, i1 0, i32 0
+  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i1> %splat
+}
+
+define <vscale x 8 x i1> @vsplat_nxv8i1_1() {
+; CHECK-LABEL: vsplat_nxv8i1_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m1,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 8 x i1> undef, i1 -1, i32 0
+  %splat = shufflevector <vscale x 8 x i1> %head, <vscale x 8 x i1> undef, <vscale x 8 x i32> zeroinitializer
+  ret <vscale x 8 x i1> %splat
+}
+
+define <vscale x 16 x i1> @vsplat_nxv16i1_0() {
+; CHECK-LABEL: vsplat_nxv16i1_0:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmclr.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i1> undef, i1 0, i32 0
+  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
+  ret <vscale x 16 x i1> %splat
+}
+
+define <vscale x 16 x i1> @vsplat_nxv16i1_1() {
+; CHECK-LABEL: vsplat_nxv16i1_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetvli a0, zero, e8,m2,ta,mu
+; CHECK-NEXT:    vmset.m v0
+; CHECK-NEXT:    ret
+  %head = insertelement <vscale x 16 x i1> undef, i1 -1, i32 0
+  %splat = shufflevector <vscale x 16 x i1> %head, <vscale x 16 x i1> undef, <vscale x 16 x i32> zeroinitializer
+  ret <vscale x 16 x i1> %splat
+}