[AMDGPU] Remove deprecated V_MUL_LO_I32 from GFX10

[Joe_Nash]

Summary

It was removed in GFX10 GPUs, but LLVM could
generate it.

[rampitec]

Generally speaking it is deprecated but it is supported. Well, not in gfx1030.

[arsenm]

Should the disassembler still understand it?

[rampitec]

In D94020#2477666, @arsenm wrote:

Should the disassembler still understand it?

I think we need to remove it from gfx1030+ only (e.g. !FeatureGFX10_3Insts).

[Joe_Nash]

remove inst from gfx1030 only, instead of all gfx10

[rampitec]

llvm/lib/Target/AMDGPU/AMDGPU.td

1137 ↗

(On Diff #314479)

Please use GFX10_3Insts, not encoding.

[Joe_Nash]

changed B_encoding predicate to be 10_3Insts

[rampitec]

LGTM

llvm/lib/Target/AMDGPU/VOP3Instructions.td

multiclass VOP3_Real_gfx6_gfx7_gfx10<bits<10> op> :
   VOP3_Real_gfx6_gfx7<op>, VOP3_Real_gfx10<op>;
 
 multiclass VOP3be_Real_gfx6_gfx7_gfx10<bits<10> op> :
   VOP3be_Real_gfx6_gfx7<op>, VOP3be_Real_gfx10<op>;
 
 defm V_LSHL_B64        : VOP3_Real_gfx6_gfx7<0x161>;
 defm V_LSHR_B64        : VOP3_Real_gfx6_gfx7<0x162>;
 defm V_ASHR_I64        : VOP3_Real_gfx6_gfx7<0x163>;
+defm V_MUL_LO_I32      : VOP3_Real_gfx6_gfx7<0x16b>;
 
 defm V_MAD_LEGACY_F32  : VOP3_Real_gfx6_gfx7_gfx10<0x140>;
 defm V_MAD_F32         : VOP3_Real_gfx6_gfx7_gfx10<0x141>;
 defm V_MAD_I32_I24     : VOP3_Real_gfx6_gfx7_gfx10<0x142>;
 defm V_MAD_U32_U24     : VOP3_Real_gfx6_gfx7_gfx10<0x143>;
 defm V_CUBEID_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x144>;
 defm V_CUBESC_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x145>;
 defm V_CUBETC_F32      : VOP3_Real_gfx6_gfx7_gfx10<0x146>;

 defm V_DIV_FIXUP_F64   : VOP3_Real_gfx6_gfx7_gfx10<0x160>;
 defm V_ADD_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x164>;
 defm V_MUL_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x165>;
 defm V_MIN_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x166>;
 defm V_MAX_F64         : VOP3_Real_gfx6_gfx7_gfx10<0x167>;
 defm V_LDEXP_F64       : VOP3_Real_gfx6_gfx7_gfx10<0x168>;
 defm V_MUL_LO_U32      : VOP3_Real_gfx6_gfx7_gfx10<0x169>;
 defm V_MUL_HI_U32      : VOP3_Real_gfx6_gfx7_gfx10<0x16a>;
-defm V_MUL_LO_I32      : VOP3_Real_gfx6_gfx7_gfx10<0x16b>;
 defm V_MUL_HI_I32      : VOP3_Real_gfx6_gfx7_gfx10<0x16c>;
 defm V_DIV_FMAS_F32    : VOP3_Real_gfx6_gfx7_gfx10<0x16f>;
 defm V_DIV_FMAS_F64    : VOP3_Real_gfx6_gfx7_gfx10<0x170>;
 defm V_MSAD_U8         : VOP3_Real_gfx6_gfx7_gfx10<0x171>;
 defm V_MQSAD_PK_U16_U8 : VOP3_Real_gfx6_gfx7_gfx10<0x173>;
 defm V_TRIG_PREOP_F64  : VOP3_Real_gfx6_gfx7_gfx10<0x174>;
 defm V_DIV_SCALE_F32   : VOP3be_Real_gfx6_gfx7_gfx10<0x16d>;
 defm V_DIV_SCALE_F64   : VOP3be_Real_gfx6_gfx7_gfx10<0x16e>;

llvm/test/MC/AMDGPU/gfx10_unsupported.s

 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_min_legacy_f32 v255, v1, v2
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_min_legacy_f32_e64 v255, v1, v2
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
+v_mul_lo_i32 v0, v1, v2
+// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
+
 v_rcp_clamp_f32 v255, v1
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rcp_clamp_f32_e64 v255, v1
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
 
 v_rcp_clamp_f64 v[254:255], v[1:2]
 // CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU